• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 99 subscribers
  • Views 363 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM625: Ethernet Backup Boot

Alexander Sverdlin
Prodigy 60 points
Part Number: AM625


Dear TI Engineers!

Could you please clarify couple of uncertainties I still have after reading AM625 TRM (SPRUIV7) (or point me to the relevant documentation)?

1. BOOTMODE13 in Ethernet Backup Boot mode selects between SGMI and RMII. However, when configured as primary boot mode, SGMII comes in two flavours: BOOTMODE7==0 (MDIO PHY scan) and BOOTMODE7==1, "Link parameters programmed by the ROM" (would be nice to have this documented as well). Which flavour is used when SGMII is Backup Boot mode? MDIO PHY scan or the hardcoded one?

2. BOOTMODE13==1 is RMII, which in case of primary boot mode only does "MDIO PHY scan". Let's assume it's the case for RMII in backup mode case. But what is the algorithm for this scan and what are the requirements for the PHY MDIO addresses? Can we design multiple PHY chips on the bus, which addresses will be used? Is it possible to have hardcoded link parameters in RMII case (similar to RGMII) so that BootROM doesn't require MDIO access?

It could be that I've missed some existing documentation or parts of it... Any pointers appreciated!

--

Alexander.

  • 0
    TI__Mastermind 40310 points

    Hi,

    For question 1 I need to highlight that RGMII is supported, not SGMII. The Link info when to 1 or programmed by ROM means that this is a fixed link mode. In this mode the ROM will set the interface to RGMII mode full duplex at 1G. The MDIO bus is used, the ROM assumes the PHY is HW configured for this mode and has a link partner that is connected at 1G. Any link partner other this speed and duplex mode will fail. Section 5.4.5.1.1 Ethernet Initialization Process of the TRM covers this area.

    Please note there is an errata i2329 MDIO: MDIO interface corruption (CPSW and PRU-ICSS) which recommends that Ethernet boot is not recommended. Some users have been using this mode for initial device programming, is that your use case?

    On question 2 to my knowledge there is a designated PHY address which I believe is address 0. Unfortunately I can't find this either in the TRM. I will have to check on this and get back to you. The TI EVM has multiple PHYs on the same MDIO bus.

    Best Regards,

    Schuyler

  • 0 in reply to Schuyler Patton
    Prodigy 60 points

    Thanks for quick reply Schuyler!
    Sorry, SGMII was really a typo on my side, surely I've referred to RGMII.

    It would be nice to get more info on PHY Scan algorithm, because seems that am335x had this a bit more documented, with "In dual-port configurations, the ROM code assumes that the Ethernet PHY with the lowest MDIO
    address (0-31) is connected to CPGMAC port 1" in TRM, for am64x there is a e2e post here:
    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1345457/am6411-am64x-boot-over-ethernet-on-custom-board-how-mdio-scan-with-multiple-phy-on-the-same-mdio-bus

    But it's not referring any document, only some internal verbal communication and a proposal to find out empirically.

    It would be nice to clarify and document this topic because we are trying to interface am625 to multiple different Ethernet switches, some of them can emulate PHY chips, others cannot, but as we try to go beyond the simple MAC-PHY setup similar to TI evalboards, it makes it harder to figure out things empirically.

    Thank you and best regards!

  • 0 in reply to Alexander Sverdlin
    TI__Mastermind 40310 points

    Hi,

    I discussed the question with the ROM team and what you are describing is accurate. The ROM code will take the lowest addressed PHY and assume it is attached to the first Ethernet port. The ROM code will use the MDIO Alive register to find the lowest addressed PHY. After the PHY is detected the ROM will force auto-neg to establish a link. Once the link is detected the boot process begins.

    Please note the ROM will only be setting up one interface, a dual port configuration is not configured by the ROM. 

    Please also note that once out of the ROM code the MDIO module for this device is used in manual mode which means that the scan is done by a bit bang technique to satisfy the errata mentioned earlier.

    Best Regards,

    Schuyler