TDA4VM: SerDes with 1 Lane

Hi Marina,

Could you share with me the following:

• Which SDK version is being used. For example, PROCESSOR-SDK-LINUX-J721E 09.02.00.05 is currently the latest Linux SDK version
• What changes are done for enabling only Lane 0.
• What changes are done for enabling both lanes.

For context, the purpose of these questions is to see if we can replicate the issue on TI EVM. 

Regards,

Takuma

Hi Marina,

I also see the other thread over PCIe: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1360785/tda4vm-serdes-filter-coefficients

Is this all using the PDK implementation? Or is this Linux?

Regards,

Takuma

Hello Takuma,

yes, we are implementing everything baremetal without Linux.

The steps that I use to configure the lanes are the following (for only lane 0, I only configure LANECTL0):

1) Disable lane 0 and 1 by cleaning LANECTL0::P0_ENABLE (Offset 480h, bits 30-31) and LANECTL1::P0_ENABLE (Offset 4C0h, bits 30-31)

    Reference from TI PDK:  void CSL_serdesDisablePllAndLanes(uint32_t baseAddr, uint32_t numLanes, uint8_t laneMask) in csl_serdes3.c

2) Select Serdes PCIe Mode on lane 0 and 1 by setting LANECTL0::P0_STANDARD_MODE(Offset 480h, bits 24-25) and  LANECTL1::P0_STANDARD_MODE (Offset 4C0h, bits 24-25) as 2 (PCIe Gen 3)

    Reference from TI PDK: void CSL_serdesPCIeModeSelect(uint32_t baseAddr, CSL_SerdesPCIeGenType pcieGenType, uint32_t laneNum) in in csl_serdes3.c

3) Enable Serdes Lane 0 and Lane 1 by setting LANECTL0::P0_ENABLE(Offset 480h, bit 31) and  LANECTL1::P0_ENABLE(Offset 4C0h, bit 31)

    Reference from TI PDK: CSL_SerdesLaneEnableStatus CSL_serdesLaneEnable(CSL_SerdesLaneEnableParams *serdesLaneEnableParams) in in csl_serdes3.c

Regards,

Marina

Hi Marina,

Understood. As mentioned in the other thread, I am putting in a disclaimer that the PDK implementation of PCIe driver has been descoped. Most likely there are some issues that have been found and fixed in Linux driver through SDK 8.x and 9.x versions that are not in PDK. As such, I would recommend using the Linux driver if possible. If not possible, then next recommendation would be to use the Linux driver as reference.

Now, getting back to the issue... when configuring the lanes, the Linux driver has an option for UNUSED, and it is configured in device tree like the following:

• https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/include/dt-bindings/mux/ti-serdes.h?h=ti-linux-6.1.y
• https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts?h=ti-linux-6.1.y#n494

- So it could be that there is a value that explicitly needs to be set for unused lanes that the PDK driver is not initializing.

Otherwise, I see a function who's description is that it configures the serdes module for PCIe, but it looks to be configuring for SGMII/QSGMII:

And I see that PCIe + QSGMII multilink configuration in board_serdes_cfg.c file within PDK is the only configuration that sets phyType to PCIe:

- So it could be that PCIe is only getting configured when it detects multilink, which could explain why PCIe is only coming up when configuring multiple lanes. Unless you have developed a new function that configures phyType for PCIe for a single link.

Regards,

Takuma