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Original question:

TDA4VE-Q1: Power-down sequence

TDA4VM-Q1: TDA4 Power-off sequence

jingle.lan
Prodigy 120 points
Part Number: TDA4VM-Q1
Other Parts Discussed in Thread: TDA4VM

Hi ：

May I ask the power-off timing of TDA4VM? For example, the power supply DDR:VDD1 starts power-off at 3ms, does the voltage need to drop to 0V before 3.5ms? There are more capacitors in the actual power supply, and the power supply voltage cannot be dropped completely within 500us in the power-off timing we tested.

For example, in the timing of the data sheet, the Core power starts to drop at T2, but the capacitance of the Core power is very large, and the Core voltage must not fall to 0V at 3ms, so does this meet the requirements of the power-off timing?

     

  • 0
    TI__Expert 6965 points

    1. The only specific requirement for power down sequence is described by "Note #10" (shown below) which states MCU_PORz and PORz msut be asserted low at least 200us before any SoC voltage begins to ramp down.

  • 0 in reply to Bill McCracken
    Intellectual 540 points

    Bill,

    So no requirement for slew rate of ramp-down? For example, a power rail with power down time stamp T1 doesn't need to fall below a specific voltage level at T2(let's assum it is the the time the next voltage rail group starts ramp-down, considering my next question)?

    If the only specific requirement for power down sequence is described by "Note #10", what about the Time Stamp Markers? For example, a power rail with power down time stamp T2 must start ramp-down between T2 and T3, or at exactly T2, or possibly before T2 as long as it starts ramp-down after power rails with power down time stamp T1? Which one is correct?

  • 0 in reply to Zehui Li
    TI__Genius 9520 points

    Since there is no activity for more than 6 months, please let us know whether this is still a problem.

    Br, Tommy

  • 0 in reply to TommySong
    Intellectual 540 points

    Hi Tommy，

    We did not found any issues about it during use, but since this involves testing standards, it is best to provide a definitive conclusion. Due to the presence of caps at each power rail, the real waveform is different from what is shown in the figure.

  • 0 in reply to Zehui Li
    TI__Expert 6440 points

    Hi Zehui,

    So regarding the power down, you need make sure the MCU_PORz and PORz assert down at least 200us, this is the only specific requirement for SOC then the Soc will be in safe state, then you can power down as the PDN, but this is not the must requirements. you don't need follow the waveform in strict compliance. it can be flexible.

    BR,

    Biao