Part Number: TDA4VM
Hello Champs ,
I am trying to run a custom model and i am getting the following error please find the following logs and debug
Settings :
SDK : 9.2.7
Docker
Mode : Compilation
root@397074ad6dc3:/home/root/examples/osrt_python/ort# python3 onnxrt_ep_dock927_condlanet_fp32.py -c
Available execution providers : ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider']
Running 1 Models - ['condlanet_org']
Running_Model : condlanet_org
Running shape inference on model /home/root/lucid/model_onnx/condlanettest.onnx
***** WARNING : tensor_bits = 32 -- Compiling for floating point - target execution is not supported for 32 bit compilation !! *****
tidl_tools_path = /home/root/tidl_tools
artifacts_folder = ../../../model-artifacts//condlanet_org/
tidl_tensor_bits = 32
debug_level = 6
num_tidl_subgraphs = 16
tidl_denylist = Div Gather
tidl_denylist_layer_name =
tidl_denylist_layer_type =
tidl_allowlist_layer_name =
model_type =
tidl_calibration_accuracy_level = 64
tidl_calibration_options:num_frames_calibration = 3
tidl_calibration_options:bias_calibration_iterations = 3
mixed_precision_factor = -1.000000
model_group_id = 0
power_of_2_quantization = 2
ONNX QDQ Enabled = 0
enable_high_resolution_optimization = 0
pre_batchnorm_fold = 1
add_data_convert_ops = 0
output_feature_16bit_names_list =
m_params_16bit_names_list =
m_single_core_layers_names_list =
reserved_compile_constraints_flag = 1601
ti_internal_reserved_1 =
WARNING : 'meta_layers_names_list' is not provided - running OD post processing in ARM mode
Number of OD backbone nodes = 0
Size of odBackboneNodeIds = 0
Layer 0 -- layer name -- Conv_0
Input dims size = 4 dims --- 1 3 320 800
Supported TIDL layer type --- Conv -- Conv_0
Layer 1 -- layer name -- Relu_1
Input dims size = 4 dims --- 1 64 160 400
Supported TIDL layer type --- Relu -- Relu_1
Layer 2 -- layer name -- MaxPool_2
Input dims size = 4 dims --- 1 64 160 400
Supported TIDL layer type --- MaxPool -- MaxPool_2
Layer 3 -- layer name -- Conv_3
Input dims size = 4 dims --- 1 64 80 200
Supported TIDL layer type --- Conv -- Conv_3
Layer 4 -- layer name -- Relu_4
Input dims size = 4 dims --- 1 64 80 200
Supported TIDL layer type --- Relu -- Relu_4
Layer 5 -- layer name -- Conv_5
Input dims size = 4 dims --- 1 64 80 200
Supported TIDL layer type --- Conv -- Conv_5
Layer 6 -- layer name -- Add_6
Input dims size = 4 dims --- 1 64 80 200
Supported TIDL layer type --- Add -- Add_6
Layer 7 -- layer name -- Relu_7
Input dims size = 4 dims --- 1 64 80 200
Supported TIDL layer type --- Relu -- Relu_7
Layer 8 -- layer name -- Conv_8
Input dims size = 4 dims --- 1 64 80 200
Supported TIDL layer type --- Conv -- Conv_8
Layer 9 -- layer name -- Relu_9
Input dims size = 4 dims --- 1 64 80 200
Supported TIDL layer type --- Relu -- Relu_9
Layer 10 -- layer name -- Conv_10
Input dims size = 4 dims --- 1 64 80 200
Supported TIDL layer type --- Conv -- Conv_10
Layer 11 -- layer name -- Add_11
Input dims size = 4 dims --- 1 64 80 200
Supported TIDL layer type --- Add -- Add_11
Layer 12 -- layer name -- Relu_12
Input dims size = 4 dims --- 1 64 80 200
Supported TIDL layer type --- Relu -- Relu_12
Layer 13 -- layer name -- Conv_13
Input dims size = 4 dims --- 1 64 80 200
Supported TIDL layer type --- Conv -- Conv_13
Layer 14 -- layer name -- Relu_14
Input dims size = 4 dims --- 1 128 40 100
Supported TIDL layer type --- Relu -- Relu_14
Layer 15 -- layer name -- Conv_15
Input dims size = 4 dims --- 1 128 40 100
Supported TIDL layer type --- Conv -- Conv_15
Layer 16 -- layer name -- Conv_16
Input dims size = 4 dims --- 1 64 80 200
Supported TIDL layer type --- Conv -- Conv_16
Layer 17 -- layer name -- Add_17
Input dims size = 4 dims --- 1 128 40 100
Supported TIDL layer type --- Add -- Add_17
Layer 18 -- layer name -- Relu_18
Input dims size = 4 dims --- 1 128 40 100
Supported TIDL layer type --- Relu -- Relu_18
Layer 19 -- layer name -- Conv_19
Input dims size = 4 dims --- 1 128 40 100
Supported TIDL layer type --- Conv -- Conv_19
Layer 20 -- layer name -- Relu_20
Input dims size = 4 dims --- 1 128 40 100
Supported TIDL layer type --- Relu -- Relu_20
Layer 21 -- layer name -- Conv_21
Input dims size = 4 dims --- 1 128 40 100
Supported TIDL layer type --- Conv -- Conv_21
Layer 22 -- layer name -- Add_22
Input dims size = 4 dims --- 1 128 40 100
Supported TIDL layer type --- Add -- Add_22
Layer 23 -- layer name -- Relu_23
Input dims size = 4 dims --- 1 128 40 100
Supported TIDL layer type --- Relu -- Relu_23
Layer 24 -- layer name -- Conv_24
Input dims size = 4 dims --- 1 128 40 100
Supported TIDL layer type --- Conv -- Conv_24
Layer 25 -- layer name -- Relu_25
Input dims size = 4 dims --- 1 256 20 50
Supported TIDL layer type --- Relu -- Relu_25
Layer 26 -- layer name -- Conv_26
Input dims size = 4 dims --- 1 256 20 50
Supported TIDL layer type --- Conv -- Conv_26
Layer 27 -- layer name -- Conv_27
Input dims size = 4 dims --- 1 128 40 100
Supported TIDL layer type --- Conv -- Conv_27
Layer 28 -- layer name -- Add_28
Input dims size = 4 dims --- 1 256 20 50
Supported TIDL layer type --- Add -- Add_28
Layer 29 -- layer name -- Relu_29
Input dims size = 4 dims --- 1 256 20 50
Supported TIDL layer type --- Relu -- Relu_29
Layer 30 -- layer name -- Conv_30
Input dims size = 4 dims --- 1 256 20 50
Supported TIDL layer type --- Conv -- Conv_30
Layer 31 -- layer name -- Relu_31
Input dims size = 4 dims --- 1 256 20 50
Supported TIDL layer type --- Relu -- Relu_31
Layer 32 -- layer name -- Conv_32
Input dims size = 4 dims --- 1 256 20 50
Supported TIDL layer type --- Conv -- Conv_32
Layer 33 -- layer name -- Add_33
Input dims size = 4 dims --- 1 256 20 50
Supported TIDL layer type --- Add -- Add_33
Layer 34 -- layer name -- Relu_34
Input dims size = 4 dims --- 1 256 20 50
Supported TIDL layer type --- Relu -- Relu_34
Layer 35 -- layer name -- Conv_35
Input dims size = 4 dims --- 1 256 20 50
Supported TIDL layer type --- Conv -- Conv_35
Layer 36 -- layer name -- Relu_36
Input dims size = 4 dims --- 1 512 10 25
Supported TIDL layer type --- Relu -- Relu_36
Layer 37 -- layer name -- Conv_37
Input dims size = 4 dims --- 1 512 10 25
Supported TIDL layer type --- Conv -- Conv_37
Layer 38 -- layer name -- Conv_38
Input dims size = 4 dims --- 1 256 20 50
Supported TIDL layer type --- Conv -- Conv_38
Layer 39 -- layer name -- Add_39
Input dims size = 4 dims --- 1 512 10 25
Supported TIDL layer type --- Add -- Add_39
Layer 40 -- layer name -- Relu_40
Input dims size = 4 dims --- 1 512 10 25
Supported TIDL layer type --- Relu -- Relu_40
Layer 41 -- layer name -- Conv_41
Input dims size = 4 dims --- 1 512 10 25
Supported TIDL layer type --- Conv -- Conv_41
Layer 42 -- layer name -- Relu_42
Input dims size = 4 dims --- 1 512 10 25
Supported TIDL layer type --- Relu -- Relu_42
Layer 43 -- layer name -- Conv_43
Input dims size = 4 dims --- 1 512 10 25
Supported TIDL layer type --- Conv -- Conv_43
Layer 44 -- layer name -- Add_44
Input dims size = 4 dims --- 1 512 10 25
Supported TIDL layer type --- Add -- Add_44
Layer 45 -- layer name -- Relu_45
Input dims size = 4 dims --- 1 512 10 25
Supported TIDL layer type --- Relu -- Relu_45
Layer 46 -- layer name -- Conv_46
Input dims size = 4 dims --- 1 512 10 25
Supported TIDL layer type --- Conv -- Conv_46
Layer 47 -- layer name -- Relu_47
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Relu -- Relu_47
Layer 48 -- layer name -- Add_58
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Add -- Add_58
Layer 49 -- layer name -- Conv_59
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Conv -- Conv_59
Layer 50 -- layer name -- Reshape_64
Input dims size = 4 dims --- 1 16 10 25
Supported TIDL layer type --- Reshape -- Reshape_64
Layer 51 -- layer name -- Transpose_65
Input dims size = 3 dims --- 1 16 250
Supported TIDL layer type --- Transpose -- Transpose_65
Layer 52 -- layer name -- Conv_66
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Conv -- Conv_66
Layer 53 -- layer name -- Reshape_71
Input dims size = 4 dims --- 1 16 10 25
Supported TIDL layer type --- Reshape -- Reshape_71
Layer 54 -- layer name -- MatMul_72
Input dims size = 3 dims --- 1 250 16
Supported TIDL layer type --- MatMul -- MatMul_72
Layer 55 -- layer name -- Softmax_73
Input dims size = 3 dims --- 1 250 250
Supported TIDL layer type --- Softmax -- Softmax_73
Layer 56 -- layer name -- Transpose_74
Input dims size = 3 dims --- 1 250 250
Supported TIDL layer type --- Transpose -- Transpose_74
Layer 57 -- layer name -- Conv_75
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Conv -- Conv_75
Layer 58 -- layer name -- Reshape_80
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Reshape -- Reshape_80
Layer 59 -- layer name -- MatMul_81
Input dims size = 3 dims --- 1 64 250
Supported TIDL layer type --- MatMul -- MatMul_81
Layer 60 -- layer name -- Reshape_86
Input dims size = 3 dims --- 1 64 250
Supported TIDL layer type --- Reshape -- Reshape_86
Layer 61 -- layer name -- custom_added_Mul0
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Mul -- custom_added_Mul0
Layer 62 -- layer name -- Add_88
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Add -- Add_88
Layer 63 -- layer name -- Conv_89
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Conv -- Conv_89
Layer 64 -- layer name -- Relu_90
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Relu -- Relu_90
Layer 65 -- layer name -- Conv_91
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Conv -- Conv_91
Layer 66 -- layer name -- Relu_92
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Relu -- Relu_92
Layer 67 -- layer name -- Add_103
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Add -- Add_103
Layer 68 -- layer name -- Conv_104
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Conv -- Conv_104
Layer 69 -- layer name -- Reshape_109
Input dims size = 4 dims --- 1 16 10 25
Supported TIDL layer type --- Reshape -- Reshape_109
Layer 70 -- layer name -- Transpose_110
Input dims size = 3 dims --- 1 16 250
Supported TIDL layer type --- Transpose -- Transpose_110
Layer 71 -- layer name -- Conv_111
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Conv -- Conv_111
Layer 72 -- layer name -- Reshape_116
Input dims size = 4 dims --- 1 16 10 25
Supported TIDL layer type --- Reshape -- Reshape_116
Layer 73 -- layer name -- MatMul_117
Input dims size = 3 dims --- 1 250 16
Supported TIDL layer type --- MatMul -- MatMul_117
Layer 74 -- layer name -- Softmax_118
Input dims size = 3 dims --- 1 250 250
Supported TIDL layer type --- Softmax -- Softmax_118
Layer 75 -- layer name -- Transpose_119
Input dims size = 3 dims --- 1 250 250
Supported TIDL layer type --- Transpose -- Transpose_119
Layer 76 -- layer name -- Conv_120
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Conv -- Conv_120
Layer 77 -- layer name -- Reshape_125
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Reshape -- Reshape_125
Layer 78 -- layer name -- MatMul_126
Input dims size = 3 dims --- 1 64 250
Supported TIDL layer type --- MatMul -- MatMul_126
Layer 79 -- layer name -- Reshape_131
Input dims size = 3 dims --- 1 64 250
Supported TIDL layer type --- Reshape -- Reshape_131
Layer 80 -- layer name -- custom_added_Mul1
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Mul -- custom_added_Mul1
Layer 81 -- layer name -- Add_133
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Add -- Add_133
Layer 82 -- layer name -- Conv_134
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Conv -- Conv_134
Layer 83 -- layer name -- Relu_135
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Relu -- Relu_135
Layer 84 -- layer name -- Conv_138
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Conv -- Conv_138
Layer 85 -- layer name -- Upsample_139
Input dims size = 4 dims --- 1 64 10 25
Supported TIDL layer type --- Upsample -- Upsample_139
Layer 86 -- layer name -- Conv_137
Input dims size = 4 dims --- 1 256 20 50
Supported TIDL layer type --- Conv -- Conv_137
Layer 87 -- layer name -- Add_140
Input dims size = 4 dims --- 1 64 20 50
Supported TIDL layer type --- Add -- Add_140
Layer 88 -- layer name -- Conv_144
Input dims size = 4 dims --- 1 64 20 50
Supported TIDL layer type --- Conv -- Conv_144
Layer 89 -- layer name -- Conv_148
Input dims size = 4 dims --- 1 64 20 50
Supported TIDL layer type --- Conv -- Conv_148
Layer 90 -- layer name -- Relu_149
Input dims size = 4 dims --- 1 64 20 50
Supported TIDL layer type --- Relu -- Relu_149
Layer 91 -- layer name -- Conv_150
Input dims size = 4 dims --- 1 64 20 50
Supported TIDL layer type --- Conv -- Conv_150
Layer 92 -- layer name -- Sigmoid_166
Input dims size = 4 dims --- 1 8 20 50
Supported TIDL layer type --- Sigmoid -- Sigmoid_166
Layer 93 -- layer name -- Clip_167
Input dims size = 4 dims --- 1 8 20 50
Supported TIDL layer type --- Clip -- Clip_167
Layer 94 -- layer name -- custom_added_Mul9
Input dims size = 4 dims --- 1 8 20 50
Supported TIDL layer type --- Mul -- custom_added_Mul9
Layer 95 -- layer name -- MaxPool_182
Input dims size = 4 dims --- 1 8 20 50
Supported TIDL layer type --- MaxPool -- MaxPool_182
Layer 96 -- layer name -- custom_added_Add1
Input dims size = 4 dims --- 1 8 20 50
Supported TIDL layer type --- Add -- custom_added_Add1
Layer 97 -- layer name -- custom_added_Add0
Input dims size = 4 dims --- 1 8 20 50
Supported TIDL layer type --- Add -- custom_added_Add0
Op type 'Div' added to unsupported nodes as specified in deny list
Layer 99 -- layer name -- custom_added_Mul8
Input dims size = 4 dims --- 1 8 20 50
Supported TIDL layer type --- Mul -- custom_added_Mul8
Layer 100 -- layer name -- custom_added_Add3
Input dims size = 4 dims --- 1 8 20 50
Supported TIDL layer type --- Add -- custom_added_Add3
Layer 101 -- layer name -- Mul_189
Input dims size = 4 dims --- 1 8 20 50
Supported TIDL layer type --- Mul -- Mul_189
Layer 102 -- layer name -- Squeeze_190
Input dims size = 4 dims --- 1 8 20 50
Supported TIDL layer type --- Squeeze -- Squeeze_190
Layer 103 -- layer name -- Reshape_192
Input dims size = 3 dims --- 8 20 50
Supported TIDL layer type --- Reshape -- Reshape_192
Layer 104 -- layer name -- TopK_193
Input dims size = 1 dims --- 8000
Unsupported (imports) TIDL layer type for ONNX op type --- TopK
Layer 105 -- layer name -- Reshape_195
Input dims size = 1 dims --- 6
Supported TIDL layer type --- Reshape -- Reshape_195
Layer 106 -- layer name -- custom_added_Mul2
Input dims size = 2 dims --- 6 1
Supported TIDL layer type --- Mul -- custom_added_Mul2
Layer 107 -- layer name -- Slice_203
Input dims size = 2 dims --- 6 134
Supported TIDL layer type --- Slice -- Slice_203
Op type 'Gather' added to unsupported nodes as specified in deny list
Layer 109 -- layer name -- Conv_151
Input dims size = 4 dims --- 1 64 20 50
Supported TIDL layer type --- Conv -- Conv_151
Layer 110 -- layer name -- Relu_152
Input dims size = 4 dims --- 1 64 20 50
Supported TIDL layer type --- Relu -- Relu_152
Layer 111 -- layer name -- Conv_153
Input dims size = 4 dims --- 1 64 20 50
Supported TIDL layer type --- Conv -- Conv_153
Layer 112 -- layer name -- Reshape_172
Input dims size = 4 dims --- 1 1072 20 50
Supported TIDL layer type --- Reshape -- Reshape_172
Layer 113 -- layer name -- Transpose_179
Input dims size = 5 dims --- 1 8 134 20 50
Supported TIDL layer type --- Transpose -- Transpose_179
Layer 114 -- layer name -- Reshape_181
Input dims size = 5 dims --- 1 8 20 50 134
Supported TIDL layer type --- Reshape -- Reshape_181
Layer 115 -- layer name -- Slice_205
Input dims size = 2 dims --- 8000 134
Supported TIDL layer type --- Slice -- Slice_205
Op type 'Gather' added to unsupported nodes as specified in deny list
Layer 117 -- layer name -- Slice_228
Input dims size = 2 dims --- 6 67
Supported TIDL layer type --- Slice -- Slice_228
Layer 118 -- layer name -- Reshape_236
Input dims size = 2 dims --- 6 66
Supported TIDL layer type --- Reshape -- Reshape_236
Layer 119 -- layer name -- Reshape_243
Input dims size = 4 dims --- 6 66 1 1
Supported TIDL layer type --- Reshape -- Reshape_243
Layer 120 -- layer name -- Upsample_141
Input dims size = 4 dims --- 1 64 20 50
Supported TIDL layer type --- Upsample -- Upsample_141
Layer 121 -- layer name -- Conv_136
Input dims size = 4 dims --- 1 128 40 100
Supported TIDL layer type --- Conv -- Conv_136
Layer 122 -- layer name -- Add_142
Input dims size = 4 dims --- 1 64 40 100
Supported TIDL layer type --- Add -- Add_142
Layer 123 -- layer name -- Conv_143
Input dims size = 4 dims --- 1 64 40 100
Supported TIDL layer type --- Conv -- Conv_143
Layer 124 -- layer name -- Conv_173
Input dims size = 4 dims --- 1 64 40 100
Supported TIDL layer type --- Conv -- Conv_173
Layer 125 -- layer name -- Relu_174
Input dims size = 4 dims --- 1 64 40 100
Supported TIDL layer type --- Relu -- Relu_174
Layer 126 -- layer name -- Conv_175
Input dims size = 4 dims --- 1 64 40 100
Supported TIDL layer type --- Conv -- Conv_175
Layer 127 -- layer name -- Relu_176
Input dims size = 4 dims --- 1 64 40 100
Supported TIDL layer type --- Relu -- Relu_176
Layer 128 -- layer name -- Conv_177
Input dims size = 4 dims --- 1 64 40 100
Supported TIDL layer type --- Conv -- Conv_177
Layer 129 -- layer name -- Relu_178
Input dims size = 4 dims --- 1 64 40 100
Supported TIDL layer type --- Relu -- Relu_178
Layer 130 -- layer name -- Concat_217
Input dims size = 0 dims ---
Supported TIDL layer type --- Concat -- Concat_217
Layer 131 -- layer name -- Concat_220
Input dims size = 4 dims --- 1 66 40 100
Supported TIDL layer type --- Concat -- Concat_220
Layer 132 -- layer name -- Reshape_224
Input dims size = 4 dims --- 1 396 40 100
Supported TIDL layer type --- Reshape -- Reshape_224
Layer 133 -- layer name -- Mul_244
Input dims size = 4 dims --- 1 396 40 100
Unsupported (TIDL check) TIDL layer type --- Mul
Layer 134 -- layer name -- Reshape_246
Input dims size = 4 dims --- 1 396 40 100
Supported TIDL layer type --- Reshape -- Reshape_246
Layer 135 -- layer name -- ReduceSum_247
Input dims size = 5 dims --- 1 6 66 40 100
Unsupported (imports) TIDL layer type for ONNX op type --- ReduceSum
Layer 136 -- layer name -- Slice_229
Input dims size = 2 dims --- 6 67
Supported TIDL layer type --- Slice -- Slice_229
Layer 137 -- layer name -- custom_added_Reshape1
Input dims size = 2 dims --- 6 1
Supported TIDL layer type --- Reshape -- custom_added_Reshape1
Layer 138 -- layer name -- custom_added_Add5
Input dims size = 4 dims --- 1 1 1 6
Supported TIDL layer type --- Add -- custom_added_Add5
Layer 139 -- layer name -- Reshape_249
Input dims size = 4 dims --- 1 1 1 6
Supported TIDL layer type --- Reshape -- Reshape_249
Layer 140 -- layer name -- Add_250
Input dims size = 4 dims --- 1 6 40 100
Unsupported (TIDL check) TIDL layer type --- Add
Layer 141 -- layer name -- Reshape_254
Input dims size = 4 dims --- 1 6 40 100
Supported TIDL layer type --- Reshape -- Reshape_254
Layer 142 -- layer name -- Transpose_305
Input dims size = 4 dims --- 1 6 40 100
Supported TIDL layer type --- Transpose -- Transpose_305
Layer 143 -- layer name -- custom_added_Conv0
Input dims size = 4 dims --- 6 100 1 40
Supported TIDL layer type --- Conv -- custom_added_Conv0
Layer 144 -- layer name -- Relu_314
Input dims size = 4 dims --- 6 64 1 40
Supported TIDL layer type --- Relu -- Relu_314
Layer 145 -- layer name -- custom_added_Conv1
Input dims size = 4 dims --- 6 64 1 40
Supported TIDL layer type --- Conv -- custom_added_Conv1
Layer 146 -- layer name -- custom_added_Squeeze2
Input dims size = 4 dims --- 6 2 1 40
Supported TIDL layer type --- Squeeze -- custom_added_Squeeze2
Layer 147 -- layer name -- Transpose_316
Input dims size = 3 dims --- 6 2 40
Supported TIDL layer type --- Transpose -- Transpose_316
Layer 148 -- layer name -- Slice_204
Input dims size = 2 dims --- 6 134
Supported TIDL layer type --- Slice -- Slice_204
Op type 'Gather' added to unsupported nodes as specified in deny list
Layer 150 -- layer name -- Slice_255
Input dims size = 2 dims --- 8000 134
Supported TIDL layer type --- Slice -- Slice_255
Op type 'Gather' added to unsupported nodes as specified in deny list
Layer 152 -- layer name -- Slice_278
Input dims size = 2 dims --- 6 67
Supported TIDL layer type --- Slice -- Slice_278
Layer 153 -- layer name -- Reshape_286
Input dims size = 2 dims --- 6 66
Supported TIDL layer type --- Reshape -- Reshape_286
Layer 154 -- layer name -- Reshape_293
Input dims size = 4 dims --- 6 66 1 1
Supported TIDL layer type --- Reshape -- Reshape_293
Layer 155 -- layer name -- Reshape_274
Input dims size = 4 dims --- 1 396 40 100
Supported TIDL layer type --- Reshape -- Reshape_274
Layer 156 -- layer name -- Mul_294
Input dims size = 4 dims --- 1 396 40 100
Unsupported (TIDL check) TIDL layer type --- Mul
Layer 157 -- layer name -- Reshape_296
Input dims size = 4 dims --- 1 396 40 100
Supported TIDL layer type --- Reshape -- Reshape_296
Layer 158 -- layer name -- ReduceSum_297
Input dims size = 5 dims --- 1 6 66 40 100
Unsupported (imports) TIDL layer type for ONNX op type --- ReduceSum
Layer 159 -- layer name -- Slice_279
Input dims size = 2 dims --- 6 67
Supported TIDL layer type --- Slice -- Slice_279
Layer 160 -- layer name -- custom_added_Reshape2
Input dims size = 2 dims --- 6 1
Supported TIDL layer type --- Reshape -- custom_added_Reshape2
Layer 161 -- layer name -- custom_added_Add4
Input dims size = 4 dims --- 1 1 1 6
Supported TIDL layer type --- Add -- custom_added_Add4
Layer 162 -- layer name -- Reshape_299
Input dims size = 4 dims --- 1 1 1 6
Supported TIDL layer type --- Reshape -- Reshape_299
Layer 163 -- layer name -- Add_300
Input dims size = 4 dims --- 1 6 40 100
Unsupported (TIDL check) TIDL layer type --- Add
Layer 164 -- layer name -- Reshape_304
Input dims size = 4 dims --- 1 6 40 100
Supported TIDL layer type --- Reshape -- Reshape_304
Layer 165 -- layer name -- custom_added_Reshape0
Input dims size = 2 dims --- 6 1
Supported TIDL layer type --- Reshape -- custom_added_Reshape0
Layer 166 -- layer name -- Reshape_197
Input dims size = 1 dims --- 6
Supported TIDL layer type --- Reshape -- Reshape_197
Preliminary subgraphs created = 13
Final number of subgraphs created are : 11, - Offloaded Nodes - 155, Total Nodes - 167
INFORMATION -- [TIDL_ResizeLayer] Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
Node in deny list...delegated to ARM --- layer type - Div, Node name - Div_186
Layers type not supported by TIDL --- layer type - TopK, Node name -TopK_193
Node in deny list...delegated to ARM --- layer type - Gather, Node name - Gather_207
Node in deny list...delegated to ARM --- layer type - Gather, Node name - Gather_209
INFORMATION -- [TIDL_ResizeLayer] Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
ALLOWLISTING : ADD/MUL/SUB/DIV layer : The variable inputs must of be same dimensions --tidl_import_common_model_check.cpp , TIDL_checkAddMulSubDivTensorProperties , 403
Layers type not supported by TIDL --- layer type - ReduceSum, Node name -ReduceSum_247
ALLOWLISTING : ADD/MUL/SUB/DIV layer : The variable inputs must of be same dimensions --tidl_import_common_model_check.cpp , TIDL_checkAddMulSubDivTensorProperties , 403
Node in deny list...delegated to ARM --- layer type - Gather, Node name - Gather_257
Node in deny list...delegated to ARM --- layer type - Gather, Node name - Gather_259
ALLOWLISTING : ADD/MUL/SUB/DIV layer : The variable inputs must of be same dimensions --tidl_import_common_model_check.cpp , TIDL_checkAddMulSubDivTensorProperties , 403
Layers type not supported by TIDL --- layer type - ReduceSum, Node name -ReduceSum_297
ALLOWLISTING : ADD/MUL/SUB/DIV layer : The variable inputs must of be same dimensions --tidl_import_common_model_check.cpp , TIDL_checkAddMulSubDivTensorProperties , 403
Running runtimes graphviz - /home/root/tidl_tools/tidl_graphVisualiser_runtimes.out ../../../model-artifacts//condlanet_org//allowedNode.txt ../../../model-artifacts//condlanet_org//tempDir/graphvizInfo.txt ../../../model-artifacts//condlanet_org//tempDir/runtimes_visualization.svg
*** In TIDL_createStateImportFunc ***
Compute on node : TIDLExecutionProvider_TIDL_0_0
0, Conv, 3, 1, image, 600
1, Relu, 1, 1, 600, 203
2, MaxPool, 1, 1, 203, 204
3, Conv, 3, 1, 204, 603
4, Relu, 1, 1, 603, 207
5, Conv, 3, 1, 207, 606
6, Add, 2, 1, 606, 210
7, Relu, 1, 1, 210, 211
8, Conv, 3, 1, 211, 609
9, Relu, 1, 1, 609, 214
10, Conv, 3, 1, 214, 612
11, Add, 2, 1, 612, 217
12, Relu, 1, 1, 217, 218
13, Conv, 3, 1, 218, 621
14, Conv, 3, 1, 218, 615
15, Relu, 1, 1, 615, 221
16, Conv, 3, 1, 221, 618
17, Add, 2, 1, 618, 226
18, Relu, 1, 1, 226, 227
19, Conv, 3, 1, 227, 624
20, Relu, 1, 1, 624, 230
21, Conv, 3, 1, 230, 627
22, Add, 2, 1, 627, 233
23, Relu, 1, 1, 233, 234
24, Conv, 3, 1, 234, 636
25, Conv, 3, 1, 234, 630
26, Relu, 1, 1, 630, 237
27, Conv, 3, 1, 237, 633
28, Add, 2, 1, 633, 242
29, Relu, 1, 1, 242, 243
30, Conv, 3, 1, 243, 639
31, Relu, 1, 1, 639, 246
32, Conv, 3, 1, 246, 642
33, Add, 2, 1, 642, 249
34, Relu, 1, 1, 249, 250
35, Conv, 3, 1, 250, 378
36, Conv, 3, 1, 250, 651
37, Conv, 3, 1, 250, 645
38, Relu, 1, 1, 645, 253
39, Conv, 3, 1, 253, 648
40, Add, 2, 1, 648, 258
41, Relu, 1, 1, 258, 259
42, Conv, 3, 1, 259, 654
43, Relu, 1, 1, 654, 262
44, Conv, 3, 1, 262, 657
45, Add, 2, 1, 657, 265
46, Relu, 1, 1, 265, 266
47, Conv, 3, 1, 266, 660
48, Relu, 1, 1, 660, 269
49, Add, 2, 1, 269, 280
50, Conv, 3, 1, 280, 301
51, Reshape, 2, 1, 301, 308
52, Conv, 3, 1, 280, 290
53, Reshape, 2, 1, 290, 297
54, Conv, 3, 1, 280, 281
55, Reshape, 2, 1, 281, 288
56, Transpose, 1, 1, 288, 289
57, MatMul, 2, 1, 289, 298
58, Softmax, 1, 1, 298, 299
59, Transpose, 1, 1, 299, 300
60, MatMul, 2, 1, 308, 309
61, Reshape, 2, 1, 309, 316
62, Mul, 2, 1, 316, 317
63, Add, 2, 1, 317, 318
64, Conv, 3, 1, 318, 663
65, Relu, 1, 1, 663, 321
66, Conv, 3, 1, 321, 666
67, Relu, 1, 1, 666, 324
68, Add, 2, 1, 324, 335
69, Conv, 3, 1, 335, 356
70, Reshape, 2, 1, 356, 363
71, Conv, 3, 1, 335, 345
72, Reshape, 2, 1, 345, 352
73, Conv, 3, 1, 335, 336
74, Reshape, 2, 1, 336, 343
75, Transpose, 1, 1, 343, 344
76, MatMul, 2, 1, 344, 353
77, Softmax, 1, 1, 353, 354
78, Transpose, 1, 1, 354, 355
79, MatMul, 2, 1, 363, 364
80, Reshape, 2, 1, 364, 371
81, Mul, 2, 1, 371, 372
82, Add, 2, 1, 372, 373
83, Conv, 3, 1, 373, 669
84, Relu, 1, 1, 669, 376
85, Conv, 3, 1, 376, 379
86, Upsample, 2, 1, 379, 383
87, Add, 2, 1, 378, 384
88, Conv, 3, 1, 384, 391
89, Conv, 3, 1, 391, 398
90, Relu, 1, 1, 398, 399
91, Conv, 3, 1, 399, 400
92, Reshape, 2, 1, 400, 423
93, Transpose, 1, 1, 423, 433
94, Reshape, 2, 1, 433, 435
95, Slice, 1, 1, 435, 524
96, Slice, 1, 1, 435, 460
97, Conv, 3, 1, 391, 395
98, Relu, 1, 1, 395, 396
99, Conv, 3, 1, 396, 397
100, Sigmoid, 1, 1, 397, 413
101, Clip, 1, 1, 413, 414
102, MaxPool, 1, 1, 414, 436
103, Mul, 2, 1, 414, mul_out_Sub_183
104, Add, 2, 1, mul_out_Sub_183, 437
105, Add, 2, 1, 437, 439
Input tensor name - image
Output tensor name - 234
Output tensor name - 384
Output tensor name - 414
Output tensor name - 437
Output tensor name - 439
Output tensor name - 460
Output tensor name - 524
*** In TIDL_createStateImportFunc ***
Compute on node : TIDLExecutionProvider_TIDL_1_1
0, Mul, 2, 1, 440, mul_out_Sub_188
1, Add, 2, 1, mul_out_Sub_188, 442
2, Mul, 2, 1, 414, 443
3, Squeeze, 1, 1, 443, 444
4, Reshape, 2, 1, 444, 446
Input tensor name - 440
Input tensor name - 414
Output tensor name - 446
*** In TIDL_createStateImportFunc ***
Compute on node : TIDLExecutionProvider_TIDL_2_2
0, Reshape, 2, 1, 448, seeds
1, Mul, 2, 1, seeds, 454
2, Slice, 1, 1, 454, 458
Input tensor name - 448
Output tensor name - seeds
Output tensor name - 454
Output tensor name - 458
*** In TIDL_createStateImportFunc ***
Compute on node : TIDLExecutionProvider_TIDL_3_3
0, Conv, 3, 1, 234, 377
1, Upsample, 2, 1, 384, 388
2, Add, 2, 1, 377, 389
3, Conv, 3, 1, 389, 390
4, Conv, 3, 1, 390, 672
5, Relu, 1, 1, 672, 426
6, Conv, 3, 1, 426, 675
7, Relu, 1, 1, 675, 429
8, Conv, 3, 1, 429, 678
9, Relu, 1, 1, 678, 432
10, Concat, 2, 1, 471, 472
11, Concat, 6, 1, 472, 475
12, Reshape, 2, 1, 475, 483
13, Slice, 1, 1, 464, 487
14, Reshape, 2, 1, 487, 501
15, Reshape, 2, 1, 501, 508
Input tensor name - 464
Input tensor name - 384
Input tensor name - 234
Output tensor name - 508
Output tensor name - 475
Output tensor name - 483
*** In TIDL_createStateImportFunc ***
Compute on node : TIDLExecutionProvider_TIDL_4_4
0, Reshape, 2, 1, 509, 511
Input tensor name - 509
Output tensor name - 511
*** In TIDL_createStateImportFunc ***
Compute on node : TIDLExecutionProvider_TIDL_5_5
0, Slice, 1, 1, 464, 488
1, Reshape, 2, 1, 488, reshape_out_Sub_231
2, Add, 2, 1, reshape_out_Sub_231, add_out_Sub_231
3, Reshape, 2, 1, add_out_Sub_231, 514
Input tensor name - 464
Output tensor name - 514
*** In TIDL_createStateImportFunc ***
Compute on node : TIDLExecutionProvider_TIDL_6_6
0, Slice, 1, 1, 454, 459
1, Reshape, 2, 1, 515, 523
2, Transpose, 1, 1, 523, out_Transpose_305
3, Conv, 3, 1, out_Transpose_305, out_Conv_313
4, Relu, 1, 1, out_Conv_313, out_Relu_314
5, Conv, 3, 1, out_Relu_314, out_Conv_315
6, Squeeze, 1, 1, out_Conv_315, 598
7, Transpose, 1, 1, 598, 599
Input tensor name - 515
Input tensor name - 454
Output tensor name - 523
Output tensor name - 599
Output tensor name - 459
*** In TIDL_createStateImportFunc ***
Compute on node : TIDLExecutionProvider_TIDL_7_7
0, Reshape, 2, 1, 475, 547
1, Slice, 1, 1, 528, 551
2, Reshape, 2, 1, 551, 565
3, Reshape, 2, 1, 565, 572
Input tensor name - 528
Input tensor name - 475
Output tensor name - 572
Output tensor name - 547
*** In TIDL_createStateImportFunc ***
Compute on node : TIDLExecutionProvider_TIDL_8_8
0, Reshape, 2, 1, 573, 575
Input tensor name - 573
Output tensor name - 575
*** In TIDL_createStateImportFunc ***
Compute on node : TIDLExecutionProvider_TIDL_9_9
0, Slice, 1, 1, 528, 552
1, Reshape, 2, 1, 552, reshape_out_Sub_281
2, Add, 2, 1, reshape_out_Sub_281, add_out_Sub_281
3, Reshape, 2, 1, add_out_Sub_281, 578
Input tensor name - 528
Output tensor name - 578
*** In TIDL_createStateImportFunc ***
Compute on node : TIDLExecutionProvider_TIDL_10_10
0, Reshape, 2, 1, 447, output_dict_list
1, Reshape, 2, 1, seeds, output_seeds
2, Reshape, 2, 1, 579, 587
Input tensor name - 579
Input tensor name - seeds
Input tensor name - 447
Output tensor name - 587
Output tensor name - output_seeds
Output tensor name - output_dict_list
***************Running_Inference Section **********
This is Lucid Model for image /home/root/lucid/data_onnx/test_images/img0221.png
Graph Domain TO version : 9In TIDL_onnxRtImportInit subgraph_name=subgraph_0
Layer 0, subgraph id subgraph_0, name=234
Layer 1, subgraph id subgraph_0, name=384
Layer 2, subgraph id subgraph_0, name=414
Layer 3, subgraph id subgraph_0, name=437
Layer 4, subgraph id subgraph_0, name=439
Layer 5, subgraph id subgraph_0, name=460
Layer 6, subgraph id subgraph_0, name=524
Layer 7, subgraph id subgraph_0, name=image
In TIDL_runtimesOptimizeNet: LayerIndex = 114, dataIndex = 107
WARNING: Batch Norm Layer custom_added_Mul0's coeff cannot be found(or not match) in coef file, Random bias will be generated! Only for evaluation usage! Results are all random!
WARNING: Batch Norm Layer custom_added_Mul1's coeff cannot be found(or not match) in coef file, Random bias will be generated! Only for evaluation usage! Results are all random!
************** Frame index 1 : Running float import *************
In TIDL_runtimesPostProcessNet
In TIDL_runtimesPostProcessNet 1
In TIDL_runtimesPostProcessNet 2
In TIDL_runtimesPostProcessNet 3
INFORMATION: [TIDL_ResizeLayer] Upsample_139 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
****************************************************
** 1 WARNINGS 0 ERRORS **
****************************************************
In TIDL_runtimesPostProcessNet 4
************ in TIDL_subgraphRtCreate ************
The soft limit is 2048
The hard limit is 2048
MEM: Init ... !!!
MEM: Init ... Done !!!
0.0s: VX_ZONE_INIT:Enabled
0.8s: VX_ZONE_ERROR:Enabled
0.10s: VX_ZONE_WARNING:Enabled
0.2258s: VX_ZONE_INIT:[tivxInit:185] Initialization Done !!!
TIDL_initDebugTraceParams Done
--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr
0 , DDR Cacheable , Persistent , 128, 19.25 , 0x00000000
1 , DDR Cacheable , Persistent , 128, 0.64 , 0x00000000
2 , DDR Cacheable , Scratch , 128, 16.00 , 0x00000000
3 , DDR Cacheable , Scratch , 128, 4.00 , 0x00000000
4 , DDR Cacheable , Scratch , 128, 56.00 , 0x00000000
5 , DDR Cacheable , Persistent , 128, 537.00 , 0x00000000
6 , DDR Cacheable , Scratch , 128, 70188.19, 0x00000000
7 , DDR Cacheable , Scratch , 128, 0.12 , 0x00000000
8 , DDR Cacheable , Scratch , 128, 24511.25, 0x00000000
9 , DDR Cacheable , Scratch , 128, 32684.50, 0x00000000
10 , DDR Cacheable , Persistent , 128, 1589.58 , 0x00000000
11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000
12 , DDR Cacheable , Persistent , 128, 0.12 , 0x00000000
13 , DDR Cacheable , Persistent , 128, 52728.01, 0x00000000
14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 182846.92
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
To get the actual TIDL memory requirement make sure to run on EVM with
debugTraceLevel = 2
--------------------------------------------
TIDL init call from ivision API
--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr
0 , DDR Cacheable , Persistent , 128, 19.25 , 0x9578e000
1 , DDR Cacheable , Persistent , 128, 0.64 , 0xb29bd000
2 , DDR Cacheable , Scratch , 128, 16.00 , 0xb2728000
3 , DDR Cacheable , Scratch , 128, 4.00 , 0xb2066000
4 , DDR Cacheable , Scratch , 128, 56.00 , 0x33ecb000
5 , DDR Cacheable , Persistent , 128, 537.00 , 0x25679000
6 , DDR Cacheable , Scratch , 128, 70188.19, 0x97b74000
7 , DDR Cacheable , Scratch , 128, 0.12 , 0xaf83d000
8 , DDR Cacheable , Scratch , 128, 24511.25, 0xa246e000
9 , DDR Cacheable , Scratch , 128, 32684.50, 0xa0482000
10 , DDR Cacheable , Persistent , 128, 1589.58 , 0xa02f4000
11 , DDR Cacheable , Scratch , 128, 512.25 , 0xe3a4d000
12 , DDR Cacheable , Persistent , 128, 0.12 , 0x9d52d000
13 , DDR Cacheable , Persistent , 128, 52728.01, 0x947f5000
14 , DDR Cacheable , Persistent , 128, 0.00 , 0x9ce07000
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 182846.92
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
To get the actual TIDL memory requirement make sure to run on EVM with
debugTraceLevel = 2
--------------------------------------------
Alg Init for Layer # - 1
Alg Init for Layer # - 2
Alg Init for Layer # - 3
Alg Init for Layer # - 4
Alg Init for Layer # - 5
Alg Init for Layer # - 6
Alg Init for Layer # - 7
Alg Init for Layer # - 8
Alg Init for Layer # - 9
Alg Init for Layer # - 10
Alg Init for Layer # - 11
Alg Init for Layer # - 12
Alg Init for Layer # - 13
Alg Init for Layer # - 14
Alg Init for Layer # - 15
Alg Init for Layer # - 16
Alg Init for Layer # - 17
Alg Init for Layer # - 18
Alg Init for Layer # - 19
Alg Init for Layer # - 20
Alg Init for Layer # - 21
Alg Init for Layer # - 22
Alg Init for Layer # - 23
Alg Init for Layer # - 24
Alg Init for Layer # - 25
Alg Init for Layer # - 26
Alg Init for Layer # - 27
Alg Init for Layer # - 28
Alg Init for Layer # - 29
Alg Init for Layer # - 30
Alg Init for Layer # - 31
Alg Init for Layer # - 32
Alg Init for Layer # - 33
Alg Init for Layer # - 34
Alg Init for Layer # - 35
Alg Init for Layer # - 37
Alg Init for Layer # - 38
Alg Init for Layer # - 39
Alg Init for Layer # - 40
Alg Init for Layer # - 41
Alg Init for Layer # - 42
Alg Init for Layer # - 43
Alg Init for Layer # - 44
Alg Init for Layer # - 45
Alg Init for Layer # - 46
Alg Init for Layer # - 47
Alg Init for Layer # - 48
Alg Init for Layer # - 49
Alg Init for Layer # - 50
Alg Init for Layer # - 51
Alg Init for Layer # - 52
Alg Init for Layer # - 53
Alg Init for Layer # - 54
Alg Init for Layer # - 55
Alg Init for Layer # - 56
Alg Init for Layer # - 57
Alg Init for Layer # - 58
Alg Init for Layer # - 59
Alg Init for Layer # - 60
Alg Init for Layer # - 61
Alg Init for Layer # - 62
Alg Init for Layer # - 63
Alg Init for Layer # - 64
Alg Init for Layer # - 65
Alg Init for Layer # - 66
Alg Init for Layer # - 67
Alg Init for Layer # - 68
Alg Init for Layer # - 69
Alg Init for Layer # - 70
Alg Init for Layer # - 71
Alg Init for Layer # - 72
Alg Init for Layer # - 73
Alg Init for Layer # - 74
Alg Init for Layer # - 75
Alg Init for Layer # - 76
Alg Init for Layer # - 77
Alg Init for Layer # - 78
Alg Init for Layer # - 79
Alg Init for Layer # - 80
Alg Init for Layer # - 81
Alg Init for Layer # - 82
Alg Init for Layer # - 83
Alg Init for Layer # - 84
Alg Init for Layer # - 85
Alg Init for Layer # - 86
Alg Init for Layer # - 87
Alg Init for Layer # - 88
Alg Init for Layer # - 89
Alg Init for Layer # - 90
Alg Init for Layer # - 91
Alg Init for Layer # - 92
Alg Init for Layer # - 93
Alg Init for Layer # - 94
Alg Init for Layer # - 95
Alg Init for Layer # - 96
Alg Init for Layer # - 97
Alg Init for Layer # - 98
Alg Init for Layer # - 99
Alg Init for Layer # - 100
Alg Init for Layer # - 101
Alg Init for Layer # - 102
Alg Init for Layer # - 103
Alg Init for Layer # - 104
Alg Init for Layer # - 105
Alg Init for Layer # - 106
Alg Init for Layer # - 107
Alg Init for Layer # - 108
Alg Init for Layer # - 109
Alg Init for Layer # - 110
Alg Init for Layer # - 111
Alg Init for Layer # - 112
Alg Init for Layer # - 113
Alg Init for Layer # - 114
Alg Init for Layer # - 115
Alg Init for Layer # - 116
Alg Init for Layer # - 117
Alg Init for Layer # - 118
Alg Init for Layer # - 119
Alg Init for Layer # - 120
Alg Init for Layer # - 121
Alg Init for Layer # - 122
Alg Init for Layer # - 123
Alg Init for Layer # - 124
Alg Init for Layer # - 125
Alg Init for Layer # - 126
Alg Init for Layer # - 127
Alg Init for Layer # - 128
Alg Init for Layer # - 129
Alg Init for Layer # - 134
Alg Init for Layer # - 135
Alg Init for Layer # - 136
Alg Init for Layer # - 137
Alg Init for Layer # - 138
Alg Init for Layer # - 139
Alg Init for Layer # - 140
Alg Init for Layer # - 141
Alg Init for Layer # - 142
Alg Init for Layer # - 143
Alg Init for Layer # - 144
Alg Init for Layer # - 145
Alg Init for Layer # - 146
Alg Init for Layer # - 147
PREEMPTION: Adding a new priority object for targetPriority = 2, handle = 0x7d449578e000
PREEMPTION: Now total number of priority objects = 1 at priorityId = 2, with new memRec of base = 0x7d449d52d000 and size = 128
PREEMPTION: Requesting context memory addr for handle 0x7d449578e000, return Addr = 0x7d43cc039db8
************ TIDL_subgraphRtCreate done ************
********** Frame Index 1 : Running float inference **********
Graph Domain TO version : 9In TIDL_onnxRtImportInit subgraph_name=subgraph_1
Layer 0, subgraph id subgraph_1, name=446
Layer 1, subgraph id subgraph_1, name=440
Layer 2, subgraph id subgraph_1, name=414
In TIDL_runtimesOptimizeNet: LayerIndex = 8, dataIndex = 7
************** Frame index 1 : Running float import *************
In TIDL_runtimesPostProcessNet
In TIDL_runtimesPostProcessNet 1
In TIDL_runtimesPostProcessNet 2
In TIDL_runtimesPostProcessNet 3
****************************************************
** ALL MODEL CHECK PASSED **
****************************************************
In TIDL_runtimesPostProcessNet 4
************ in TIDL_subgraphRtCreate ************
TIDL_initDebugTraceParams Done
--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr
0 , DDR Cacheable , Persistent , 128, 19.25 , 0x00000000
1 , DDR Cacheable , Persistent , 128, 0.64 , 0x00000000
2 , DDR Cacheable , Scratch , 128, 16.00 , 0x00000000
3 , DDR Cacheable , Scratch , 128, 4.00 , 0x00000000
4 , DDR Cacheable , Scratch , 128, 56.00 , 0x00000000
5 , DDR Cacheable , Persistent , 128, 320.00 , 0x00000000
6 , DDR Cacheable , Scratch , 128, 32.75 , 0x00000000
7 , DDR Cacheable , Scratch , 128, 0.12 , 0x00000000
8 , DDR Cacheable , Scratch , 128, 47.00 , 0x00000000
9 , DDR Cacheable , Scratch , 128, 65.50 , 0x00000000
10 , DDR Cacheable , Persistent , 128, 302.89 , 0x00000000
11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000
12 , DDR Cacheable , Persistent , 128, 0.12 , 0x00000000
13 , DDR Cacheable , Persistent , 128, 6290.82 , 0x00000000
14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 7667.35
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
To get the actual TIDL memory requirement make sure to run on EVM with
debugTraceLevel = 2
--------------------------------------------
TIDL init call from ivision API
--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr
0 , DDR Cacheable , Persistent , 128, 19.25 , 0x91a2a000
1 , DDR Cacheable , Persistent , 128, 0.64 , 0x92936000
2 , DDR Cacheable , Scratch , 128, 16.00 , 0x44c29000
3 , DDR Cacheable , Scratch , 128, 4.00 , 0x92935000
4 , DDR Cacheable , Scratch , 128, 56.00 , 0x283a1000
5 , DDR Cacheable , Persistent , 128, 320.00 , 0x1f089000
6 , DDR Cacheable , Scratch , 128, 32.75 , 0x43ea3000
7 , DDR Cacheable , Scratch , 128, 0.12 , 0x92934000
8 , DDR Cacheable , Scratch , 128, 47.00 , 0x2566d000
9 , DDR Cacheable , Scratch , 128, 65.50 , 0x187ef000
10 , DDR Cacheable , Persistent , 128, 302.89 , 0xe91b4000
11 , DDR Cacheable , Scratch , 128, 512.25 , 0xe367f000
12 , DDR Cacheable , Persistent , 128, 0.12 , 0x922a9000
13 , DDR Cacheable , Persistent , 128, 6290.82 , 0xa70d7000
14 , DDR Cacheable , Persistent , 128, 0.00 , 0x922a8000
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 7667.35
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
To get the actual TIDL memory requirement make sure to run on EVM with
debugTraceLevel = 2
--------------------------------------------
Alg Init for Layer # - 2
Alg Init for Layer # - 3
Alg Init for Layer # - 4
Alg Init for Layer # - 5
Alg Init for Layer # - 6
Alg Init for Layer # - 7
PREEMPTION: Adding a new priority object for targetPriority = 2, handle = 0x7d4491a2a000
PREEMPTION: Now total number of priority objects = 2 at priorityId = 2, with new memRec of base = 0x7d44922a9000 and size = 128
PREEMPTION: Requesting context memory addr for handle 0x7d4491a2a000, return Addr = 0x7d43cc039db8
************ TIDL_subgraphRtCreate done ************
********** Frame Index 1 : Running float inference **********
Graph Domain TO version : 9In TIDL_onnxRtImportInit subgraph_name=subgraph_2
Layer 0, subgraph id subgraph_2, name=seeds
Layer 1, subgraph id subgraph_2, name=454
Layer 2, subgraph id subgraph_2, name=458
Layer 3, subgraph id subgraph_2, name=448
In TIDL_runtimesOptimizeNet: LayerIndex = 7, dataIndex = 4
************** Frame index 1 : Running float import *************
In TIDL_runtimesPostProcessNet
In TIDL_runtimesPostProcessNet 1
In TIDL_runtimesPostProcessNet 2
In TIDL_runtimesPostProcessNet 3
****************************************************
** ALL MODEL CHECK PASSED **
****************************************************
In TIDL_runtimesPostProcessNet 4
************ in TIDL_subgraphRtCreate ************
TIDL_initDebugTraceParams Done
--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr
0 , DDR Cacheable , Persistent , 128, 19.25 , 0x00000000
1 , DDR Cacheable , Persistent , 128, 0.64 , 0x00000000
2 , DDR Cacheable , Scratch , 128, 16.00 , 0x00000000
3 , DDR Cacheable , Scratch , 128, 4.00 , 0x00000000
4 , DDR Cacheable , Scratch , 128, 56.00 , 0x00000000
5 , DDR Cacheable , Persistent , 128, 260.64 , 0x00000000
6 , DDR Cacheable , Scratch , 128, 1.67 , 0x00000000
7 , DDR Cacheable , Scratch , 128, 0.12 , 0x00000000
8 , DDR Cacheable , Scratch , 128, 4.88 , 0x00000000
9 , DDR Cacheable , Scratch , 128, 9.28 , 0x00000000
10 , DDR Cacheable , Persistent , 128, 302.89 , 0x00000000
11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000
12 , DDR Cacheable , Persistent , 128, 0.12 , 0x00000000
13 , DDR Cacheable , Persistent , 128, 6233.32 , 0x00000000
14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 7421.07
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
To get the actual TIDL memory requirement make sure to run on EVM with
debugTraceLevel = 2
--------------------------------------------
TIDL init call from ivision API
--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr
0 , DDR Cacheable , Persistent , 128, 19.25 , 0x2839c000
1 , DDR Cacheable , Persistent , 128, 0.64 , 0x2566c000
2 , DDR Cacheable , Scratch , 128, 16.00 , 0x187d4000
3 , DDR Cacheable , Scratch , 128, 4.00 , 0x1f088000
4 , DDR Cacheable , Scratch , 128, 56.00 , 0xe91a6000
5 , DDR Cacheable , Persistent , 128, 260.64 , 0xe00b3000
6 , DDR Cacheable , Scratch , 128, 1.67 , 0x1f087000
7 , DDR Cacheable , Scratch , 128, 0.12 , 0x187d3000
8 , DDR Cacheable , Scratch , 128, 4.88 , 0x187d1000
9 , DDR Cacheable , Scratch , 128, 9.28 , 0x187ce000
10 , DDR Cacheable , Persistent , 128, 302.89 , 0xe0067000
11 , DDR Cacheable , Scratch , 128, 512.25 , 0xd3f7f000
12 , DDR Cacheable , Persistent , 128, 0.12 , 0x187cd000
13 , DDR Cacheable , Persistent , 128, 6233.32 , 0xa6ac0000
14 , DDR Cacheable , Persistent , 128, 0.00 , 0x187cc000
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 7421.07
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
To get the actual TIDL memory requirement make sure to run on EVM with
debugTraceLevel = 2
--------------------------------------------
Alg Init for Layer # - 1
Alg Init for Layer # - 2
Alg Init for Layer # - 3
Alg Init for Layer # - 4
Alg Init for Layer # - 6
Alg Init for Layer # - 7
PREEMPTION: Adding a new priority object for targetPriority = 2, handle = 0x7d442839c000
PREEMPTION: Now total number of priority objects = 3 at priorityId = 2, with new memRec of base = 0x7d44187cd000 and size = 128
PREEMPTION: Requesting context memory addr for handle 0x7d442839c000, return Addr = 0x7d43cc039db8
************ TIDL_subgraphRtCreate done ************
Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
********** Frame Index 1 : Running float inference **********
2024-05-22 11:54:38.782101957 [E:onnxruntime:, sequential_executor.cc:494 ExecuteKernel] Non-zero status code returned while running Gather node. Name:'Gather_207' Status Message: /onnxruntime/onnxruntime/core/framework/op_kernel.cc:83 virtual OrtValue* onnxruntime::OpKernelContext::OutputMLValue(int, const onnxruntime::TensorShape&) status.IsOK() was false. Shape mismatch attempting to re-use buffer. {1,1,1,1,1,6 } != {1,1,1,6,67}. Validate usage of dim_value (values should be > 0) and dim_param (all values with the same string should equate to the same size) in shapes in the model.
Traceback (most recent call last):
File "/home/root/examples/osrt_python/ort/onnxrt_ep_dock927_condlanet_fp32.py", line 434, in <module>
run_model(model, mIdx)
File "/home/root/examples/osrt_python/ort/onnxrt_ep_dock927_condlanet_fp32.py", line 332, in run_model
imgs, output, proc_time, sub_graph_time, height, width,org_imgs,img_name = infer_image(sess, input_images, config)
File "/home/root/examples/osrt_python/ort/onnxrt_ep_dock927_condlanet_fp32.py", line 189, in infer_image
output = list(sess.run(None, {input_name: input_data }))
File "/usr/local/lib/python3.10/dist-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 200, in run
return self._sess.run(output_names, input_feed, run_options)
onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Gather node. Name:'Gather_207' Status Message: /onnxruntime/onnxruntime/core/framework/op_kernel.cc:83 virtual OrtValue* onnxruntime::OpKernelContext::OutputMLValue(int, const onnxruntime::TensorShape&) status.IsOK() was false. Shape mismatch attempting to re-use buffer. {1,1,1,1,1,6} != {1,1,1,6,67}. Validate usage of dim_value (values should be > 0) and dim_param (all values with the same string should equate to the same size) in shapes in the model.
************ in TIDL_subgraphRtDelete ************
PREEMPTION: Removing priroty object with handle = 0x7d449578e000 and targetPriority = 2, Number of obejcts left are = 2, removed object with base = 0x7d44922a9000 and size =128
************ in TIDL_subgraphRtDelete ************
PREEMPTION: Removing priroty object with handle = 0x7d4491a2a000 and targetPriority = 2, Number of obejcts left are = 1, removed object with base = 0x7d44187cd000 and size =128
************ in TIDL_subgraphRtDelete ************
PREEMPTION: Removing priroty object with handle = 0x7d442839c000 and targetPriority = 2, Number of obejcts left are = 0, removed object with base = 0x7d449d52d000 and size =128
MEM: Deinit ... !!!
MEM: Alloc's: 84 alloc's of 285425743 bytes
MEM: Free's : 84 free's of 285425743 bytes
MEM: Open's : 0 allocs of 0 bytes
MEM: Deinit ... Done !!!
************ in TIDL_subgraphRtDelete ************
Segmentation fault (core dumped)
