TDA4VL-Q1: Capture node frame tearing

Quanfeng Fu

Part Number: TDA4VL-Q1

Hi TI experts,

HW: our custom board

SDK: j721s2, 8.6

Frame tearing occurs occasionally in our vision_apps application, the following is the application output log. How to resolve it? Could you give me some suggestions?

Fullscreen 4503.graph.log Download

Summary of CPU load,
====================

CPU: mpu1_0: TOTAL LOAD =  47.37 % ( HWI =   1.80 %, SWI =   0.32 % )
CPU: mcu2_0: TOTAL LOAD =  36. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU:  c7x_1: TOTAL LOAD =  49. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU:  c7x_2: TOTAL LOAD =  48. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )


HWA performance statistics,
===========================

HWA:   LDC : LOAD =  39.56 % ( 167 MP/s )
HWA:   MSC0: LOAD =  12.30 % ( 61 MP/s )
HWA:   MSC1: LOAD =   6.11 % ( 31 MP/s )
HWA:   GPU : LOAD =  63.67 % | PVR_LOAD =  39% ( 85 MP/s )


DDR performance statistics,
===========================

DDR: READ  BW: AVG =   2780 MB/s, PEAK =  10199 MB/s
DDR: WRITE BW: AVG =   1627 MB/s, PEAK =   7888 MB/s
DDR: TOTAL BW: AVG =   4407 MB/s, PEAK =  18087 MB/s

GRAPH:        avm_graph (#nodes =   8, #executions =   1037)
 NODE:       CAPTURE1:             capture_node: avg =  16467 usecs, min/max =    172 /  76329 usecs, #executions =       1037
 NODE:      VPAC_LDC1:                  ldc_avm: avg =  11723 usecs, min/max =   8811 /  17962 usecs, #executions =       1037
 NODE:          A72-2:      OpenGL_APS_SRV_Node: avg =  23604 usecs, min/max =  18684 /  53821 usecs, #executions =       1037
 NODE:       DSS_M2M2:             CsitxM2mNode: avg =   4806 usecs, min/max =   4122 /   5661 usecs, #executions =       1037
 NODE:          CSITX:                CsitxNode: avg =  17543 usecs, min/max =  16693 /  20150 usecs, #executions =       1037
 NODE:       DSS_M2M2:           DisplayM2mNode: avg =   2998 usecs, min/max =   2511 /   5055 usecs, #executions =       1037
 NODE:          A72-0:     PARKLANE_DETECT_NODE: avg =     29 usecs, min/max =     16 /    135 usecs, #executions =       1037
 NODE:      VPAC_LDC1:                 ldc_node: avg =  12377 usecs, min/max =   8852 /  19390 usecs, #executions =       1037

 PERF:         AvmGraph: avg =  42427 usecs, min/max =  21092 / 145779 usecs, #executions =       1037
 PERF:         AvmGraph:   23.56 FPS

GRAPH:   avm_graph_tidl (#nodes =   8, #executions =   1038)
 NODE:      VPAC_MSC2:               ScalerNode: avg =   3680 usecs, min/max =   3311 /   9433 usecs, #executions =       1038
 NODE:          DSP-1:            SDPreProcNode: avg =   2302 usecs, min/max =   1439 /  12666 usecs, #executions =       1038
 NODE:       DSP_C7-1:          StopperTIDLNode: avg =   7281 usecs, min/max =   5809 /   8956 usecs, #executions =       1038
 NODE:          DSP-1:      PostProcStopperNode: avg =     74 usecs, min/max =     16 /  15421 usecs, #executions =       1038
 NODE:       DSP_C7-1:               SDTIDLNode: avg =   6578 usecs, min/max =   5259 /   8121 usecs, #executions =       1038
 NODE:          DSP-1:           PostProcSdNode: avg =     82 usecs, min/max =     56 /   5935 usecs, #executions =       1038
 NODE:          A72-0:        LZQSlotFusionNode: avg =     50 usecs, min/max =     20 /   1103 usecs, #executions =       1038
 NODE:          DSP-1:    LZQDrawDetectionsNode: avg =   5008 usecs, min/max =   1669 /  23341 usecs, #executions =       1038

 PERF:     AvmTidlGraph: avg =  42426 usecs, min/max =  21089 / 144281 usecs, #executions =       1037
 PERF:     AvmTidlGraph:   23.57 FPS

GRAPH:       tidl_graph (#nodes =   5, #executions =    510)
 NODE:      VPAC_MSC1:               ScalerNode: avg =  14966 usecs, min/max =  13488 /  22775 usecs, #executions =        510
 NODE:          DSP-1:           img_merge_node: avg =    347 usecs, min/max =    237 /   5785 usecs, #executions =        510
 NODE:          DSP-1:            ODPreProcNode: avg =   3062 usecs, min/max =   1916 /  21890 usecs, #executions =        510
 NODE:       DSP_C7-1:               ODTIDLNode: avg =  22571 usecs, min/max =  18442 /  25889 usecs, #executions =        510
 NODE:          A72-0:           AVM Putod Node: avg =    437 usecs, min/max =     18 /   9169 usecs, #executions =        510

 PERF:        TidlGraph: avg =  86527 usecs, min/max =  67075 / 181440 usecs, #executions =        508
 PERF:        TidlGraph:   11.55 FPS

[MCU2_0]     65.841589 s: ==========================================================
[MCU2_0]     65.841724 s:  Capture Status: Instance|0
[MCU2_0]     65.841761 s: ==========================================================
[MCU2_0]     65.841814 s:  overflowCount: 0
[MCU2_0]     65.841853 s:  spuriousUdmaIntrCount: 0
[MCU2_0]     65.841941 s:  frontFIFOOvflCount: 0
[MCU2_0]     65.841993 s:  crcCount: 0
[MCU2_0]     65.842029 s:  eccCount: 0
[MCU2_0]     65.842063 s:  correctedEccCount: 0
[MCU2_0]     65.842103 s:  dataIdErrorCount: 0
[MCU2_0]     65.842141 s:  invalidAccessCount: 0
[MCU2_0]     65.842179 s:  invalidSpCount: 0
[MCU2_0]     65.842221 s:  strmFIFOOvflCount[0]: 0
[MCU2_0]     65.842273 s:  strmFIFOOvflCount[1]: 0
[MCU2_0]     65.842317 s:  Channel Num | Frame Queue Count | Frame De-queue Count | Frame Drop Count | Error Frame Count |
[MCU2_0]     65.842407 s:            0 |              1041 |                 1039 |               61 |                 0 |
[MCU2_0]     65.842509 s:            1 |              1041 |                 1039 |               61 |                 0 |
[MCU2_0]     65.842609 s:            2 |              1041 |                 1039 |               61 |                 0 |
[MCU2_0]     65.842715 s:            3 |              1041 |                 1039 |               61 |                 0 |

Thanks
Regards
quanfeng

over 2 years ago

0 Brijesh Jadav over 2 years ago

TI__Guru**** 502325 points

Hi quanfeng,

As such capture does not report any error, so does not seem like coming from the capture. If you can share some output image, it would help to understand the issue.

Also what else are you running along with the capture node?

Is it possible to check it out on the latest SDK9.2 release?

Regards,

Brijesh

0 Quanfeng Fu over 2 years ago in reply to Brijesh Jadav

Intellectual 325 points

Hi Brijesh,

Brijesh Jadav said:
Is it possible to check it out on the latest SDK9.2 release?

This project is close to SOP and I can't switch the SDK version.

As shown in the figure below, the top left is the loop test image we used in the CAPTURE node, it is normal with no tearing, the other 3 are raw camera outputs all have tearing. By the way, the image sensor is output in UYVY format.

Thanks
Regards
quanfeng

0 Brijesh Jadav over 2 years ago in reply to Quanfeng Fu

TI__Guru**** 502325 points

Hi,

Sorry, the image is not visible, so can you please share it again? or can you zip it and share it on the forum?

Btw, since you are using YUV422 camera format, can you try enabling dual-pixel mode in the CSIRX and see if it helps?

Regards,

Brijesh

0 Quanfeng Fu over 2 years ago in reply to Brijesh Jadav

Intellectual 325 points

Hi Brijesh,

Brijesh Jadav said:
Btw, since you are using YUV422 camera format, can you try enabling dual-pixel mode in the CSIRX and see if it helps?

Do you mean setting the numPixels variable to 1?

captureObj->params.instCfg[id].numPixels = 1U;

When I add the above line to the code, the image still tears.

Below is the image file.

IMG_4159.zip

Thanks
Regards
quanfeng

0 Quanfeng Fu over 2 years ago in reply to Quanfeng Fu

Intellectual 325 points

Hi Brijesh,

In addition, image tearing occurs at high dsp loads(50%), and almost no tearing occurs when we reduce the DSP algorithm runs(load 24%).

Thanks
Regards
quanfeng

0 Linjun Meng over 2 years ago in reply to Quanfeng Fu

TI__Genius 11251 points

Hi quanfeng,

Here is gel script, could you please dump these info to us?

/cfs-file/__key/communityserver-discussions-components-files/791/TDA4VL_5F00_Qos_5F00_Dump_5F00_update.gel

Regards,

Linjun

0 Quanfeng Fu over 2 years ago in reply to Linjun Meng

Intellectual 325 points

Hi Linjun,

Here is the dump info.

qos.log

Thanks
Regards
quanfeng

0 Quanfeng Fu over 2 years ago in reply to Quanfeng Fu

Intellectual 325 points

Hi TI experts,

Our dsp algorithm mainly does image affine transformation and luminance balancing. We found that the image tearing is reduced when moving the DSP algorithm from C7x_2 to C7x_1(~80% load on C7x_1 and ~20% load on C7x_2). However, this will result in the TIDL running at a frame rate that does not meet our requirements.Why does running the same algorithm on different DSP cores lead to different situations?

Thanks
Regards
quanfeng

0 Linjun Meng over 2 years ago in reply to Quanfeng Fu

TI__Genius 11251 points

Hi quanfeng，

One c71 with MMA， the other without MMA.

Regards，

Linjun

0 Quanfeng Fu over 2 years ago in reply to Linjun Meng

Intellectual 325 points

Hi Linjun,

Here are the Dsp binaries. In the zip file, DSP-algOnC7x_1 indicates that the algorithm runs on C7x_1, and so on.

dsp-bin.zip

Thanks
Regards
quanfeng

0 Linjun Meng over 2 years ago in reply to Quanfeng Fu

TI__Genius 11251 points

End point	Column3	Column4	EPRIORITY	ORDERID	QOS
COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM	Reg_0x45D86100	0x00007000	7	0	0
COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM	Reg_0x45D86500	0x00007000	7	0	0
DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR	Reg_0x45DA0100	0x00007000	7	0	0
DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW	Reg_0x45DA0500	0x00007000	7	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH0	Reg_0x45DC0100	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH1	Reg_0x45DC0104	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH2	Reg_0x45DC0108	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH3	Reg_0x45DC010C	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH4	Reg_0x45DC0110	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH5	Reg_0x45DC0114	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH6	Reg_0x45DC0118	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH7	Reg_0x45DC011C	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH8	Reg_0x45DC0120	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH9	Reg_0x45DC0124	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH10	Reg_0x45DC0128	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH11	Reg_0x45DC012C	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH12	Reg_0x45DC0130	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH13	Reg_0x45DC0134	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH14	Reg_0x45DC0138	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH15	Reg_0x45DC013C	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH16	Reg_0x45DC0140	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH17	Reg_0x45DC0144	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH18	Reg_0x45DC0148	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH19	Reg_0x45DC014C	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH20	Reg_0x45DC0150	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH21	Reg_0x45DC0154	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH22	Reg_0x45DC0158	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH23	Reg_0x45DC015C	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH24	Reg_0x45DC0160	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH25	Reg_0x45DC0164	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH26	Reg_0x45DC0168	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH27	Reg_0x45DC016C	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH28	Reg_0x45DC0170	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH29	Reg_0x45DC0174	0x00000000	0	0	0
DMPAC_TOP_MAIN_0_DATA_MST_CH30	Reg_0x45DC0178	0x00000000	0	0	0
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EMMCSD4SS_MAIN_0_EMMCSDSS_RD	Reg_0x45D82900	0x00007000	7	0	0
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J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH16	Reg_0x45DC5140	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH17	Reg_0x45DC5144	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH18	Reg_0x45DC5148	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH19	Reg_0x45DC514C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH20	Reg_0x45DC5150	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH21	Reg_0x45DC5154	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH22	Reg_0x45DC5158	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH23	Reg_0x45DC515C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH24	Reg_0x45DC5160	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH25	Reg_0x45DC5164	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH26	Reg_0x45DC5168	0x30000000	0	0	0
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J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH45	Reg_0x45DC51B4	0x30000000	0	0	0
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J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH47	Reg_0x45DC51BC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH48	Reg_0x45DC51C0	0x30000000	0	0	0
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J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH57	Reg_0x45DC51E4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH58	Reg_0x45DC51E8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH59	Reg_0x45DC51EC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH60	Reg_0x45DC51F0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH61	Reg_0x45DC51F4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH62	Reg_0x45DC51F8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH63	Reg_0x45DC51FC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH64	Reg_0x45DC5200	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH65	Reg_0x45DC5204	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH66	Reg_0x45DC5208	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH67	Reg_0x45DC520C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH68	Reg_0x45DC5210	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH69	Reg_0x45DC5214	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH70	Reg_0x45DC5218	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH71	Reg_0x45DC521C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH72	Reg_0x45DC5220	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH73	Reg_0x45DC5224	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH74	Reg_0x45DC5228	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH75	Reg_0x45DC522C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH76	Reg_0x45DC5230	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH77	Reg_0x45DC5234	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH78	Reg_0x45DC5238	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH79	Reg_0x45DC523C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH80	Reg_0x45DC5240	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH81	Reg_0x45DC5244	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH82	Reg_0x45DC5248	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH83	Reg_0x45DC524C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH84	Reg_0x45DC5250	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH85	Reg_0x45DC5254	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH86	Reg_0x45DC5258	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH87	Reg_0x45DC525C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH88	Reg_0x45DC5260	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH89	Reg_0x45DC5264	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH90	Reg_0x45DC5268	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH91	Reg_0x45DC526C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH92	Reg_0x45DC5270	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH93	Reg_0x45DC5274	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH94	Reg_0x45DC5278	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH95	Reg_0x45DC527C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH96	Reg_0x45DC5280	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH97	Reg_0x45DC5284	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH98	Reg_0x45DC5288	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH99	Reg_0x45DC528C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH100	Reg_0x45DC5290	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH101	Reg_0x45DC5294	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH102	Reg_0x45DC5298	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH103	Reg_0x45DC529C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH104	Reg_0x45DC52A0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH105	Reg_0x45DC52A4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH106	Reg_0x45DC52A8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH107	Reg_0x45DC52AC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH108	Reg_0x45DC52B0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH109	Reg_0x45DC52B4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH110	Reg_0x45DC52B8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH111	Reg_0x45DC52BC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH112	Reg_0x45DC52C0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH113	Reg_0x45DC52C4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH114	Reg_0x45DC52C8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH115	Reg_0x45DC52CC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH116	Reg_0x45DC52D0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH117	Reg_0x45DC52D4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH118	Reg_0x45DC52D8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH119	Reg_0x45DC52DC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH120	Reg_0x45DC52E0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH121	Reg_0x45DC52E4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH122	Reg_0x45DC52E8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH123	Reg_0x45DC52EC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH124	Reg_0x45DC52F0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH125	Reg_0x45DC52F4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH126	Reg_0x45DC52F8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH127	Reg_0x45DC52FC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH128	Reg_0x45DC5300	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH129	Reg_0x45DC5304	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH130	Reg_0x45DC5308	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH131	Reg_0x45DC530C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH132	Reg_0x45DC5310	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH133	Reg_0x45DC5314	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH134	Reg_0x45DC5318	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH135	Reg_0x45DC531C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH136	Reg_0x45DC5320	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH137	Reg_0x45DC5324	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH138	Reg_0x45DC5328	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH139	Reg_0x45DC532C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH140	Reg_0x45DC5330	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH141	Reg_0x45DC5334	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH142	Reg_0x45DC5338	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH143	Reg_0x45DC533C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH144	Reg_0x45DC5340	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH145	Reg_0x45DC5344	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH146	Reg_0x45DC5348	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH147	Reg_0x45DC534C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH148	Reg_0x45DC5350	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH149	Reg_0x45DC5354	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH150	Reg_0x45DC5358	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH151	Reg_0x45DC535C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH152	Reg_0x45DC5360	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH153	Reg_0x45DC5364	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH154	Reg_0x45DC5368	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH155	Reg_0x45DC536C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH156	Reg_0x45DC5370	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH157	Reg_0x45DC5374	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH158	Reg_0x45DC5378	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC_CH159	Reg_0x45DC537C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH0	Reg_0x45DC5900	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH1	Reg_0x45DC5904	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH2	Reg_0x45DC5908	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH3	Reg_0x45DC590C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH4	Reg_0x45DC5910	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH5	Reg_0x45DC5914	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH6	Reg_0x45DC5918	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH7	Reg_0x45DC591C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH8	Reg_0x45DC5920	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH9	Reg_0x45DC5924	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH10	Reg_0x45DC5928	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH11	Reg_0x45DC592C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH12	Reg_0x45DC5930	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH13	Reg_0x45DC5934	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH14	Reg_0x45DC5938	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH15	Reg_0x45DC593C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH16	Reg_0x45DC5940	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH17	Reg_0x45DC5944	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH18	Reg_0x45DC5948	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH19	Reg_0x45DC594C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH20	Reg_0x45DC5950	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH21	Reg_0x45DC5954	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH22	Reg_0x45DC5958	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH23	Reg_0x45DC595C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH24	Reg_0x45DC5960	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH25	Reg_0x45DC5964	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH26	Reg_0x45DC5968	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH27	Reg_0x45DC596C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH28	Reg_0x45DC5970	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH29	Reg_0x45DC5974	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH30	Reg_0x45DC5978	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH31	Reg_0x45DC597C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH32	Reg_0x45DC5980	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH33	Reg_0x45DC5984	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH34	Reg_0x45DC5988	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH35	Reg_0x45DC598C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH36	Reg_0x45DC5990	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH37	Reg_0x45DC5994	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH38	Reg_0x45DC5998	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH39	Reg_0x45DC599C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH40	Reg_0x45DC59A0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH41	Reg_0x45DC59A4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH42	Reg_0x45DC59A8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH43	Reg_0x45DC59AC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH44	Reg_0x45DC59B0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH45	Reg_0x45DC59B4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH46	Reg_0x45DC59B8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH47	Reg_0x45DC59BC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH48	Reg_0x45DC59C0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH49	Reg_0x45DC59C4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH50	Reg_0x45DC59C8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH51	Reg_0x45DC59CC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH52	Reg_0x45DC59D0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH53	Reg_0x45DC59D4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH54	Reg_0x45DC59D8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH55	Reg_0x45DC59DC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH56	Reg_0x45DC59E0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH57	Reg_0x45DC59E4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH58	Reg_0x45DC59E8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH59	Reg_0x45DC59EC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH60	Reg_0x45DC59F0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH61	Reg_0x45DC59F4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH62	Reg_0x45DC59F8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH63	Reg_0x45DC59FC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH64	Reg_0x45DC5A00	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH65	Reg_0x45DC5A04	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH66	Reg_0x45DC5A08	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH67	Reg_0x45DC5A0C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH68	Reg_0x45DC5A10	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH69	Reg_0x45DC5A14	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH70	Reg_0x45DC5A18	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH71	Reg_0x45DC5A1C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH72	Reg_0x45DC5A20	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH73	Reg_0x45DC5A24	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH74	Reg_0x45DC5A28	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH75	Reg_0x45DC5A2C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH76	Reg_0x45DC5A30	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH77	Reg_0x45DC5A34	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH78	Reg_0x45DC5A38	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH79	Reg_0x45DC5A3C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH80	Reg_0x45DC5A40	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH81	Reg_0x45DC5A44	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH82	Reg_0x45DC5A48	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH83	Reg_0x45DC5A4C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH84	Reg_0x45DC5A50	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH85	Reg_0x45DC5A54	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH86	Reg_0x45DC5A58	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH87	Reg_0x45DC5A5C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH88	Reg_0x45DC5A60	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH89	Reg_0x45DC5A64	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH90	Reg_0x45DC5A68	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH91	Reg_0x45DC5A6C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH92	Reg_0x45DC5A70	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH93	Reg_0x45DC5A74	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH94	Reg_0x45DC5A78	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH95	Reg_0x45DC5A7C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH96	Reg_0x45DC5A80	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH97	Reg_0x45DC5A84	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH98	Reg_0x45DC5A88	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH99	Reg_0x45DC5A8C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH100	Reg_0x45DC5A90	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH101	Reg_0x45DC5A94	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH102	Reg_0x45DC5A98	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH103	Reg_0x45DC5A9C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH104	Reg_0x45DC5AA0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH105	Reg_0x45DC5AA4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH106	Reg_0x45DC5AA8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH107	Reg_0x45DC5AAC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH108	Reg_0x45DC5AB0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH109	Reg_0x45DC5AB4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH110	Reg_0x45DC5AB8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH111	Reg_0x45DC5ABC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH112	Reg_0x45DC5AC0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH113	Reg_0x45DC5AC4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH114	Reg_0x45DC5AC8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH115	Reg_0x45DC5ACC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH116	Reg_0x45DC5AD0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH117	Reg_0x45DC5AD4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH118	Reg_0x45DC5AD8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH119	Reg_0x45DC5ADC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH120	Reg_0x45DC5AE0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH121	Reg_0x45DC5AE4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH122	Reg_0x45DC5AE8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH123	Reg_0x45DC5AEC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH124	Reg_0x45DC5AF0	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH125	Reg_0x45DC5AF4	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH126	Reg_0x45DC5AF8	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH127	Reg_0x45DC5AFC	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH128	Reg_0x45DC5B00	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH129	Reg_0x45DC5B04	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH130	Reg_0x45DC5B08	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH131	Reg_0x45DC5B0C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH132	Reg_0x45DC5B10	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH133	Reg_0x45DC5B14	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH134	Reg_0x45DC5B18	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH135	Reg_0x45DC5B1C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH136	Reg_0x45DC5B20	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH137	Reg_0x45DC5B24	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH138	Reg_0x45DC5B28	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH139	Reg_0x45DC5B2C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH140	Reg_0x45DC5B30	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH141	Reg_0x45DC5B34	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH142	Reg_0x45DC5B38	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH143	Reg_0x45DC5B3C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH144	Reg_0x45DC5B40	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH145	Reg_0x45DC5B44	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH146	Reg_0x45DC5B48	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH147	Reg_0x45DC5B4C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH148	Reg_0x45DC5B50	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH149	Reg_0x45DC5B54	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH150	Reg_0x45DC5B58	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH151	Reg_0x45DC5B5C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH152	Reg_0x45DC5B60	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH153	Reg_0x45DC5B64	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH154	Reg_0x45DC5B68	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH155	Reg_0x45DC5B6C	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH156	Reg_0x45DC5B70	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH157	Reg_0x45DC5B74	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH158	Reg_0x45DC5B78	0x30000000	0	0	0
J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC_CH159	Reg_0x45DC5B7C	0x30000000	0	0	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA_CH0	Reg_0x45DC2100	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA_CH1	Reg_0x45DC2104	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA_CH2	Reg_0x45DC2108	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA_CH3	Reg_0x45DC210C	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA_CH4	Reg_0x45DC2110	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA_CH5	Reg_0x45DC2114	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA_CH6	Reg_0x45DC2118	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA_CH7	Reg_0x45DC211C	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA_CH8	Reg_0x45DC2120	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA_CH9	Reg_0x45DC2124	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC_CH0	Reg_0x45DC2500	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC_CH1	Reg_0x45DC2504	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC_CH2	Reg_0x45DC2508	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC_CH3	Reg_0x45DC250C	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC_CH4	Reg_0x45DC2510	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC_CH5	Reg_0x45DC2514	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC_CH6	Reg_0x45DC2518	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC_CH7	Reg_0x45DC251C	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC_CH8	Reg_0x45DC2520	0x300000F0	0	15	0
K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC_CH9	Reg_0x45DC2524	0x300000F0	0	15	0
K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC	Reg_0x45DC0D00	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC	Reg_0x45DC1100	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC_CH0	Reg_0x45DC3500	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC_CH1	Reg_0x45DC3504	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC_CH2	Reg_0x45DC3508	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC_CH3	Reg_0x45DC350C	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC_CH4	Reg_0x45DC3510	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC_CH0	Reg_0x45DC3900	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC_CH1	Reg_0x45DC3904	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC_CH2	Reg_0x45DC3908	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC_CH3	Reg_0x45DC390C	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC_CH4	Reg_0x45DC3910	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_R_ASYNC	Reg_0x45DC3D00	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_W_ASYNC	Reg_0x45DC4100	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC _CH0	Reg_0x45DC4500	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC _CH1	Reg_0x45DC4504	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC _CH2	Reg_0x45DC4508	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC _CH3	Reg_0x45DC450C	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC _CH4	Reg_0x45DC4510	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC _CH0	Reg_0x45DC4900	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC _CH1	Reg_0x45DC4904	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC _CH2	Reg_0x45DC4908	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC _CH3	Reg_0x45DC490C	0x00007000	7	0	0
K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC _CH4	Reg_0x45DC4910	0x00007000	7	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_RD_CH0	Reg_0x45D98500	0x00007000	7	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_RD_CH1	Reg_0x45D98504	0x00007000	7	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_RD_CH2	Reg_0x45D98508	0x00007000	7	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_RD_CH3	Reg_0x45D9850C	0x00007000	7	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_RD_CH4	Reg_0x45D98510	0x00007000	7	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_RD_CH5	Reg_0x45D98514	0x00007000	7	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_RD_CH6	Reg_0x45D98518	0x00007000	7	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_RD_CH7	Reg_0x45D9851C	0x00007000	7	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_WR_CH0	Reg_0x45D98D00	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_WR_CH1	Reg_0x45D98D04	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_WR_CH2	Reg_0x45D98D08	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_WR_CH3	Reg_0x45D98D0C	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_WR_CH4	Reg_0x45D98D10	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_WR_CH5	Reg_0x45D98D14	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_WR_CH6	Reg_0x45D98D18	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_0_PCIE_MST_WR_CH7	Reg_0x45D98D1C	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_RD_CH0	Reg_0x45D99500	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_RD_CH1	Reg_0x45D99504	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_RD_CH2	Reg_0x45D99508	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_RD_CH3	Reg_0x45D9950C	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_RD_CH4	Reg_0x45D99510	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_RD_CH5	Reg_0x45D99514	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_RD_CH6	Reg_0x45D99518	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_RD_CH7	Reg_0x45D9951C	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_WR_CH0	Reg_0x45D99D00	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_WR_CH1	Reg_0x45D99D04	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_WR_CH2	Reg_0x45D99D08	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_WR_CH3	Reg_0x45D99D0C	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_WR_CH4	Reg_0x45D99D10	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_WR_CH5	Reg_0x45D99D14	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_WR_CH6	Reg_0x45D99D18	0x00007000	0	0	0
PCIE_G3X4_128_MAIN_1_PCIE_MST_WR_CH7	Reg_0x45D99D1C	0x00007000	0	0	0
PULSAR_SL_MAIN_0_PBDG_RMST0	Reg_0x45D78100	0x00007000	0	0	0
PULSAR_SL_MAIN_0_PBDG_WMST0	Reg_0x45D78500	0x00007000	0	0	0
PULSAR_SL_MAIN_0_PBDG_RMST1	Reg_0x45D78900	0x00007000	0	0	0
PULSAR_SL_MAIN_0_PBDG_WMST1	Reg_0x45D78D00	0x00007000	0	0	0
PULSAR_SL_MAIN_0_CPU0_RMST	Reg_0x45DC8100	0x00007000	0	0	0
PULSAR_SL_MAIN_0_CPU0_WMST	Reg_0x45DC8500	0x00007000	0	0	0
PULSAR_SL_MAIN_0_CPU1_RMST	Reg_0x45DC8900	0x000000F0	0	15	0
PULSAR_SL_MAIN_0_CPU1_WMST	Reg_0x45DC8D00	0x000000F0	0	15	0
PULSAR_SL_MAIN_1_CPU0_RMST	Reg_0x45DA8100	0x00007000	0	0	0
PULSAR_SL_MAIN_1_CPU0_WMST	Reg_0x45DA8500	0x00007000	0	0	0
PULSAR_SL_MAIN_1_CPU1_RMST	Reg_0x45DA8900	0x00007000	0	0	0
PULSAR_SL_MAIN_1_CPU1_WMST	Reg_0x45DA8D00	0x00007000	0	0	0
PULSAR_SL_MAIN_1_PBDG_RMST0	Reg_0x45DCA100	0x00007000	0	0	0
PULSAR_SL_MAIN_1_PBDG_WMST0	Reg_0x45DCA500	0x00007000	0	0	0
PULSAR_SL_MAIN_1_PBDG_RMST1	Reg_0x45DCA900	0x00007000	0	0	0
PULSAR_SL_MAIN_1_PBDG_WMST1	Reg_0x45DCAD00	0x00007000	0	0	0
PULSAR_SL_MAIN_2_CPU0_RMST	Reg_0x45DA9100	0x00007000	0	0	0
PULSAR_SL_MAIN_2_CPU0_WMST	Reg_0x45DA9500	0x00007000	0	0	0
PULSAR_SL_MAIN_2_CPU1_RMST	Reg_0x45DA9900	0x00007000	0	0	0
PULSAR_SL_MAIN_2_CPU1_WMST	Reg_0x45DA9D00	0x00007000	0	0	0
PULSAR_SL_MAIN_2_PBDG_RMST0	Reg_0x45DCB100	0x00007000	0	0	0
PULSAR_SL_MAIN_2_PBDG_WMST0	Reg_0x45DCB500	0x00007000	0	0	0
PULSAR_SL_MAIN_2_PBDG_RMST1	Reg_0x45DCB900	0x00007000	0	0	0
PULSAR_SL_MAIN_2_PBDG_WMST1	Reg_0x45DCBD00	0x00007000	0	0	0
PULSAR_SL_MCU_0_CPU0_RMST	Reg_0x45D10100	0x00007000	0	0	0
PULSAR_SL_MCU_0_CPU0_WMST	Reg_0x45D10500	0x00007000	0	0	0
PULSAR_SL_MCU_0_CPU0_PMST	Reg_0x45D10900	0x00007000	0	0	0
PULSAR_SL_MCU_0_CPU1_RMST	Reg_0x45D11100	0x00007000	0	0	0
PULSAR_SL_MCU_0_CPU1_WMST	Reg_0x45D11500	0x00007000	0	0	0
PULSAR_SL_MCU_0_CPU1_PMST	Reg_0x45D11900	0x00007000	0	0	0
SA2_UL_MAIN_0_CTXCACH_EXT_DMA	Reg_0x45D9BD00	0x00007000	0	0	0
SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA	Reg_0x45D13100	0x00007000	0	0	0
SMS_WKUP_0_TIFS_VBUSP_M	Reg_0x45D00100	0x00007000	0	0	0
SMS_WKUP_0_HSM_VBUSP_M	Reg_0x45D00500	0x00007000	0	0	0
UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD_CH0	Reg_0x45D9AD00	0x00007000	0	0	0
UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD_CH1	Reg_0x45D9AD04	0x00007000	0	0	0
UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR_CH0	Reg_0x45D9B100	0x00007000	0	0	0
UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR_CH1	Reg_0x45D9B104	0x00007000	0	0	0
UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR_CH2	Reg_0x45D9B108	0x00007000	0	0	0
UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR_CH3	Reg_0x45D9B10C	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTR0	Reg_0x45D9A100	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTR1	Reg_0x45D9A104	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTR2	Reg_0x45D9A108	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTR3	Reg_0x45D9A10C	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTR4	Reg_0x45D9A110	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTR5	Reg_0x45D9A114	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTR6	Reg_0x45D9A118	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTR7	Reg_0x45D9A11C	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTW0	Reg_0x45D9A500	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTW1	Reg_0x45D9A504	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTW2	Reg_0x45D9A508	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTW3	Reg_0x45D9A50C	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTW4	Reg_0x45D9A510	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTW5	Reg_0x45D9A514	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTW6	Reg_0x45D9A518	0x00007000	0	0	0
USB3P0SS_16FFC_MAIN_0_MSTW7	Reg_0x45D9A51C	0x00007000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH0	Reg_0x45DC1500	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH1	Reg_0x45DC1504	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH2	Reg_0x45DC1508	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH3	Reg_0x45DC150C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH4	Reg_0x45DC1510	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH5	Reg_0x45DC1514	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH6	Reg_0x45DC1518	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH7	Reg_0x45DC151C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH8	Reg_0x45DC1520	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH9	Reg_0x45DC1524	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH10	Reg_0x45DC1528	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH11	Reg_0x45DC152C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH12	Reg_0x45DC1530	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH13	Reg_0x45DC1534	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH14	Reg_0x45DC1538	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH15	Reg_0x45DC153C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH16	Reg_0x45DC1540	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH17	Reg_0x45DC1544	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH18	Reg_0x45DC1548	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH19	Reg_0x45DC154C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH20	Reg_0x45DC1550	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH21	Reg_0x45DC1554	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH22	Reg_0x45DC1558	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH23	Reg_0x45DC155C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH24	Reg_0x45DC1560	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH25	Reg_0x45DC1564	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH26	Reg_0x45DC1568	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH27	Reg_0x45DC156C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH28	Reg_0x45DC1570	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH29	Reg_0x45DC1574	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH30	Reg_0x45DC1578	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_0_CH31	Reg_0x45DC157C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH0	Reg_0x45DC1900	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH1	Reg_0x45DC1904	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH2	Reg_0x45DC1908	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH3	Reg_0x45DC190C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH4	Reg_0x45DC1910	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH5	Reg_0x45DC1914	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH6	Reg_0x45DC1918	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH7	Reg_0x45DC191C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH8	Reg_0x45DC1920	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH9	Reg_0x45DC1924	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH10	Reg_0x45DC1928	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH11	Reg_0x45DC192C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH12	Reg_0x45DC1930	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH13	Reg_0x45DC1934	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH14	Reg_0x45DC1938	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH15	Reg_0x45DC193C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH16	Reg_0x45DC1940	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH17	Reg_0x45DC1944	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH18	Reg_0x45DC1948	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH19	Reg_0x45DC194C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH20	Reg_0x45DC1950	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH21	Reg_0x45DC1954	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH22	Reg_0x45DC1958	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH23	Reg_0x45DC195C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH24	Reg_0x45DC1960	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH25	Reg_0x45DC1964	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH26	Reg_0x45DC1968	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH27	Reg_0x45DC196C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH28	Reg_0x45DC1970	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH29	Reg_0x45DC1974	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH30	Reg_0x45DC1978	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH31	Reg_0x45DC197C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH32	Reg_0x45DC1980	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH33	Reg_0x45DC1984	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH34	Reg_0x45DC1988	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH35	Reg_0x45DC198C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH36	Reg_0x45DC1990	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH37	Reg_0x45DC1994	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH38	Reg_0x45DC1998	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH39	Reg_0x45DC199C	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH40	Reg_0x45DC19A0	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH41	Reg_0x45DC19A4	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH42	Reg_0x45DC19A8	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH43	Reg_0x45DC19AC	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH44	Reg_0x45DC19B0	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH45	Reg_0x45DC19B4	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH46	Reg_0x45DC19B8	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH47	Reg_0x45DC19BC	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH48	Reg_0x45DC19C0	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH49	Reg_0x45DC19C4	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH50	Reg_0x45DC19C8	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH51	Reg_0x45DC19CC	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH52	Reg_0x45DC19D0	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH53	Reg_0x45DC19D4	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH54	Reg_0x45DC19D8	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH55	Reg_0x45DC19DC	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH56	Reg_0x45DC19E0	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH57	Reg_0x45DC19E4	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH58	Reg_0x45DC19E8	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH59	Reg_0x45DC19EC	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH60	Reg_0x45DC19F0	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH61	Reg_0x45DC19F4	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH62	Reg_0x45DC19F8	0x00000000	0	0	0
VPAC_TOP_MAIN_0_DATA_MST_1 _CH63	Reg_0x45DC19FC	0x00000000	0	0	0
VPAC_TOP_MAIN_0_LDC0_M_MST_CH0	Reg_0x45DC1D00	0x00007000	0	0	0
VPAC_TOP_MAIN_0_LDC0_M_MST_CH1	Reg_0x45DC1D04	0x00007000	0	0	0
VPAC_TOP_MAIN_0_LDC0_M_MST_CH2	Reg_0x45DC1D08	0x00007000	0	0	0
VPAC_TOP_MAIN_1_LDC0_M_MST_CH0	Reg_0x45DC2900	0x00007000	0	0	0
VPAC_TOP_MAIN_1_LDC0_M_MST_CH1	Reg_0x45DC2904	0x00007000	0	0	0
VPAC_TOP_MAIN_1_LDC0_M_MST_CH2	Reg_0x45DC2908	0x00007000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH0	Reg_0x45DC2D00	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH1	Reg_0x45DC2D04	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH2	Reg_0x45DC2D08	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH3	Reg_0x45DC2D0C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH4	Reg_0x45DC2D10	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH5	Reg_0x45DC2D14	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH6	Reg_0x45DC2D18	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH7	Reg_0x45DC2D1C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH8	Reg_0x45DC2D20	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH9	Reg_0x45DC2D24	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH10	Reg_0x45DC2D28	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH11	Reg_0x45DC2D2C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH12	Reg_0x45DC2D30	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH13	Reg_0x45DC2D34	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH14	Reg_0x45DC2D38	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH15	Reg_0x45DC2D3C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH16	Reg_0x45DC2D40	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH17	Reg_0x45DC2D44	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH18	Reg_0x45DC2D48	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH19	Reg_0x45DC2D4C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH20	Reg_0x45DC2D50	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH21	Reg_0x45DC2D54	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH22	Reg_0x45DC2D58	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH23	Reg_0x45DC2D5C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH24	Reg_0x45DC2D60	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH25	Reg_0x45DC2D64	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH26	Reg_0x45DC2D68	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH27	Reg_0x45DC2D6C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH28	Reg_0x45DC2D70	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH29	Reg_0x45DC2D74	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH30	Reg_0x45DC2D78	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_0_CH31	Reg_0x45DC2D7C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH0	Reg_0x45DC3100	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH1	Reg_0x45DC3104	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH2	Reg_0x45DC3108	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH3	Reg_0x45DC310C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH4	Reg_0x45DC3110	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH5	Reg_0x45DC3114	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH6	Reg_0x45DC3118	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH7	Reg_0x45DC311C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH8	Reg_0x45DC3120	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH9	Reg_0x45DC3124	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH10	Reg_0x45DC3128	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH11	Reg_0x45DC312C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH12	Reg_0x45DC3130	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH13	Reg_0x45DC3134	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH14	Reg_0x45DC3138	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH15	Reg_0x45DC313C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH16	Reg_0x45DC3140	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH17	Reg_0x45DC3144	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH18	Reg_0x45DC3148	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH19	Reg_0x45DC314C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH20	Reg_0x45DC3150	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH21	Reg_0x45DC3154	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH22	Reg_0x45DC3158	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH23	Reg_0x45DC315C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH24	Reg_0x45DC3160	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH25	Reg_0x45DC3164	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH26	Reg_0x45DC3168	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH27	Reg_0x45DC316C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH28	Reg_0x45DC3170	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH29	Reg_0x45DC3174	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH30	Reg_0x45DC3178	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH31	Reg_0x45DC317C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH32	Reg_0x45DC3180	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH33	Reg_0x45DC3184	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH34	Reg_0x45DC3188	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH35	Reg_0x45DC318C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH36	Reg_0x45DC3190	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH37	Reg_0x45DC3194	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH38	Reg_0x45DC3198	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH39	Reg_0x45DC319C	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH40	Reg_0x45DC31A0	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH41	Reg_0x45DC31A4	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH42	Reg_0x45DC31A8	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH43	Reg_0x45DC31AC	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH44	Reg_0x45DC31B0	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH45	Reg_0x45DC31B4	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH46	Reg_0x45DC31B8	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH47	Reg_0x45DC31BC	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH48	Reg_0x45DC31C0	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH49	Reg_0x45DC31C4	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH50	Reg_0x45DC31C8	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH51	Reg_0x45DC31CC	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH52	Reg_0x45DC31D0	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH53	Reg_0x45DC31D4	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH54	Reg_0x45DC31D8	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH55	Reg_0x45DC31DC	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH56	Reg_0x45DC31E0	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH57	Reg_0x45DC31E4	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH58	Reg_0x45DC31E8	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH59	Reg_0x45DC31EC	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH60	Reg_0x45DC31F0	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH61	Reg_0x45DC31F4	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH62	Reg_0x45DC31F8	0x00000000	0	0	0
VPAC_TOP_MAIN_1_DATA_MST_1_CH63	Reg_0x45DC31FC	0x00000000	0	0	0
VUSR_DUAL_MAIN_0_V0_M	Reg_0x45D9C100	0x00000000	0	0	0
VUSR_DUAL_MAIN_0_V1_M	Reg_0x45D9C500	0x00000000	0	0	0

0 Linjun Meng over 2 years ago in reply to Quanfeng Fu

TI__Genius 11251 points

Hi Quanfen,

I disassembled the vx_app_rtos_linux_c7x_1.out and vx_app_rtos_linux_c7x_2.out , found when you use the C7X_1, the stream engine is enable in both folder. Such as below,

./vx_app_rtos_linux_c7x_1.out.txt:1847:0x0000b1400b28   4a080433 || SEOPEN .D2 D0,0,VB2
./vx_app_rtos_linux_c7x_1.out.txt:1911:0x0000b1400c24   4a188433 || SEOPEN .D2 D1,0x1,VB2
./vx_app_rtos_linux_c7x_1.out.txt:1937:0x0000b1400c8c   42080432 || SEOPEN .D2 D0,0,VB0
./vx_app_rtos_linux_c7x_1.out.txt:1978:0x0000b1400d28   46188432    SEOPEN .D2 D1,0x1,VB1
./vx_app_rtos_linux_c7x_1.out.txt:1982:0x0000b1400d38   42080432 || SEOPEN .D2 D0,0,VB0
./vx_app_rtos_linux_c7x_1.out.txt:19266:0x0000b141154c   42168432    SEOPEN .D2 A13,0x1,VB0
./vx_app_rtos_linux_c7x_1.out.txt:19267:0x0000b1411550   460c0432    SEOPEN .D2 D8,0,VB1
./vx_app_rtos_linux_c7x_1.out.txt:29387:0x0000b141b10c   46080433    SEOPEN .D2 D0,0,VB1
./vx_app_rtos_linux_c7x_1.out.txt:29389:0x0000b141b114   621f0432    SEOPEN .D2 D14,0x1,VB8
./vx_app_rtos_linux_c7x_1.out.txt:34792:0x0000b1420448   46130432 || SEOPEN .D2 A6,0x1,VB1
./vx_app_rtos_linux_c7x_1.out.txt:34847:0x0000b1420524   46080433 || SEOPEN .D2 D0,0,VB1
./vx_app_rtos_linux_c7x_1.out.txt:34912:0x0000b1420624   46130433 || SEOPEN .D2 A6,0x1,VB1

As to the algorithm should works on L2, leveraged the access to DDR bandwidth, so the issue seems disappeared.

What you should do is optimize your TIDL and AVM algorithm on C7x_1.

Thanks.

Linjun

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