AM625: QSPI Internal PHY loopback mode

Hi Koichiro,

Thanks for your question.

Allow me sometime to follow up with you.

Regards,

Vaibhav

Hi Koichiro,

Thanks for your patience.

Koichiro Tashiro said:

My customer wants to use QSPI PHY mode with internal PHY loopback.

Is this the setting the customer will use to boot the board? I want to know at which stage they want to have this configuration applied, at all stages or at some later stage when the board has booted up with some other configuration.

Regards,

Vaibhav

Hi Vaibhav,

They wants to use QSPI after the system has booted up.

Thanks and regards,
Koichiro Tashiro

Hi Koichiro,

Thanks for your patience.

Koichiro Tashiro said:

Could you tell me how to configure QSPI registers to enable that mode?

I believe you are talking about configuration which will be done in the custom application, please correct my understanding here.

I would request you to share the following information with the customer as the customer is interested in using QSPI Phy Internal Loopback mode.

1. Please read through TRM section 12.4.2.4.2.1 Read Data Capture
   
2. One more section to read would be Phy Pipeline mode and Read Data Capturing by the Phy Module section
   
   

Regards,

Vaibhav

Hi Vaibhav,

According to TRM, below configurations are required to use PHY internal loopback mode.

Option-A: SPI mode 0 is used.
OSPI_CONFIG_REG[2] SEL_CLK_PHASE_FLD=0
OSPI_CONFIG_REG[1] SEL_CLK_POL_FLD=0
OSPI_CONFIG_REG[3] PHY_MODE_ENABLE_FLD=1

Option-B: SPI mode 3 is used.
OSPI_CONFIG_REG[2] SEL_CLK_PHASE_FLD=1
OSPI_CONFIG_REG[1] SEL_CLK_POL_FLD=1
OSPI_CONFIG_REG[3] PHY_MODE_ENABLE_FLD=1

Then below configurations are needed for both options.
OSPI_RD_DATA_CAPTURE_REG[0] BYPASS_FLD=0
OSPI_RD_DATA_CAPTURE_REG[8] DQS_ENABLE_FLD=0

I have a few more questions.
Q1) TRM section 12.4.2.4.2.1 also says
"The taps are selected by programming OSPI_RD_DATA_CAPTURE_REG[4-1] DELAY_FLD field."
But it does not explain how to determine the taps value.
How to select DELAY_FLD value?

Q2) In CTRL_MMR registers, there is OSPI0_CLKSEL register.
It seems bit4 OSPI0_CLKSEL_LOOPCLK_SEL should be set for internal loopback, correct?

How about bit1? The reset value '0' is ok?

Q3) Any other registers need to be configured?

Thanks and regards,
Koichiro Tashiro

Greetings Koichiro,

Thank you for your response.

I will try to answer your questions individually.

Koichiro Tashiro said:

Q1) TRM section 12.4.2.4.2.1 also says
"The taps are selected by programming OSPI_RD_DATA_CAPTURE_REG[4-1] DELAY_FLD field."
But it does not explain how to determine the taps value.
How to select DELAY_FLD value?

So delay field value can be set via trial and error, we want to make sure to use a value which ensures proper and correct data capture.

Check line number 1192:

Koichiro Tashiro said:

Q2) In CTRL_MMR registers, there is OSPI0_CLKSEL register.
It seems bit4 OSPI0_CLKSEL_LOOPCLK_SEL should be set for internal loopback, correct?

How about bit1? The reset value '0' is ok?

Q3) Any other registers need to be configured?

I would let another expert comment on this.

Regards,

Vaibhav

Hi Vaibhav,

For Q1), the flash_nor_ospi.c file is included in Linux SDK?
If so, could you tell me the file path?

For Q2), did you get any comments from the expert?

Thanks and regards,
Koichiro Tashiro

Greetings Koichiro,

Thank you for your response.

Koichiro Tashiro said:

flash_nor_ospi.c

This file is present in the mcu plus sdk.

Koichiro Tashiro said:

For Q2), did you get any comments from the expert?

I am going to follow up with the expert on this. 

Thanks for your patience.

Regards,

Vaibhav

Hi Vaibhav,

Do you have any updates?
The customer is a bit frustrated due to slow response from TI.

Thanks and regards,
Koichiro Tashiro

Hello Koichiro,

Apologies in delayed responses.

Koichiro Tashiro said:

Q2) In CTRL_MMR registers, there is OSPI0_CLKSEL register.
It seems bit4 OSPI0_CLKSEL_LOOPCLK_SEL should be set for internal loopback, correct?

How about bit1? The reset value '0' is ok?

Q3) Any other registers need to be configured?

Please expect responses in sometime from the assigned expert.

Regards,

Vaibhav

Hello Koichiro,

I believe the customer is using MCU PLUS SDK AM62x.

If the customer is using TI Drivers which comes with MCU PLUS SDK, then few APIs like Drivers_open() and Board_driversOpen() takes care of the initialization of the OSPI/QSPI IP.

I would request the customer to use the SysConfig options to enable the Tap/Phy mode.

For that the customer can simply check one of the SDK examples named as ospi_flash_io.c

This is available at MCU_PLUS_SDK_INSTALL_PATH > examples > drivers > ospi > ospi_flash_io

From CCS(Code composer studio) the customer can import this example and open the application named example.syscfg

Once opened, the customer can then easily configure Tap Mode/Phy mode. Please look at the options below on how to do it:

1. For PHY mode
   
   
2. For TAP mode
   
   

You can go ahead and change the frequency in the field Input Clock Frequency(Hz)

Please let me know if you still need to register settings flow/the above method works for you?

Regards,

Vaibhav

Greetings Koichiro,

Key registers in the OSPI IP are:

OSPI_RD_DATA_CAPTURE_REG[8].DQS_ENABLE_FLD = 0b0

OSPI_RD_DATA_CAPTURE_REG[0].BYPASS_FLD = 0b1

Bit 8 is the DQS enable field. Since we are not using the DQS signal, this should be set to 0.

Bit 0 is the bypass enable for loopback clocking, and in this case we are not using the loopback logic so it should be set to 1 to disable. This is where the terminology can be slightly confusing. Internal PHY loopback does not technically use any loopback clock, it's just using the reference clock to be driven into the PHY as part of the sampling block.

The other clocking modes involve driving DQS into that sampling logic or a copy of the clock (on the LBCLK pin) that is routed external to the IP. This loopback of the clock can be done at the PAD level (Internal Pad Loopback) which does not actually leave the chip, or at the board level (External Board Loopback) which has to be physically routed back into a pin.

As far as other registers, in the CTRL MMR snippet you shared:

Bit 4 in this mode is a don't care and would recommend leaving this at the reset value of 0b0. We are not technically using any loopback which is why this is a DC, but for context clearing to 0 would be for External Board Loopback and setting to 1 would be for Internal Pad Loopback.

Bit 0 will depend on which PLL they want to use and that PLL's configuration. Either 0 or 1 are valid options, but each PLL has different frequencies and options for dividing it down. I would highly recommend sticking to whichever high level software package (Linux or MCU+SDK) is doing the PLL configuration and not try to do this sequencing by hand. 

Sincerely,

Lucas

Hi Lucas, Vaibhav,

The customer configured these required settings, but still read access is failing (read all zero).
TAP mode is working.
Please see below results.

Any settings are missed?

Thanks and regards,
Koichiro Tashiro

Hello Koichiro,

Thank you for your response.

It would be helpful if you can answer my following questions:

So, for SDR mode, are you operating in 8-8-8S mode? Can you please tell me the frequency as well? Wat is the clock divider value as well?

Regards,

Vaibhav

Hi Vaibhav,

Vaibhav Kumar said:

So, for SDR mode, are you operating in 8-8-8S mode?

4-4-4S mode is used as the memory does not support OSPI.

Vaibhav Kumar said:

Can you please tell me the frequency as well?

50MHz

Vaibhav Kumar said:

Wat is the clock divider value as well?

Which clock divider value are you asking for?

Thanks and regards,
Koichiro Tashiro

Hello Koichiro,

Koichiro Tashiro said:

Vaibhav Kumar said:

So, for SDR mode, are you operating in 8-8-8S mode?

4-4-4S mode is used as the memory does not support OSPI.

Vaibhav Kumar said:

Can you please tell me the frequency as well?

50MHz

Thank you for responding to my questions.

Please allow me sometime to check with another expert on the register flow.

Regards,

Vaibhav

Hi Vaibhav,

Any updates to this item?

Thanks and regards,
Koichiro Tashiro

Hello Koichiro,

As per my understanding the idea is when Phy mode is enabled, we do Direct read operations.

Hence, we need to have DAC mode enabled.

Can you please go ahead and tell me the value of the following registers after you have made the configurations?

Register name: OSPI_CONFIG_REG Address: 0x0FC40000h

Register name: OSPI_RD_DATA_CAPTURE_REG Address: 0x0FC40010h

I would need to know the value of this register in both the modes which you are operating in. that is TAP and PHY.

Regards,

Vaibhav

Hi Vaibhav,

Sorry for my late reply.
Here are register values for TAP mode and PHY internal loopback mode.

#1 TAP mode
・Register name: OSPI_CONFIG_REG Address: 0x0FC40000h　0x80083881
・Register name: OSPI_RD_DATA_CAPTURE_REG Address: 0x0FC40010h　0x00000001

#2 PHY mode
・Register name: OSPI_CONFIG_REG Address: 0x0FC40000h　0x80083889
・Register name: OSPI_RD_DATA_CAPTURE_REG Address: 0x0FC40010h　0x00000001

Thanks and regards,
Koichiro Tashiro

Hello Koichiro,

Thank you for your patience.

Allow me sometime to put out a dump of register values when TAP mode is enabled vs Phy mode is enabled just for you to make sure it aligned with your application vs when I run a sample application on the TI EVM.

Regards,

Vaibhav

Hello Koichiro,

So, I ran a SDK example based out of MCU PLUS SDK just to see what will be the value of the registers when PHY mode is enabled vs when TAP mode is enabled: FYI this is from AM64x execution and will be mostly same for AM62x for sure. But will cross check with AM62x as well.

Before any configuration is done for Phy mode enabled OR Tap mode the register values are the same:

After all the configurations for OSPI are done for PHY Enabled mode the register values are:

After all the configurations for OSPI are done for TAP mode the register values are:

Regards,

Vaibhav

Hi Vaibhav,

Thanks for your reply and sorry for my late feedback.
Now the customer is able to read/write to the memory using PHY mode configuration you provided.
But it seems PHY_MODE_ENABLE_FLD bit in OSPI0_CONFIG_REG(0x0FC4:0000) is 0.
According to TRM (SPRUIV7B) Table 14-18650 description, the bit should be 1 for PHY mode.


The customer tried to change the bit to 1, then read/write to the memory failed.
Q1) Is this expected PHY_MODE_ENABLE_FLD is 0 for PHY mode?
Q2) If TRM description is typo, please correct it.

Thanks and regards,
Koichiro Tashiro

Hello Koichiro,

Thanks for your patience.

Koichiro Tashiro said:

Thanks for your reply and sorry for my late feedback.

It is fine.

Koichiro Tashiro said:

Now the customer is able to read/write to the memory using PHY mode configuration you provided.

I am glad that the customer is able to do the write and read operations with the register configurations I provided. Good to hear this.

Koichiro Tashiro said:

Q1) Is this expected PHY_MODE_ENABLE_FLD is 0 for PHY mode?

So I will explain this in another response as it needs some explanation.

Regards,

Vaibhav

Hello,

Thank you for the patience.

So, I am yet to respond on this question

Koichiro Tashiro said:

Q1) Is this expected PHY_MODE_ENABLE_FLD is 0 for PHY mode?

Here we go,

You see that the register configurations I have given you and which worked for the customer is absolutely fine.

The Phy enable field should only be set to 1, when doing read operations, else most of the times this phy enable field should be set to 0.

And when the read is done, we need to disable phy and then do the other operation like write.

Regards,

Vaibhav

Hi Vaibhav,

Thanks for your reply.

Vaibhav Kumar said:

The Phy enable field should only be set to 1, when doing read operations, else most of the times this phy enable field should be set to 0.

And when the read is done, we need to disable phy and then do the other operation like write.

Please let me confirm if I understood your answer correctly.
The phy enable filed is set to 1 only at read. And the field should be set to 0 for other operation.
Does it mean the phy enable bit is automatically controlled by hardware?
Or user needs to control the bit depending on memory operations?

Thanks and regards,
Koichiro Tashiro

Hello Koichiro,

Your understanding is correct.

Koichiro Tashiro said:

Or user needs to control the bit depending on memory operations?

User needs to control it based on the operation.

So for reads phy enable bit should be set, and for write it should not be set.

Regards,

Vaibhav

I have unlocked this thread based on a recent mail from Tashiro.

If the customer is using DQS line, then the DQS line is set to 1 when we find the OTP during Phy Tuning operation.

There are two cases:

1. If customer wants to read <= 1024 bytes, then the Phy Enable bit should be set along with DAC enable bit set.
2. If the customer wants to read > 1024 bytes then the Phy enable bit should be set along with DAC enable:
   1. If the customer wants to do DMA read here, then DMA bit should be set along with Phy pipeline enable field.
   2. If the customer does not wants to do DMA read, then neither the DMA enable nor the Phy pipeline bit should be set.

For writes, for NOR flash, we can only do INDAC writes, hence, for INDAC writes, the DQS enable bit is a no care.

Please ask the customer to follow up here for further queries.

Regards,

Vaibhav

Hi Vaibhav,

I will check your answer, but could you first reply to below questions from the customer?

1) OSPI_RD_DATA_CAPTURE_REG[8].DQS_ENABLE_FLD value
Lucas said it should be 0, but PHY mode register dump sent by Vaibhav shows the bit is 1.
0x0FC40010 is 0x0000123 for both PHY mode and TAP mode.


2) Difference between PHY mode and TAP mode is only OSPI0_CONFIG_REG[7].ENB_DIR_ACC_CTLR_FLD.
0x0FC40000 is 0xC1083881(PHY) or 0xC1083801(TAP).
This is strange.

3) Below comments for OSPI0_CONFIG_REG[3].PHY_MODE_ENABLE_FLD does not seem correct.
As soon as PHY_MODE_ENABLE is set, the customer cannot read memory data.

Vaibhav Kumar said:

The Phy enable field should only be set to 1, when doing read operations, else most of the times this phy enable field should be set to 0.

And when the read is done, we need to disable phy and then do the other operation like write.

The customer thinks above comment is to for OSPI0_CONFIG_REG[25].PIPELINE_PHY_FLD.
TRM Table 14-18650.

Thanks and regards,
Koichiro Tashiro 

Koichiro Tashiro said:

I will check your answer, but could you first reply to below questions from the customer?

I am sure going to reply to the questions. Allow me sometime to read through them and answer one by one.

Thanks for your patience and I also appreciate continuing our communication over E2E rather over mails to maintain uniformity.

Regards,

Vaibhav

Koichiro Tashiro said:

1) OSPI_RD_DATA_CAPTURE_REG[8].DQS_ENABLE_FLD value
Lucas said it should be 0, but PHY mode register dump sent by Vaibhav shows the bit is 1.
0x0FC40010 is 0x0000123 for both PHY mode and TAP mode.

I have checked properly by executing the code again.

What I have observed is upon resetting DQS field gets reset to 0. Which I think while running and giving you the register dump earlier, I did not happen to reset correctly.

So, safe to say:

1. DQS filed should only be set to 1, when the Phy is enabled.
2. If the Phy is not enabled, meaning the operation is in TAP mode, no need of having DQS set to 0, it should be always 0 in TAP mode.

Koichiro Tashiro said:

2) Difference between PHY mode and TAP mode is only OSPI0_CONFIG_REG[7].ENB_DIR_ACC_CTLR_FLD.
0x0FC40000 is 0xC1083881(PHY) or 0xC1083801(TAP).
This is strange.

I will explain this in another response with the help of a whiteboard diagram.

Koichiro Tashiro said:

3) Below comments for OSPI0_CONFIG_REG[3].PHY_MODE_ENABLE_FLD does not seem correct.
As soon as PHY_MODE_ENABLE is set, the customer cannot read memory data.

Vaibhav Kumar said:

The Phy enable field should only be set to 1, when doing read operations, else most of the times this phy enable field should be set to 0.

And when the read is done, we need to disable phy and then do the other operation like write.

The customer thinks above comment is to for OSPI0_CONFIG_REG[25].PIPELINE_PHY_FLD.
TRM Table 14-18650.

Please see the diagram I am drawing for you to understand this visually.

FYI, Allow me sometime to put forward the diagrams.

Hi,

I have drawn a rough sketch. Please find it as follows:

If the customer is going to read more than 1024 bytes at a time, then let me know, in that case, the diagram would need a bit of modification.

Regards,

Vaibhav