AM625: Controlling MAIN domain pins from MCU domain and vice versa

Mari Tsunoda

Part Number: AM625

Tool/software:

Hi Team,

My customer has question about controlling pins in the MAIN domain from the MCU domain and its real-time response/latency. They do not have enough pins in the MCU domain and want to control the MAIN domain pins from MCU domain.They are concerned with real-time response because they want to use the pins for the following purpose:

ADC control (through SPI)
Motor control (through SPI and GPIO)
LINE sensor control (control through GPIO and sync with ADC)

Can you answer the questions below in detail?

If they want to control SPI and GPIO in MAIN domain from the MCU domain what latency values should they expect? Should they be concerned with latency and its effect on real-time response?
What effects will there be the MAIN domain if they want to control SPI and GPIO in MAIN from MCU domain? For example, will performance decrease in MAIN domain if they try to control peripherals from MCU domain?
Are there interrupts they will not be able to use if they try to control SPI and GPIO in MAIN domain from MCU domain? Should they be aware of anything regarding interrupt usage?

On the other hand, in the situation where they try to control SPI and GPIO in MCU domain from MAIN domain, can you answer the following questions?

Are there interrupts they will not be able to use? Should they be aware of anything regarding interrupt usage?
What are ways for real-time transmission between MAIN and MCU domain? How can they do this? Is there any sample code for this they can reference?
Is there any way they can transfer data taken from the ADC that is connected to MCU domain to the MAIN domain without having drops in MAIN domain performance?
What are other ways to increase real-time performance?

Best regards,

Mari Tsunoda

10 months ago

0 Mukul Bhatnagar 10 months ago

TI__Guru* 82555 points

What OS are they planning to use?

0 Mari Tsunoda 10 months ago in reply to Mukul Bhatnagar

TI__Expert 4890 points

They are using Linux

0 Mari Tsunoda 9 months ago in reply to Mari Tsunoda

TI__Expert 4890 points

Hi Team,

Any update on this?

Best regards,

Mari Tsunoda

0 Mukul Bhatnagar 9 months ago

TI__Guru* 82555 points

Hello Mari

In general we do not recommend or expect users to use the M4 to control the peripherals in main domain. This is not an envisioned use-case , so there is not much system level analysis or performance data available and none planned.

At a high level GPIOs etc should be ok. There will likely be some additional delay accessing main domain GPIO registers from MCU domain (and vice versa). Some previously quick / informal bench data showed something to the order of 150 ns to A53 access main domain GPIO ( read from GPIO reg) and M4 taking about 270 ns for reading main GPIO (this is just to give you relative difference, might not be fully accurate)

Main SPI does not have interrupt connection going to M4, so I do not need recommend it being used for such a use-case

You can find the summary of various peripheral interrupt connectivity in the TRM , Chapter 10

https://www.ti.com/lit/ug/spruiv7b/spruiv7b.pdf

10.1.12 Interrupt Connections Summary

Additionally M4 on AM62 does not have cache, so if the user program/data for M4 does not fit on the on chip RAM and requires DDR, the access penalty is huge. You can refer to the following FAQ

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1187962/faq-sk-am62-how-to-execute-code-from-external-memory-using-m4f-core

We do not recommend that they actually "transmit" data between main and mcu , they should simply be using IPC / Rpmsg for communication and pointing to relevant buffers if needed

https://dev.ti.com/tirex/nodeContent?node=A__AVjm7chph.4Q-bCWodAr.w__AM62-ACADEMY__uiYMDcq__LATEST

IPC benchmarks are currently work in progress. Will need to get back to you next week to check the status ( expert is traveling this week)

0 Swargam Anil 9 months ago in reply to Mukul Bhatnagar

TI__Mastermind 38671 points

Hello Mari,

As Mukul mentioned the above points are all correct, users can't use the SPI peripheral in interrupt mode on the M4F core, and it does not have a cache and runs at lower frequencies.

See if you are able to move this application to the WKUP domain since WAKU core is R5F core, and it has a cache and runs at higher frequencies.

But, low power modes do not support on DM R5F core when you run applications on R5F core. Please look at more details in the link below.

An initial check, all MCSPI interrupts are routed to R5F core, and you can go with MCSPI on DM core with the interrupt mode.

https://software-dl.ti.com/mcu-plus-sdk/esd/AM62X/latest/exports/docs/api_guide_am62x/DEVELOP_AND_DEBUG_DMR5.html

Regards,

Anil.

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AM625: Controlling MAIN domain pins from MCU domain and vice versa