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TDA4VH-Q1: C7x DSPLIB SVD performance is much bad than running on A72

Tony Tang
Mastermind 30707 points

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Tool/software:

Customer test condition:

HW: TDA4VH EVM. 

SW: Based on Linux SDK 9.2. 

Algorithm: DSPLIB of MCU SDK9.2. 

Compile the SVD source code of c66x DSP Lib with gcc and run it on A72. 

Comparison: Same double float point 6x6 SVD on A72 takes 20us, but it takes about 90us with C7x DSPLib running on C7x DSP on TDA4VH EVM.

 I tested C7x DSPLIB 6x6 SVD double point on TDA4VH EVM got test result as below, although I don't understand the items, all larger than 20us.

Test Pass!
Test 0: Cold Cycles = 3767, Warm Cycles = 2178, Warm Cycles WRB = 2225
Test 14: Cold Cycles = 60108, Warm Cycles = 57954, Warm Cycles WRB = 58009
Test 49: Cold Cycles = 78972, Warm Cycles = 76077, Warm Cycles WRB = 76153
Test 50: Cold Cycles = 132887, Warm Cycles = 129085, Warm Cycles WRB = 129222

Question: Is it reasonable? if not, what is wrong with the test.

Supports needs: Could TI test DP SVD on ARM A72 core as upper to compare the performance? 

  • 0
    TI__Guru**** 503225 points

    hi Tony,

    DSPLib kernels are not optimized, so yes, there may not give optimal performance. 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    TI__Genius 10170 points

    Hi Tony,

    Let me clarify Brijesh's statement. The 9.2 SDK DSPLIB is optimized for C7x. For the case of SVD, the code is generally optimized for larger matrix sizes. As I have stated in our earlier thread, we do not have benchmarks between C7x and A72. As I requested in our earlier thread, if you know what the implementation they are running on A72 as a comparison, then we could potentially provide more feedback. 

    Related thread for reference: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1355375/tda4vh-q1-c71x-double-precision-dsplib

    Best,

    Asha

  • 0 in reply to Asha Bhandarkar
    TI__Mastermind 30707 points

    Hi Asha,

    Customer compiled the SVD source code of C66x DSP Library with gcc and run it on A72, get much better benchmark as upper.

  • 0 in reply to Tony Tang
    TI__Genius 10170 points

    Hi Tony,

    Okay, thank you the clarification on that! I've been in discussion with our C7x development team on this topic already. The SVD function was developed by another team. I'm reaching out to them to get a more detailed answer that I can provide you and customer regarding the implementation of the vectorized SVD function and its performance. Please expect a delay due to this, but I will do my best to provide an update by the end of the week from them. 

    Best,

    Asha

  • 0 in reply to Asha Bhandarkar
    TI__Genius 10170 points

    Hi Tony,

    Sorry for the delay in getting a response back to you. 

    In general, the optimization for the SVD function is focused on larger matrix sizes, more specifically SIMD width and greater (i.e. matrix sizes of 16x16, 32x32 and larger). In the 10.0 SDK, we will have some further general optimization improvements being released for the SVD function, so there should be some improvement for 6x6 double precision SVD than what you are currently testing in the 9.2 SDK. However, any further optimizations for smaller matrix sizes such as 6x6 are currently not in the scope for the function, so it is likely that in this particular case you will see better performance on A72. In general, since the C7x is a vector processor, the biggest performance gains will be seen with larger amounts of data processing. In the case of evaluating C7x functions, it is also always a case-by-case basis given how the algorithm scales to vector processing and based on the specific optimizations. To clarify that, just because SVD might perform better on A72 with these parameters in this use case, does not mean other functions on C7x will follow the same trend. 

    With regards to your question via messaging about the C66x SVD algorithm, that is optimized for the C66x scalar processor specifically and would not perform vector operations such as the C7x implementation. 

    Best,

    Asha

  • 0 in reply to Asha Bhandarkar
    TI__Mastermind 30707 points

    Hi Asha,

    Customer tested more larger matrix size, got data as below table, 

    Data of A72 is SVD function execution time, before provided 20us is the whole algorithm execution time.

    From the data, consider the CPU frequency in, C7x is also slow than A72 with 16x16 matrix.

    SVD Matrix size 6x6 16x16 32x32
    TDA4VH C71(us) 1GHz 59 199 552
    TDA4VH A72(us) 2GHz 7 66 374
  • 0 in reply to Tony Tang
    TI__Genius 10170 points

    Hi Tony,

    I apologize for the late response - I did not see you had updated this thread until now. Overall, if the execution time in microseconds that the customer is profiling match the cycle counts given in the test cases (note that the test cases profile the cycles of just the execute function), then that is the current performance of the SVD function. As I mentioned earlier, there will be improvements in the 10.0 SDK release that will result in lower cycle counts, especially for the 16x16 and 32x32 matrix sizes. Beyond that, I do not believe there is a roadmap for further work. 

    Best,

    Asha

  • 0 in reply to Asha Bhandarkar
    TI__Mastermind 30707 points

    Hi Asha,

    Customer's application can only use 6x6 or 6x7 SVD. 16x16 and larger matrix is not needed.

    Hope the 6x6 SVD performance will get much improved in SDK10.0

  • 0 in reply to Tony Tang
    TI__Genius 10170 points

    Hi Tony,

    I believe Wallace has responded to this request via email with details - this would be the most up to date information on where we stand with this. I have mentioned in an earlier message that further significant improvements for a 6x6 matrix were not in the scope of the 10.0 SDK release. 

    Best,

    Asha