AM3359: In AM3359 after RAMFS only 1 Ethernet Port is working

Hi, 

I am currently out of the office, I will need to research and will respond in a couple of days.

Best Regards,

Schuyler

Hi Schuyler Patton,

Please do needful..

Awaiting for your response

Regards

Vanam Bala Raju

Hi,

Let's only concentrate on the board that is not working. 

Some first thoughts is if the DTS for the 2 port has both ports configured. 

Could you please attach the bootlog for the 2nd board?

Best Regards,

Schuyler

Hi Schuyler,

Please find attached bootlog data and dts file

FYR..

Bootlog as below

<debug_uart> ti-i2c initialized....board detected..............>>>>>>>>>>>>>>>>>>>>>>
Timed out in wait_for_event: status=0000
�!���������������������������������detected..............>>>>>>>>>>>>>>>>************>>>>>>>>>>>>>>>>>>>>>>

U-Boot SPL 2018.01-gc14892445a-dirty (Jun 03 2024 - 20:53:45)
Trying to boot from NAND

U-Boot 2018.01-gc14892445a-dirty (Jun 03 2024 - 20:53:45 +0530)

CPU : AM335X-GP rev 2.1
Model: TI AM3359 ICE-V2
DRAM: 512 MiB
NAND: 512 MiB
MMC:
Net:
********************UBOOT MSCC.C vsc8531_config function*************************

>>>>>>>>>>>>>>>>>>>>>> init_b <<<<<<<<<<<<<<<<<<< u-boot <<<<<<<<<<<<<<<<<< mscc.c <<<<<<<<<<<<<<<<<<

********************UBOOT MSCC.C vsc8531_MAC_config function*************************

*****U-BOOT MSCC.C vsc8531_config_init function***** 31
cpsw, usb_ether
Hit any key to stop autoboot: 0
Booting from nand ...

NAND read: device 0 offset 0x80000, size 0x40000
262144 bytes read: OK

NAND read: device 0 offset 0x200000, size 0x1000000
16777216 bytes read: OK
## Flattened Device Tree blob at 88000000
Booting using the fdt blob at 0x88000000
Loading Device Tree to 8fff3000, end 8ffff49e ... OK

Starting kernel ...

[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.19.94 (root@rd07) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #230 PREEMPT Mon Jun 3 20:54:38 IST 2024
[ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] OF: fdt: Machine model: TI AM3359 ICE-V2
[ 0.000000] Memory policy: Data cache writeback
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: UEFI not found.
[ 0.000000] cma: Reserved 48 MiB at 0x9d000000
[ 0.000000] CPU: All CPU(s) started in SVC mode.
[ 0.000000] AM335X ES2.1 (sgx neon)
[ 0.000000] random: get_random_bytes called from start_kernel+0xa4/0x434 with crng_init=0
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 129920
[ 0.000000] Kernel command line: console=ttyO0,115200n8 root=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048 rootfstype=ubifs rootwait=1
[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[ 0.000000] Memory: 452876K/524288K available (9216K kernel code, 308K rwdata, 2724K rodata, 4096K init, 252K bss, 22260K reserved, 49152K cma-reserved, 0K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
[ 0.000000] vmalloc : 0xe0800000 - 0xff800000 ( 496 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xe0000000 ( 512 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0x(ptrval) - 0x(ptrval) (10208 kB)
[ 0.000000] .init : 0x(ptrval) - 0x(ptrval) (4096 kB)
[ 0.000000] .data : 0x(ptrval) - 0x(ptrval) ( 309 kB)
[ 0.000000] .bss : 0x(ptrval) - 0x(ptrval) ( 253 kB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
[ 0.000000] Tasks RCU enabled.
[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
[ 0.000000] OMAP clockevent source: timer2 at 25000000 Hz
[ 0.000018] sched_clock: 32 bits at 25MHz, resolution 40ns, wraps every 85899345900ns
[ 0.000041] clocksource: timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 76450417870 ns
[ 0.000053] OMAP clocksource: timer1 at 25000000 Hz
[ 0.000241] timer_probe: no matching timers found
[ 0.000444] Console: colour dummy device 80x30
[ 0.000476] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
[ 0.000483] This ensures that you still see kernel messages. Please
[ 0.000489] update your kernel commandline.
[ 0.000548] Calibrating delay loop... 795.44 BogoMIPS (lpj=3977216)
[ 0.089035] pid_max: default: 32768 minimum: 301
[ 0.089258] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.089275] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.090163] CPU: Testing write buffer coherency: ok
[ 0.090235] CPU0: Spectre v2: using BPIALL workaround
[ 0.091195] Setting up static identity map for 0x80100000 - 0x80100060
[ 0.091364] rcu: Hierarchical SRCU implementation.
[ 0.091742] EFI services will not be available.
[ 0.093272] devtmpfs: initialized
[ 0.101990] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
[ 0.102421] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.102447] futex hash table entries: 256 (order: -1, 3072 bytes)
[ 0.106532] pinctrl core: initialized pinctrl subsystem
[ 0.107402] DMI not present or invalid.
[ 0.107873] NET: Registered protocol family 16
[ 0.110569] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.136473] l4_wkup_cm:clk:0010:0: failed to disable
[ 0.189588] cpuidle: using governor ladder
[ 0.189632] cpuidle: using governor menu
[ 0.195243] OMAP GPIO hardware version 0.1
[ 0.204453] No ATAGs?
[ 0.204468] hw-breakpoint: debug architecture 0x4 unsupported.
[ 0.220007] edma 49000000.edma: TI EDMA DMA engine driver
[ 0.223322] SCSI subsystem initialized
[ 0.223841] media: Linux media interface: v0.10
[ 0.223901] videodev: Linux video capture interface: v2.00
[ 0.224005] pps_core: LinuxPPS API ver. 1 registered
[ 0.224016] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 0.224041] PTP clock support registered
[ 0.224078] EDAC MC: Ver: 3.0.0
[ 0.225284] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
[ 0.225932] Advanced Linux Sound Architecture Driver Initialized.
[ 0.227272] clocksource: Switched to clocksource timer1
[ 0.236578] NET: Registered protocol family 2
[ 0.237591] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes)
[ 0.237632] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.237682] TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.237729] TCP: Hash tables configured (established 4096 bind 4096)
[ 0.237846] UDP hash table entries: 256 (order: 0, 4096 bytes)
[ 0.237868] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
[ 0.238035] NET: Registered protocol family 1
[ 0.238689] RPC: Registered named UNIX socket transport module.
[ 0.238705] RPC: Registered udp transport module.
[ 0.238713] RPC: Registered tcp transport module.
[ 0.238720] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.502914] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
[ 0.504433] Initialise system trusted keyrings
[ 0.504766] workingset: timestamp_bits=14 max_order=17 bucket_order=3
[ 0.510165] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 0.510985] NFS: Registering the id_resolver key type
[ 0.511032] Key type id_resolver registered
[ 0.511040] Key type id_legacy registered
[ 0.511096] ntfs: driver 2.1.32 [Flags: R/O].
[ 0.513636] Key type asymmetric registered
[ 0.513658] Asymmetric key parser 'x509' registered
[ 0.513739] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[ 0.513755] io scheduler noop registered
[ 0.513763] io scheduler deadline registered
[ 0.514031] io scheduler cfq registered (default)
[ 0.514043] io scheduler mq-deadline registered
[ 0.514052] io scheduler kyber registered
[ 0.515932] pinctrl-single 44e10800.pinmux: 142 pins, size 568
[ 0.515954] pinctrl-single 44e10800.pinmux: <<<<<<<<<<<<<<<<<<<<<<<< Added VSC8531 RESET >>>>>>>>>>>>>>>>>>>>>>>>>
[ 0.682161] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
[ 0.686464] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 30, base_baud = 3000000) is a 8250
[ 1.315559] console [ttyS0] enabled
[ 1.320385] 48022000.serial: ttyS1 at MMIO 0x48022000 (irq = 31, base_baud = 3000000) is a 8250
[ 1.330425] 481a8000.serial: ttyS4 at MMIO 0x481a8000 (irq = 32, base_baud = 3000000) is a 8250
[ 1.341325] omap_rng 48310000.rng: Random Number Generator ver. 20
[ 1.347787] random: fast init done
[ 1.351442] random: crng init done
[ 1.369170] brd: module loaded
[ 1.379808] loop: module loaded
[ 1.384543] <<<<<<<<<<<<<<<<<<<<***************SPI Slave Intialized>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
[ 1.399873] <<<<<<<<<<<<<<<<<<<<***************SPI Slave Intialized>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
[ 1.414807] libphy: Fixed MDIO Bus: probed
[ 1.487363] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
[ 1.495075] libphy: 4a101000.mdio: probed
[ 1.509405] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver Microsemi VSC8531
[ 1.518495] davinci_mdio 4a101000.mdio: phy[3]: device 4a101000.mdio:03, driver Microsemi VSC8531
[ 1.528669] cpsw 4a100000.ethernet: Detected MACID = 14:7f:0f:e5:26:ec
[ 1.535374] cpsw 4a100000.ethernet: initialized cpsw ale version 1.4
[ 1.541903] cpsw 4a100000.ethernet: ALE Table size 1024
[ 1.547196] cpsw 4a100000.ethernet: cpts: overflow check period 500 (jiffies)
[ 1.555384] cpsw 4a100000.ethernet: cpsw: Detected MACID = 14:7f:0f:e5:26:ee
[ 1.563858] >>>>>>>>>>>>>>>>>>>>>Entered into spi_nor_read_id function_1<<<<<<<<<<<<<<<<<<<<<<<
[ 1.564129] >>>>>>>>>>>>>>>>>>>>>Entered into spi_nor_read_id function_5<<<<<<<<<<<<<<<<<<<<<<<
[ 1.572921] >>>>>>>>>>>>>>>>>>>Temp Value is >>>>>>>>>>>>>>>>>>>. 0
[ 1.587970] >>>>>>>>>>>>>>>>>>>Info Value is >>>>>>>>>>>>>>>>>>>. 5
[ 1.594261] >>>>>>>>>>>>>>>>>>>>>Entered into spi_nor_read_id function_3<<<<<<<<<<<<<<<<<<<<<<<
[ 1.594279] m25p80_SBR-GCM spi1.0: unrecognized JEDEC id bytes: ff, ff, ff, ff, ff, ff, 0
[ 1.611586] m25p80_SBR-GCM spi1.0: n25q256a (32768 Kbytes)
[ 1.617132] 1 fixed-partitions partitions found on MTD device spi1.0
[ 1.623539] Creating 1 MTD partitions on "spi1.0":
[ 1.628377] 0x000000000000-0x000002000000 : "spi1_partition_SBR-GCM"
[ 1.637741] i2c /dev entries driver
[ 1.643742] cpuidle: enable-method property 'ti,am3352' found operations
[ 1.651064] sdhci: Secure Digital Host Controller Interface driver
[ 1.657401] sdhci: Copyright(c) Pierre Ossman
[ 1.662286] sdhci-pltfm: SDHCI platform and OF driver helper
[ 1.668625] ledtrig-cpu: registered to indicate activity on CPUs
[ 1.679315] NET: Registered protocol family 10
[ 1.685337] Segment Routing with IPv6
[ 1.689307] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[ 1.696038] NET: Registered protocol family 17
[ 1.700937] Key type dns_resolver registered
[ 1.705512] omap_voltage_late_init: Voltage driver support not added
[ 1.713037] Loading compiled-in X.509 certificates
[ 1.729844] omap-gpmc 50000000.gpmc: GPMC revision 6.0
[ 1.735029] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[ 1.742924] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xdc
[ 1.749461] nand: Micron MT29F4G08ABADAWP
[ 1.753494] nand: 512 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
[ 1.761210] nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme
[ 1.766709] 10 fixed-partitions partitions found on MTD device omap2-nand.0
[ 1.773738] Creating 10 MTD partitions on "omap2-nand.0":
[ 1.779193] 0x000000000000-0x000000020000 : "NAND.SPL"
[ 1.785582] 0x000000020000-0x000000040000 : "NAND.SPL.backup1"
[ 1.792504] 0x000000040000-0x000000060000 : "NAND.SPL.backup2"
[ 1.799381] 0x000000060000-0x000000080000 : "NAND.SPL.backup3"
[ 1.806175] 0x000000080000-0x0000000c0000 : "NAND.u-boot-spl-os"
[ 1.813306] 0x0000000c0000-0x0000001c0000 : "NAND.u-boot"
[ 1.820137] 0x0000001c0000-0x0000001e0000 : "NAND.u-boot-env"
[ 1.826823] 0x0000001e0000-0x000000200000 : "NAND.u-boot-env.backup1"
[ 1.834315] 0x000000200000-0x000001200000 : "NAND.kernel"
[ 1.848192] 0x000000e00000-0x000002000000 : "NAND.file-system"
[ 1.863589] gpmc_read_settings_dt: page/burst-length set but not used!
[ 2.887337] omap_i2c 44e0b000.i2c: timeout waiting for bus ready
[ 2.893700] tps65910 0-002d: No interrupt support, no core IRQ
[ 3.917333] omap_i2c 44e0b000.i2c: timeout waiting for bus ready
[ 3.923500] tps65910-pmic: probe of tps65910-pmic failed with error -16
[ 3.931390] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
[ 3.939220] omap_i2c 4802a000.i2c: bus 1 rev0.11 at 500 kHz
[ 3.945331] ubi0: attaching mtd10
[ 4.004533] ubi0: scanning is finished
[ 4.008426] ubi0 error: ubi_read_volume_table: the layout volume was not found
[ 4.015889] ubi0 error: ubi_attach_mtd_dev: failed to attach mtd10, error -22
[ 4.023139] UBI error: cannot attach mtd10
[ 4.027730] hctosys: unable to open rtc device (rtc0)
[ 4.033414] ALSA device list:
[ 4.036402] No soundcards found.
[ 4.039973] Warning: unable to open an initial console.
[ 4.050851] Freeing unused kernel memory: 4096K
[ 4.055950] Run /init as init process
[ 5.849740] net eth0: initializing cpsw version 1.12 (0)
[ 5.957320]
[ 5.957320] ****************** *KERNEL MSCC.C vsc85xx_config_init function*************************
[ 5.968755]
[ 5.968755] *****KERNEL MSCC.C vsc85xx_default_config function_Before*****=31
[ 5.977846]
[ 5.977846] *****KERNEL MSCC.C vsc85xx_default_config function*****=31
[ 6.079897] Microsemi VSC8531 4a101000.mdio:00: attached PHY driver [Microsemi VSC8531] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
[ 6.097218] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready

_____ _____ _ _
| _ |___ ___ ___ ___ | _ |___ ___ |_|___ ___| |_
| | _| .'| . | . | | __| _| . | | | -_| _| _|
|__|__|_| |__,|_ |___| |__| |_| |___|_| |___|___|_|
|___| |___|

Arago Project http://arago-project.org am335x-evm /dev/ttyS0

Arago 2020.09 am335x-evm /dev/ttyS0

am335x-evm login: root
root@am335x-evm:~#
root@am335x-evm:~#
root@am335x-evm:~# [ 34.407365] vbat: disabling

Requesting you to pls do needful asap

Hi Schuyler,

DTS file as below

/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/

/*
* AM335x ICE V2 board
* www.ti.com/.../tmdsice3359
*/

/dts-v1/;

#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/net/mscc-phy-vsc8531.h>

/ {
model = "TI AM3359 ICE-V2";
compatible = "ti,am3359-icev2", "ti,am33xx";

memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};

chosen {
stdout-path = &uart0;
};

vbat: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
/*
vtt_fixed: fixedregulator1 {
compatible = "regulator-fixed";
regulator-name = "vtt";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
};
*/
/*
leds-iio {
status = "disabled";
compatible = "gpio-leds";
led-out0 {
label = "out0";
gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
};

led-out1 {
label = "out1";
gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};

led-out2 {
label = "out2";
gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};

led-out3 {
label = "out3";
gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};

led-out4 {
label = "out4";
gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};

led-out5 {
label = "out5";
gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};

led-out6 {
label = "out6";
gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};

led-out7 {
label = "out7";
gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};

gpio-decoder {
compatible = "gpio-decoder";
gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>,
<&pca9536 2 GPIO_ACTIVE_HIGH>,
<&pca9536 1 GPIO_ACTIVE_HIGH>,
<&pca9536 0 GPIO_ACTIVE_HIGH>;
linux,axis = <0>; // ABS_X
decoder-max-value = <9>;
};
*/

};

&am33xx_pinmux {

i2c0_pins_default: i2c0_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
>;
};

#if 0
/* Not used in MGCM*/
i2c2_pins_default: i2c2_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x95C, PIN_INPUT | MUX_MODE3) /* (B16) I2C2_SDA.I2C2_SDA */
AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE3) /* (A16) I2C2_SCL.I2C2_SCL */
>;
};

#endif

/* I2C 1 added in MGCM */
i2c1_pins_default: i2c1_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE3) /* (J15) i2c1_scl*/
AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE3) /* (H17) i2c1_sda */

>;
};

#if 0
gpio0_pins_default: gpio0_pins_default {
pinctrl-single,pins = <

AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE7) /* (C18) eCAP0_in_PWM0_out.gpio0[7] */ /*added by astra*/
AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* (D17) uart1_rtsn.gpio0[13] */ /*added by astra*/
AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* (D18) uart1_ctsn.gpio0[12] */ /*added by astra*/
AM33XX_IOPAD(0x944, PIN_INPUT_PULLUP | MUX_MODE7) /* (H18) USB1_DRVVBUS.gpio0[29] */ /*added for program_b pin for fpga*/
>;
};
gpio1_pins_default: gpio1_pins_default {
pinctrl-single,pins = <
/*AM33XX_IOPAD(0x858, PIN_INPUT_PULLUP | MUX_MODE7)*/ /*U15 - GPIO1_22 VSC8531 RESET*/
>;
};
#endif

gpio2_pins_default: gpio2_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE7) /* (F16) M0 lcd_ac_bias_en.gpio2[25]*/
/*AM33XX_IOPAD(0xa34, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (F15) USB1_DRVVBUS.gpio3[13] */ /*added for vsc8531*/
AM33XX_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE7) /* (F15) USB1_DRVVBUS.gpio3[13] */ /*added for vsc8531*/
/*AM33XX_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE7) /* (F15) M0 lcd_ac_bias_en.gpio2[25]*/
AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLUP | MUX_MODE7) /* (R6) lcd_ac_bias_en.gpio2[25]*/
AM33XX_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (G18) mmc0_dat0.gpio2[29] */ /*required gpio95 muxctl commented for testing*/
>;
};

gpio3_pins_default: gpio3_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLUP | MUX_MODE7) /* (D13) gpio3[20] */
AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE7) /* (A14) mcasp0_ahclkx.gpio3[21] */
AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE7) /* (F17) mmc0_dat3.gpio2[26] */
AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE7) /* (F18) mmc0_dat1.gpio2[28] */
AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE7) /* (G15) mmc0_dat0.gpio2[29] */
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (G16) mmc0_dat0.gpio2[29] */
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE7) /* (G17) mmc0_dat0.gpio2[29] */
/*AM33XX_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7)*/ /* (G18) mmc0_dat0.gpio2[29] */
AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */

AM33XX_IOPAD(0x9a4, PIN_INPUT_PULLUP | MUX_MODE7) /* (C13) mcasp0_fsr.gpio3[19] */ /*added by astra*/

>;
};

//#if 1
spi0_pins_default: spi0_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0)/* (C15) spi0_cs1.spi0_cs1 */
/*AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7)*/ /* (B12) mcasp0_aclkr.gpio3[18] */
>;
};
spi1_pins_default: spi1_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x990, PIN_INPUT_PULLUP | MUX_MODE3) /* (A13) mcasp0_aclkx.spi1_sclk */
AM33XX_IOPAD(0x994, PIN_INPUT_PULLUP | MUX_MODE3) /* (B13) mcasp0_fsx.spi1_d0 */
AM33XX_IOPAD(0x998, PIN_INPUT_PULLUP | MUX_MODE3) /* (D12) mcasp0_axr0.spi1_d1 */
AM33XX_IOPAD(0x99c, PIN_INPUT_PULLUP | MUX_MODE3) /* (C12) mcasp0_ahclkr.spi1_cs0 */
>;
};

//#endif
/*DEBUG UART*/
uart0_pins_default: uart0_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLUP | MUX_MODE0) /* (E16) uart0_txd.uart0_txd */
>;
};

/*HSKP UART FROM GCM TO SGCM*/
uart1_pins_default: uart1_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* (D16) uart1_rxd.uart1_rxd */
AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLUP | MUX_MODE0) /* (D15) uart1_txd.uart1_txd */
>;
};

/*Processor to FPGA, UART*/
uart4_pins_default: uart4_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE1) /* (E18) uart4_rxd */
AM33XX_IOPAD(0x96c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*(E17) uart4_txd */
>;
};

cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */

AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
/*AM33XX_IOPAD(0xA34, PIN_INPUT_PULLUP | MUX_MODE7) /* (F15) USB1_DRVVBUS.gpio3[13] */

/*pinmux for max24288*/
AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
>;
};

cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <

AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (J16) gmii1_txen.rgmii1_tctl */
AM33XX_IOPAD(0x918, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (J17) gmii1_rxdv.rgmii1_rctl */
AM33XX_IOPAD(0x92c, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (K18) gmii1_txclk.rgmii1_tclk */
AM33XX_IOPAD(0x930, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (L18) gmii1_rxclk.rgmii1_rclk */
AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (K17) gmii1_txd0.rgmii1_td0 */
AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (K16) gmii1_txd1.rgmii1_td1 */
AM33XX_IOPAD(0x920, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (K15) gmii1_txd2.rgmii1_td2 */
AM33XX_IOPAD(0x91c, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (J18) gmii1_txd3.rgmii1_td3 */
AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (M16) gmii1_rxd0.rgmii1_rd0 */
AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (L15) gmii1_rxd1.rgmii1_rd1 */
AM33XX_IOPAD(0x938, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (L16) gmii1_rxd2.rgmii1_rd2 */
AM33XX_IOPAD(0x934, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (L17) gmii1_rxd3.rgmii1_rd3 */
/*AM33XX_IOPAD(0xA34, PIN_OUTPUT_PULLDOWN | MUX_MODE7)*/
/* Slave 2 reset value*/

AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)

>;
};

davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)) /* mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0)) /* mdio_clk.mdio_clk */

/* AM33XX_IOPAD(0x88C, (PIN_OUTPUT_PULLUP | MUX_MODE5) ) /* (V12) gpmc_clk.pr1_mdio_mdclk */
/* AM33XX_IOPAD(0x888, (PIN_INPUT_PULLUP | MUX_MODE5) ) /* (T13) gpmc_csn3.pr1_mdio_data*/

>;
};

davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
>;
};

nandflash_pins_s0: nandflash_pins_s0 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE0) /*gpmc_ad8.gpmc.ad8*/
AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE0) /*gpmc_ad9.gpmc.ad9*/
AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE0) /*gpmc_ad10.gpmc.ad10*/
AM33XX_IOPAD(0x82C, PIN_INPUT_PULLUP | MUX_MODE0) /*gpmc_ad11.gpmc.ad11*/
AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE0) /*gpmc_ad12.gpmc.ad12*/
AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE0) /*gpmc_ad13.gpmc.ad13*/
AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE0) /*gpmc_ad14.gpmc.ad14*/
AM33XX_IOPAD(0x83C, PIN_INPUT_PULLUP | MUX_MODE0) /*gpmc_ad15.gpmc.ad15*/

AM33XX_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE0) /*gpmc_ben1*/
AM33XX_IOPAD(0x884, PIN_OUTPUT_PULLUP | MUX_MODE0) /*gpmc_csn2*/
/*AM33XX_IOPAD(0x888, PIN_OUTPUT_PULLUP | MUX_MODE0)*/ /* (T13) gpmc_csn3.gpmc_csn3 */
/*AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE0)*/ /*gpmc_csn1.gpmc_csn1*/
AM33XX_IOPAD(0x880, PIN_OUTPUT_PULLUP | MUX_MODE0) /*gpmc_csn1.gpmc_csn1*/
/* AM33XX_IOPAD(0x88C, PIN_INPUT | MUX_MODE0) */ /*gpmc_clk.gpmc_clk*/

AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
/*AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE0)*/ /* gpmc_wpn.gpio0_30 */
AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wpn.gpio0_30 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */

>;
};

/* test_keys: test_keys {
pinctrl-single,pins = <
AM33XX_IOPAD(0x858, PIN_INPUT_PULLUP | MUX_MODE7) //U15 - GPIO1_22 VSC8531 RESET//
>;
};*/
};

&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_default>;

status = "okay";
clock-frequency = <400000>;

tps: power-controller@2d {
reg = <0x2d>;
};
/*
tpic2810: gpio@60 {
compatible = "ti,tpic2810";
reg = <0x60>;
gpio-controller;
#gpio-cells = <2>;
};

pca9536: gpio@41 {
compatible = "ti,pca9536";
reg = <0x41>;
gpio-controller;
#gpio-cells = <2>;
};
*/
};
#if 0
&i2c1{
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_default>;

compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
reg = <0x4802a000 0x1000>;
interrupts = <71>;

status = "okay";
clock-frequency = <500000>;
ad7414@48 {
compatible = "analog,ad7414";
reg = <0x48>;
status = "okay";
};
};
#endif

/*I2C inteface b/w Processor and FPGA*/
&i2c1{
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_default>;

status = "okay";
clock-frequency = <500000>; /*for 400KHz added by Chinmay*/
/*ad7414@4A {
compatible = "analog,ad7414";
reg = <0x4A>;
status = "okay";
};*/
};
/*
#if 0
&i2c2{
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_default>;

status = "okay";
ad7414@48 {
compatible = "analog,ad7414";
reg = <0x48>;
status = "okay";
};
};
#endif
*/

&rtc {
status = "disabled";
};

&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins_default>;
spi_fpga@0 {
#address-cells = <1>;
#size-cells = <1>;

/*compatible = "mycompany,myspi"; */
compatible = "linux,spidev";
/*compatible = "winbond,w25q64", "jedec,spi-nor" , "linux,spidev";*/
spi-max-frequency = <48000000>; /* 20 mhz */
m25p,fast-read;
/* spi-cpha;*/
reg =<0>;// <1>;
};

spi_fpga_1@1 {
#address-cells = <1>;
#size-cells = <1>;

/*compatible = "mycompany,myspi"; */
compatible = "linux,spidev";
/*compatible = "winbond,w25q64", "jedec,spi-nor" , "linux,spidev";*/
spi-max-frequency = <48000000>; /* 20 mhz */
m25p,fast-read;
/* spi-cpha;*/
reg =<1>;// <1>;
};

};

&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_default>;

spidev@0 {
#address-cells = <1>;
#size-cells = <1>;
//compatible = "mt25q256","jedec,spi-nor";
compatible = "n25q256a","jedec,spi-nor";
/*compatible = "linux,spidev";*/
spi-max-frequency = <2000000>;
m25p,fast-read;
reg = <0x0>;

partition@0 {
label = "spi1_partition_SBR-GCM";
reg = <0x0 0x2000000>;
};
};
};

&tscadc {
status = "okay";
adc {
ti,adc-channels = <1 2 3 4 5 6 7>;
};
};

#include "tps65910.dtsi"
&tps {
vcc1-supply = <&vbat>;
vcc2-supply = <&vbat>;
vcc3-supply = <&vbat>;
vcc4-supply = <&vbat>;
vcc5-supply = <&vbat>;
vcc6-supply = <&vbat>;
vcc7-supply = <&vbat>;
vccio-supply = <&vbat>;

regulators {
vrtc_reg: regulator@0 {
regulator-always-on;
};

vio_reg: regulator@1 {
regulator-always-on;
};

vdd1_reg: regulator@2 {
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1326000>;
regulator-boot-on;
regulator-always-on;
};

vdd2_reg: regulator@3 {
regulator-name = "vdd_core";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1144000>;
regulator-boot-on;
regulator-always-on;
};

vdd3_reg: regulator@4 {
regulator-always-on;
};

vdig1_reg: regulator@5 {
regulator-always-on;
};

vdig2_reg: regulator@6 {
regulator-always-on;
};

vpll_reg: regulator@7 {
regulator-always-on;
};

vdac_reg: regulator@8 {
regulator-always-on;
};

vaux1_reg: regulator@9 {
regulator-always-on;
};

vaux2_reg: regulator@10 {
regulator-always-on;
};

vaux33_reg: regulator@11 {
regulator-always-on;
};

vmmc_reg: regulator@12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};

#if 0
&gpio0 {
/* Do not idle the GPIO used for holding the VTT regulator */
ti,no-reset-on-init;
ti,no-idle-on-init;
pinctrl-names = "default";
pinctrl-0 = <&gpio0_pins_default>;
status = "okay";
};

&gpio1 {
/* Do not idle the GPIO used for holding the VTT regulator */
ti,no-reset-on-init;
ti,no-idle-on-init;
pinctrl-names = "default";
pinctrl-0 = <&gpio1_pins_default>;
status = "okay";
};

#endif

&gpio2 {
/* Do not idle the GPIO used for holding the VTT regulator */
ti,no-reset-on-init;
ti,no-idle-on-init;
pinctrl-names = "default";
pinctrl-0 = <&gpio2_pins_default>;
status = "okay";

};

&gpio3 {
/* Do not idle the GPIO used for holding the VTT regulator */
ti,no-reset-on-init;
ti,no-idle-on-init;
pinctrl-names = "default";
pinctrl-0 = <&gpio3_pins_default>;
status = "okay";

};

/*DEBUG UART*/
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_default>;
status = "okay";
};

/*HSKP UART*/
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_default>;
status = "okay";
};

/*Processor to FPGA, UART*/
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_default>;
status = "okay";
};

&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
slaves = <2>;
dual_emac;
status = "okay";
};

&davinci_mdio {

pinctrl-names = "default", "sleep";
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";

#if 1
vsc8531_3: ethernet-phy@3 {
compatible = "ethernet-phy-id0007.0570";
reg = <3>;
vsc8531,vddmac = <3300>;
vsc8531,edge-slowdown = <7>;
vsc8531,led-0-mode = <VSC8531_LINK_1000_ACTIVITY>;
vsc8531,led-1-mode = <VSC8531_LINK_100_ACTIVITY>;
};

vsc8531_0: ethernet-phy@0 {
compatible = "ethernet-phy-id0007.0570";
reg = <0>;
vsc8531,vddmac = <3300>;
vsc8531,edge-slowdown = <7>;
vsc8531,led-0-mode = <VSC8531_LINK_1000_ACTIVITY>;
vsc8531,led-1-mode = <VSC8531_LINK_100_ACTIVITY>;
};

#endif
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
};

/*
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii";
};
*/
&elm{
status = "okay";
};

&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins_s0>;
ranges = <0 0 0x08000000 0x01000000>, /*CSn0 for NAND*/
<2 0 0x09000000 0x01000000>; /*CSn2 for FPGA*/
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000C0000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001C0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x001E0000 0x00020000>;
};
/*
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00A00000 0x0F600000>;
};
*/

partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x1000000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00E00000 0x01200000>;
};
};

fpga@2,0{
reg = <2 0 0x01000000>; /*CSn2*/
compatible = "cet,am335x-dma-test";
/*#address-cells = <1>;*/
#address-cells = <2>;
#size-cells = <1>;
bank-width = <2>; /* GPMC_CONFIG1_DEVICESIZE(1) *//*16 bit wide*/
interrupt-parent = <&gpmc>;
interrupts = <0 0>, <1 0>;
/*gpmc,burst-write;*/
/*gpmc,burst-read;*/
/*gpmc,burst-wrap;*/
gpmc,sync-read; /* GPMC_CONFIG1_READTYPE_ASYNC */
gpmc,sync-write; /* GPMC_CONFIG1_WRITETYPE_ASYNC */
gpmc,clk-activation-ns = <0>; /* GPMC_CONFIG1_CLKACTIVATIONTIME(2) */
gpmc,burst-length = <16>; /* GPMC_CONFIG1_PAGE_LEN(2) */
gpmc,mux-add-data = <0>; /* GPMC_CONFIG1_MUXTYPE(2) */

gpmc,sync-clk-ps = <0>; /* CONFIG2 20000*/

gpmc,cs-on-ns = <10>; /*10*/
//gpmc,cs-rd-off-ns = <30>; /*default 100*/
gpmc,cs-rd-off-ns = <30>; /*default 100*/
gpmc,cs-wr-off-ns = <0>; /*10*/

gpmc,adv-on-ns = <0>; /* CONFIG3 */
gpmc,adv-rd-off-ns = <10>;
gpmc,adv-wr-off-ns = <0>; /*10*/

gpmc,we-on-ns = <0>; /*10*//* CONFIG4 */
gpmc,we-off-ns = <0>;/*10*/
gpmc,oe-on-ns = <10>;
gpmc,oe-off-ns = <30>;/*100*/

gpmc,page-burst-access-ns = <10>; /* CONFIG 5 */
gpmc,access-ns = <10>; /*80*/
gpmc,rd-cycle-ns = <20>;/*default 120*/
//gpmc,wr-cycle-ns = <0>;/*60*/
gpmc,wr-cycle-ns = <0>;/*60*/
gpmc,wr-access-ns = <10>; /* CONFIG 6 */
gpmc,wr-data-mux-bus-ns = <20>;

gpmc,bus-turnaround-ns = <40>; /* CONFIG6:3:0 = 4 */
gpmc,cycle2cycle-samecsen; /* CONFIG6:7 = 1 */
gpmc,cycle2cycle-delay-ns = <20>; /* CONFIG6:11:8 = 4 */

/* not using dma engine yet, but we can get the channel number here */
/* dmas = <&edma 1>;*/
/* dma-names = "rxtx";*/
};
};

Hi,

At the moment I am not seeing an error in the DTS. The PHYs for the ports are being identified. The DTS and boot log need to be made into attachments as the cut and paste is making the navigating the thread hard to do.

Please attach the results of the following after the system boots:

- ifconfig -a    (Looking to see what the interface list is saying, it should report both eth0 and eth1

- ethtool eth0   (Looking to see a link status detected, may not be the case with the message reported)

I am assuming eth0 is connected to a link partner? The post says something about eth1 but I am not sure eth0 is working correctly based on what I am seeing.

Best Regards,

Schuyler

https://e2e.ti.com/home/rd-07/Documents/MGCM_RAMFS_bootlog_08072024

Hi Schuyler,

Sorry for the late reply..

i was on personal leave

ETH0 is working fine Eth1 is not working..

please find attachments..

Please verify and do neeful..

thank you

Regards

Vanam Bala Raju

Hi,

Unfortunately I am not able to look at any of the attachments in your post. Could you retry to attach the your test results?

Best Regards,

Schuyler

Hi Schuyler,

Awaiting for your reply..

Regards

Vanam Bala Raju

Hi,

I am seeing both cpsw interfaces initializing and the boot log shows 2 PHYs are being identified. What I don't see in the boot log is the link coming up on either interface. Assuming that you have a cable plugged into one of the ports (eth0 for example) there should have been a link up message.

What does ethtool eth0 show? Here we are looking for a link detected.

And what does ethtool -S eth0 show? This will packets at the hw mac being received and sent.

Best Regards,

Schuyler