Other Parts Discussed in Thread: AM6548
Tool/software:
Hi,
This question targets mainly the CCMR5 design details of the AM65x SoC.
I was figuring out whether the CCM-R5 module in the AM6548 SoC has similar behavior compared to the CCM-R4 located in the Cortex-R4. For the CCM-R4, there has figure such as:
(credit to [0])
which explains the internals of the module, in which it shows that the output of CPU1 does not delayed by the "2 cycle delay". However, I didn't find a similar one for the TI-integrated Cortex-R5 SoC, which got me wondering whether the R5 core (w/ lockstep enabled) in the AM65x is also not delayed by the comparison logic.
For now, I'm speculating that it is NOT delayed by the comparison logic, because I've done a FFT benchmark on the R5 core, w/ and w/o Lockstep being enabled. The result shows that, the two modes have the SAME benchmark results. That is, the FFT calculation latencies of both modes have the exact same result, 764us. Also, I ensured that the Lockstep mode has been configured correctly by checking the SBL log.
In spite of the test result, the TRM does not explicitly says that there would be no performance regression when the core is configured with the Lockstep mode. However, the AM65x TRM did say the following:
> All outputs from CPU0 are copied, delayed by two cycles, and compared to the outputs of CPU1.
The "All outputs from CPU0 are copied" statement, to me, seems implying that there would be no performance regression in the Lockstep mode since the output is copied instead of "waiting the comparison to be finished".
So, can TI people tell whether there has no performance regression when the Lockstep mode is enabled?
Thanks!
