AM62A7-Q1: CSI2RX: What's the best way to bring up a new sensor?

Hi Bas,

Our CSI expert is traveling. Please expect delayed response.

I have created a script that dumps the register space of the CSI2RX module:

#!/bin/bash

register () {
	echo "$1 ($2) = " $(devmem2 $2 w | grep "Read at address" | awk 'FS=" " { print $6 }')
}

register csi_rx_if_REVISION 0x30100000
register csi_rx_if_eoi_reg 0x30100010
register csi_rx_if_intr_vector_reg 0x30100014
register csi_rx_if_enable_reg_level_0 0x30100100
register csi_rx_if_enable_reg_pulse_0 0x30100104
register csi_rx_if_enable_clr_reg_level_0 0x30100300
register csi_rx_if_enable_clr_reg_pulse_0 0x30100304
register csi_rx_if_status_reg_level_0 0x30100500
register csi_rx_if_status_reg_pulse_0 0x30100504
register csi_rx_if_status_clr_reg_level_0 0x30100700
register csi_rx_if_status_clr_reg_pulse_0 0x30100704
register csi_rx_if_intr_vector_reg_level 0x30100a80
register csi_rx_if_intr_vector_reg_pulse 0x30100a84


register csi_rx_if_device_config 0x30101000
register csi_rx_if_soft_reset 0x30101004
register csi_rx_if_static_cfg 0x30101008
register csi_rx_if_error_bypass_cfg 0x30101010
register csi_rx_if_monitor_irqs 0x30101018
register csi_rx_if_monitor_irqs_mask_cfg 0x3010101c
register csi_rx_if_info_irqs 0x30101020
register csi_rx_if_info_irqs_mask_cfg 0x30101024
register csi_rx_if_error_irqs 0x30101028
register csi_rx_if_error_irqs_mask_cfg 0x3010102c
register csi_rx_if_dphy_lane_control 0x30101040
register csi_rx_if_dphy_status 0x30101048
register csi_rx_if_dphy_err_status_irq 0x3010104c
register csi_rx_if_dphy_err_irq_mask_cfg 0x30101050
register csi_rx_if_integration_debug 0x30101060
register csi_rx_if_error_debug 0x30101074
register csi_rx_if_test_generic 0x30101080
register csi_rx_if_stream0_ctrl 0x30101100
register csi_rx_if_stream0_status 0x30101104
register csi_rx_if_stream0_data_cfg 0x30101108
register csi_rx_if_stream0_cfg 0x3010110c
register csi_rx_if_stream0_monitor_ctrl 0x30101110
register csi_rx_if_stream0_monitor_frame 0x30101114
register csi_rx_if_stream0_monitor_lb 0x30101118
register csi_rx_if_stream0_timer 0x3010111c
register csi_rx_if_stream0_fcc_cfg 0x30101120
register csi_rx_if_stream0_fcc_ctrl 0x30101124
register csi_rx_if_stream0_fifo_fill_lvl 0x30101128
register csi_rx_if_stream1_ctrl 0x30101200
register csi_rx_if_stream1_status 0x30101204
register csi_rx_if_stream1_data_cfg 0x30101208
register csi_rx_if_stream1_cfg 0x3010120c
register csi_rx_if_stream1_monitor_ctrl 0x30101210
register csi_rx_if_stream1_monitor_frame 0x30101214
register csi_rx_if_stream1_monitor_lb 0x30101218
register csi_rx_if_stream1_timer 0x3010121c
register csi_rx_if_stream1_fcc_cfg 0x30101220
register csi_rx_if_stream1_fcc_ctrl 0x30101224
register csi_rx_if_stream1_fifo_fill_lvl 0x30101228
register csi_rx_if_stream2_ctrl 0x30101300
register csi_rx_if_stream2_status 0x30101304
register csi_rx_if_stream2_data_cfg 0x30101308
register csi_rx_if_stream2_cfg 0x3010130c
register csi_rx_if_stream2_monitor_ctrl 0x30101310
register csi_rx_if_stream2_monitor_frame 0x30101314
register csi_rx_if_stream2_monitor_lb 0x30101318
register csi_rx_if_stream2_timer 0x3010131c
register csi_rx_if_stream2_fcc_cfg 0x30101320
register csi_rx_if_stream2_fcc_ctrl 0x30101324
register csi_rx_if_stream2_fifo_fill_lvl 0x30101328
register csi_rx_if_stream3_ctrl 0x30101400
register csi_rx_if_stream3_status 0x30101404
register csi_rx_if_stream3_data_cfg 0x30101408
register csi_rx_if_stream3_cfg 0x3010140c
register csi_rx_if_stream3_monitor_ctrl 0x30101410
register csi_rx_if_stream3_monitor_frame 0x30101414
register csi_rx_if_stream3_monitor_lb 0x30101418
register csi_rx_if_stream3_timer 0x3010141c
register csi_rx_if_stream3_fcc_cfg 0x30101420
register csi_rx_if_stream3_fcc_ctrl 0x30101424
register csi_rx_if_stream3_fifo_fill_lvl 0x30101428
register csi_rx_if_asf_int_status 0x30101900
register csi_rx_if_asf_int_raw_status 0x30101904
register csi_rx_if_asf_int_mask 0x30101908
register csi_rx_if_asf_int_test 0x3010190c
register csi_rx_if_asf_fatal_nonfatal_select 0x30101910
register csi_rx_if_asf_sram_corr_fault_status 0x30101920
register csi_rx_if_asf_sram_uncorr_fault_status 0x30101924
register csi_rx_if_asf_sram_fault_stats 0x30101928
register csi_rx_if_asf_trans_to_ctrl 0x30101930
register csi_rx_if_asf_trans_to_fault_mask 0x30101934
register csi_rx_if_asf_trans_to_fault_status 0x30101938
register csi_rx_if_asf_protocol_fault_mask 0x30101940
register csi_rx_if_asf_protocol_fault_status 0x30101944
register csi_rx_if_id_prod_ver 0x30101ffc



register csi_rx_if_vp0 0x30102008
register csi_rx_if_vp1 0x3010200c
register csi_rx_if_cntl 0x30102010

I get the following output for my new module:

CSI2RX:

csi_rx_if_REVISION (0x30100000) =  0x6690A200
csi_rx_if_eoi_reg (0x30100010) =  0x00000000
csi_rx_if_intr_vector_reg (0x30100014) =  0x00000000
csi_rx_if_enable_reg_level_0 (0x30100100) =  0x00000000
csi_rx_if_enable_reg_pulse_0 (0x30100104) =  0x00000000
csi_rx_if_enable_clr_reg_level_0 (0x30100300) =  0x00000000
csi_rx_if_enable_clr_reg_pulse_0 (0x30100304) =  0x00000000
csi_rx_if_status_reg_level_0 (0x30100500) =  0x00000000
csi_rx_if_status_reg_pulse_0 (0x30100504) =  0x00000000
csi_rx_if_status_clr_reg_level_0 (0x30100700) =  0x00000000
csi_rx_if_status_clr_reg_pulse_0 (0x30100704) =  0x00000000
csi_rx_if_intr_vector_reg_level (0x30100a80) =  0x00000000
csi_rx_if_intr_vector_reg_pulse (0x30100a84) =  0x00000000
csi_rx_if_device_config (0x30101000) =  0x8C63164C
csi_rx_if_soft_reset (0x30101004) =  0x00000000
csi_rx_if_static_cfg (0x30101008) =  0x43210400
csi_rx_if_error_bypass_cfg (0x30101010) =  0x00000000
csi_rx_if_monitor_irqs (0x30101018) =  0x00000000
csi_rx_if_monitor_irqs_mask_cfg (0x3010101c) =  0x00000000
csi_rx_if_info_irqs (0x30101020) =  0x00000073
csi_rx_if_info_irqs_mask_cfg (0x30101024) =  0x00000000
csi_rx_if_error_irqs (0x30101028) =  0x000F1FF0
csi_rx_if_error_irqs_mask_cfg (0x3010102c) =  0x00000000
csi_rx_if_dphy_lane_control (0x30101040) =  0x0001F01F
csi_rx_if_dphy_status (0x30101048) =  0x00333307
csi_rx_if_dphy_err_status_irq (0x3010104c) =  0x00111100
csi_rx_if_dphy_err_irq_mask_cfg (0x30101050) =  0x00000000
csi_rx_if_integration_debug (0x30101060) =  0x2004A6E0
csi_rx_if_error_debug (0x30101074) =  0x41980002
csi_rx_if_test_generic (0x30101080) =  0x00000000
csi_rx_if_stream0_ctrl (0x30101100) =  0x00000001
csi_rx_if_stream0_status (0x30101104) =  0x80000112
csi_rx_if_stream0_data_cfg (0x30101108) =  0x00000000
csi_rx_if_stream0_cfg (0x3010110c) =  0x00000100
csi_rx_if_stream0_monitor_ctrl (0x30101110) =  0x00000000
csi_rx_if_stream0_monitor_frame (0x30101114) =  0x00000000
csi_rx_if_stream0_monitor_lb (0x30101118) =  0x00000000
csi_rx_if_stream0_timer (0x3010111c) =  0x00000000
csi_rx_if_stream0_fcc_cfg (0x30101120) =  0x00000000
csi_rx_if_stream0_fcc_ctrl (0x30101124) =  0x00000000
csi_rx_if_stream0_fifo_fill_lvl (0x30101128) =  0x00000000
csi_rx_if_stream1_ctrl (0x30101200) =  0x00000000
csi_rx_if_stream1_status (0x30101204) =  0x80000013
csi_rx_if_stream1_data_cfg (0x30101208) =  0x00000000
csi_rx_if_stream1_cfg (0x3010120c) =  0x00000100
csi_rx_if_stream1_monitor_ctrl (0x30101210) =  0x00000000
csi_rx_if_stream1_monitor_frame (0x30101214) =  0x00000000
csi_rx_if_stream1_monitor_lb (0x30101218) =  0x00000000
csi_rx_if_stream1_timer (0x3010121c) =  0x00000000
csi_rx_if_stream1_fcc_cfg (0x30101220) =  0x00000000
csi_rx_if_stream1_fcc_ctrl (0x30101224) =  0x00000000
csi_rx_if_stream1_fifo_fill_lvl (0x30101228) =  0x00000000
csi_rx_if_stream2_ctrl (0x30101300) =  0x00000001
csi_rx_if_stream2_status (0x30101304) =  0x80000112
csi_rx_if_stream2_data_cfg (0x30101308) =  0x00000000
csi_rx_if_stream2_cfg (0x3010130c) =  0x00000100
csi_rx_if_stream2_monitor_ctrl (0x30101310) =  0x00000000
csi_rx_if_stream2_monitor_frame (0x30101314) =  0x00000000
csi_rx_if_stream2_monitor_lb (0x30101318) =  0x00000000
csi_rx_if_stream2_timer (0x3010131c) =  0x00000000
csi_rx_if_stream2_fcc_cfg (0x30101320) =  0x00000000
csi_rx_if_stream2_fcc_ctrl (0x30101324) =  0x00000000
csi_rx_if_stream2_fifo_fill_lvl (0x30101328) =  0x00000000
csi_rx_if_stream3_ctrl (0x30101400) =  0x00000001
csi_rx_if_stream3_status (0x30101404) =  0x80000113
csi_rx_if_stream3_data_cfg (0x30101408) =  0x00000000
csi_rx_if_stream3_cfg (0x3010140c) =  0x00000100
csi_rx_if_stream3_monitor_ctrl (0x30101410) =  0x00000000
csi_rx_if_stream3_monitor_frame (0x30101414) =  0x00000000
csi_rx_if_stream3_monitor_lb (0x30101418) =  0x00000000
csi_rx_if_stream3_timer (0x3010141c) =  0x00000000
csi_rx_if_stream3_fcc_cfg (0x30101420) =  0x00000000
csi_rx_if_stream3_fcc_ctrl (0x30101424) =  0x00000000
csi_rx_if_stream3_fifo_fill_lvl (0x30101428) =  0x00000000
csi_rx_if_asf_int_status (0x30101900) =  0x00000000
csi_rx_if_asf_int_raw_status (0x30101904) =  0x00000000
csi_rx_if_asf_int_mask (0x30101908) =  0x0000007F
csi_rx_if_asf_int_test (0x3010190c) =  0x00000000
csi_rx_if_asf_fatal_nonfatal_select (0x30101910) =  0x0000007F
csi_rx_if_asf_sram_corr_fault_status (0x30101920) =  0x00000000
csi_rx_if_asf_sram_uncorr_fault_status (0x30101924) =  0x00000000
csi_rx_if_asf_sram_fault_stats (0x30101928) =  0x00000000
csi_rx_if_asf_trans_to_ctrl (0x30101930) =  0x00000000
csi_rx_if_asf_trans_to_fault_mask (0x30101934) =  0x00000001
csi_rx_if_asf_trans_to_fault_status (0x30101938) =  0x00000000
csi_rx_if_asf_protocol_fault_mask (0x30101940) =  0x00003FFF
csi_rx_if_asf_protocol_fault_status (0x30101944) =  0x00000000
csi_rx_if_id_prod_ver (0x30101ffc) =  0x50220200
csi_rx_if_vp0 (0x30102008) =  0x00000000
csi_rx_if_vp1 (0x3010200c) =  0x00000000
csi_rx_if_cntl (0x30102010) =  0x00000001

DPHY

DPHY_RX_CMN0_CMN_DIG_TBIT2 (0x30110020) =  0x00000429
DPHY_RX_CMN0_CMN_DIG_TBIT10 (0x30110040) =  0x00800000
DPHY_RX_CMN0_CMN_DIG_TBIT13 (0x3011004c) =  0x00000000
DPHY_RX_CMN0_CMN_DIG_TBIT14 (0x30110050) =  0x00000000
DPHY_RX_PCS_TX_DIG_TBIT0 (0x30110b00) =  0x000001EF
DPHY_RX_PCS_TX_DIG_TBIT1 (0x30110b04) =  0x00000000
DPHY_RX_PCS_TX_DIG_TBIT2 (0x30110b08) =  0xAAAAAAAA
DPHY_RX_PCS_TX_DIG_TBIT3 (0x30110b0c) =  0x000000AA
DPHY_RX_lane (0x30111000) =  0xC0800000

I'm not sure yet how to interpret all this.

Hi Bin Liu,

Any idea when the CSI expert will be available for comment?

Regards,

Bas Vermeulen

Hi Bin Liu,

Has the CSI expert returned? I haven't been able to solve this yet, currently testing with a line frequency of 192 MHz, and still not seeing a CSI signal.

Regards,

Bas Vermeulen

Hi Bas,

Sorry for the late response.

Bas Vermeulen said:

We have clock and data available on the CSI-2 lines, and those look ok, but when using v4l2-ctl -d 3 --stream-mmap we only get a frame rate of 0.2 fps instead of the 30 that we expect.

Can you please share a full log of "media-ctl -p" and "v4l2-ctl --stream-mmap"?

Bas Vermeulen said:

I haven't been able to solve this yet, currently testing with a line frequency of 192 MHz, and still not seeing a CSI signal.

What was the frequency when you were able to stream earlier?

Thank you.

Jianzhong

Hi Jianzhong,

Output of media-ctl -p:

root@4kcam-phyboard-2:~# media-ctl -p
Media controller API version 6.1.69

Media device information
------------------------
driver          j721e-csi2rx
model           TI-CSI2RX
serial
bus info        platform:30102000.ticsi2rx
hw revision     0x1
driver version  6.1.69

Device topology
- entity 1: 30102000.ticsi2rx (7 pads, 7 links, 1 route)
            type V4L2 subdev subtype Unknown flags 0
            device node name /dev/v4l-subdev0
        routes:
                0/0 -> 1/0 [ACTIVE]
        pad0: Sink
                [stream:0 fmt:UYVY8_1X16/640x480 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:lim-range]
                <- "cdns_csi2rx.30101000.csi-bridge":1 [ENABLED,IMMUTABLE]
        pad1: Source
                [stream:0 fmt:UYVY8_1X16/640x480 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:lim-range]
                -> "30102000.ticsi2rx context 0":0 [ENABLED,IMMUTABLE]
        pad2: Source
                -> "30102000.ticsi2rx context 1":0 [ENABLED,IMMUTABLE]
        pad3: Source
                -> "30102000.ticsi2rx context 2":0 [ENABLED,IMMUTABLE]
        pad4: Source
                -> "30102000.ticsi2rx context 3":0 [ENABLED,IMMUTABLE]
        pad5: Source
                -> "30102000.ticsi2rx context 4":0 [ENABLED,IMMUTABLE]
        pad6: Source
                -> "30102000.ticsi2rx context 5":0 [ENABLED,IMMUTABLE]

- entity 9: cdns_csi2rx.30101000.csi-bridge (5 pads, 2 links, 1 route)
            type V4L2 subdev subtype Unknown flags 0
            device node name /dev/v4l-subdev1
        routes:
                0/0 -> 1/0 [ACTIVE]
        pad0: Sink
                [stream:0 fmt:SGRBG12_1X12/3840x2160 field:none colorspace:srgb quantization:full-range]
                <- "ar0822 1-0010":0 [ENABLED,IMMUTABLE]
        pad1: Source
                [stream:0 fmt:SGRBG12_1X12/3840x2160 field:none colorspace:srgb quantization:full-range]
                -> "30102000.ticsi2rx":0 [ENABLED,IMMUTABLE]
        pad2: Source
        pad3: Source
        pad4: Source

- entity 15: ar0822 1-0010 (1 pad, 1 link, 0 route)
             type V4L2 subdev subtype Sensor flags 0
             device node name /dev/v4l-subdev2
        pad0: Source
                [stream:0 fmt:SGRBG12_1X12/3840x2160 field:none colorspace:srgb quantization:full-range]
                -> "cdns_csi2rx.30101000.csi-bridge":0 [ENABLED,IMMUTABLE]

- entity 21: 30102000.ticsi2rx context 0 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video3
        pad0: Sink
                <- "30102000.ticsi2rx":1 [ENABLED,IMMUTABLE]

- entity 27: 30102000.ticsi2rx context 1 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video4
        pad0: Sink
                <- "30102000.ticsi2rx":2 [ENABLED,IMMUTABLE]

- entity 33: 30102000.ticsi2rx context 2 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video5
        pad0: Sink
                <- "30102000.ticsi2rx":3 [ENABLED,IMMUTABLE]

- entity 39: 30102000.ticsi2rx context 3 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video6
        pad0: Sink
                <- "30102000.ticsi2rx":4 [ENABLED,IMMUTABLE]

- entity 45: 30102000.ticsi2rx context 4 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video7
        pad0: Sink
                <- "30102000.ticsi2rx":5 [ENABLED,IMMUTABLE]

- entity 51: 30102000.ticsi2rx context 5 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video8
        pad0: Sink
                <- "30102000.ticsi2rx":6 [ENABLED,IMMUTABLE]

root@4kcam-phyboard-2:~#

v4l2-ctl doesn't give output at the moment, just the driver showing all the registers that are written:

root@4kcam-phyboard-2:~# record-test.ar0822.sh
[  104.190099] ar0822 1-0010: 3010 -> beef
[  104.194440] ar0822 1-0010: 301a -> 0018 updated to 0018
[  104.199913] ar0822 1-0010: 3002 -> 0008
[  104.204024] ar0822 1-0010: 3004 -> 0008
[  104.208068] ar0822 1-0010: 3006 -> 0877
[  104.212156] ar0822 1-0010: 3008 -> 0f07
[  104.216174] ar0822 1-0010: 30a2 -> 0001
[  104.220171] ar0822 1-0010: 30a6 -> 0001
[  104.224458] ar0822 1-0010: 3402 -> 0f00
[  104.228495] ar0822 1-0010: 3404 -> 0870
[  104.232749] ar0822 1-0010: 3040 -> 0000 updated to 0000
[  104.238590] ar0822 1-0010: 3044 -> 0400 updated to 0400
[  104.244208] ar0822 1-0010: 3082 -> 0000 updated to 0000
[  104.250040] ar0822 1-0010: 30ba -> 0024 updated to 0024
[  104.255631] ar0822 1-0010: 31d0 -> 0000 updated to 0000
[  104.261031] ar0822 1-0010: 31ae -> 0204
[  104.265052] ar0822 1-0010: 31ac -> 0c0c
[  104.269060] ar0822 1-0010: 300a -> 0888
[  104.273077] ar0822 1-0010: 300c -> 16e4
[  104.277084] ar0822 1-0010: 3012 -> 009c
[  104.281101] ar0822 1-0010: 3212 -> 0000
[  104.285109] ar0822 1-0010: 3216 -> 0000
[  104.289128] ar0822 1-0010: 3238 -> 0022
[  104.293133] ar0822 1-0010: 32ec -> 72a0
[  104.297349] ar0822 1-0010: 3d02 -> 0033 updated to 0033
[  104.302742] ar0822 1-0010: 302a -> 0003
[  104.306763] ar0822 1-0010: 302c -> 0001
[  104.310768] ar0822 1-0010: 302e -> 0009
[  104.314810] ar0822 1-0010: 3030 -> 0080
[  104.318816] ar0822 1-0010: 3036 -> 0006
[  104.322834] ar0822 1-0010: 3038 -> 0002
[  104.327040] ar0822 1-0010: 31dc -> 1fb0 updated to 1fb0
[  104.332451] ar0822 1-0010: 30b0 -> 0800
[  104.336505] ar0822 1-0010: 31b0 -> 0041
[  104.340529] ar0822 1-0010: 31b2 -> 002f
[  104.344539] ar0822 1-0010: 31b4 -> 3104
[  104.348558] ar0822 1-0010: 31b6 -> 3143
[  104.352566] ar0822 1-0010: 31b8 -> 30c7
[  104.356585] ar0822 1-0010: 31ba -> 0184
[  104.360594] ar0822 1-0010: 31bc -> 0504
[  104.364612] ar0822 1-0010: 31c6 -> 8000
[  104.368621] ar0822 1-0010: 31c8 -> 0acd
[  104.372638] ar0822 1-0010: 5930 -> 007e
[  104.376857] ar0822 1-0010: 31de -> 0000 updated to 0000
[  104.382463] ar0822 1-0010: 31f8 -> 0008 updated to 0008
[  104.388058] ar0822 1-0010: 3342 -> 122c updated to 122c
[  104.393656] ar0822 1-0010: 3344 -> 0011 updated to 0011
[  104.399255] ar0822 1-0010: 3346 -> 122c updated to 122c
[  104.404855] ar0822 1-0010: 3348 -> 0111 updated to 0011
[  104.410449] ar0822 1-0010: 334a -> 122c updated to 122c
[  104.416048] ar0822 1-0010: 334c -> 0211 updated to 0011
[  104.421647] ar0822 1-0010: 334e -> 122c updated to 122c
[  104.427242] ar0822 1-0010: 3350 -> 0011 updated to 0011
[  104.432645] ar0822 1-0010: 5900 -> 0000
[  104.436665] ar0822 1-0010: 3002 -> 0008
[  104.440673] ar0822 1-0010: 3004 -> 0008
[  104.444692] ar0822 1-0010: 3006 -> 0877
[  104.448700] ar0822 1-0010: 3008 -> 0f07
[  104.452711] ar0822 1-0010: 30a2 -> 0001
[  104.456716] ar0822 1-0010: 30a6 -> 0001
[  104.460736] ar0822 1-0010: 3402 -> 0f00
[  104.464744] ar0822 1-0010: 3404 -> 0870
[  104.468962] ar0822 1-0010: 3040 -> 0000 updated to 0000
[  104.474552] ar0822 1-0010: 3044 -> 0400 updated to 0400
[  104.480152] ar0822 1-0010: 3082 -> 0000 updated to 0000
[  104.485750] ar0822 1-0010: 30ba -> 0024 updated to 0024
[  104.491351] ar0822 1-0010: 31d0 -> 0000 updated to 0000
[  104.496747] ar0822 1-0010: 31ae -> 0204
[  104.500760] ar0822 1-0010: 31ac -> 0c0c
[  104.504769] ar0822 1-0010: 300a -> 0888
[  104.508787] ar0822 1-0010: 300c -> 16e4
[  104.512796] ar0822 1-0010: 3012 -> 009c
[  104.516814] ar0822 1-0010: 3212 -> 0000
[  104.520821] ar0822 1-0010: 3216 -> 0000
[  104.524840] ar0822 1-0010: 3238 -> 0022
[  104.528847] ar0822 1-0010: 32ec -> 72a0
[  104.533060] ar0822 1-0010: 3d02 -> 0033 updated to 0033
[  104.538462] ar0822 1-0010: 3070 -> 0000
[  104.542678] ar0822 1-0010: 301a -> 0018 updated to 001c
[  104.548273] ar0822 1-0010: GPI_STATUS = 0000
[  104.552756] ar0822 1-0010: FRAME_STATUS = 0008
[  104.557420] ar0822 1-0010: RESET_REGISTER = 001c
[  104.562251] ar0822 1-0010: LOCK_REGISTER = beef

I have a different sensor (ar0521) running in the same configuration, with a line frequency of 184 MHz. The DPHY registers look almost the same, same as the csi2rx registers. The AR0521 streams correctly, the AR0822 doesn't stream at all (although the clocks and all lanes show data being sent).

Regards,

Bas Vermeulen

My current MIPI timing is configured as follows:

; [PLL PARAMETERS]
; Target Pixel Frequency: 164.300 MHz
; Input Clock Frequency: 27 MHz
;
; Actual Pixel Clock: 128 MHz
;
; pre_pll_clk_div (N+1 Value) = 9
; pll_multiplier (2M Value) = 128
; Fvco = 384 MHz
; vt_sys_clk_div (P1) = 1
; vt_pix_clk_div (P2) = 3
; op_sys_clk_div (P3) = 2
; op_word_clk_div (P4)= 6
; Pixel Clock: 128 MHz
; Serial Bit Clock: 192 MHz
; Word Clock: 32MHz
; Sensor Logic Data Rate: 512 MHz
; Serial Data Rate: 256 Mpix/s
; Serial Rate: 384 Mbit/s
; Logic Throughput Factor: 0.164

T_HS_PREPARE = 3 (clk cycles I believe)
T_HS_TRAIL = 4 clk cycles
T_CLK_TRAIL = 4 op clk cycles
T_CLK_PREPARE = 3 clk cycles?
T_HS_EXIT = 5 op_pix_clk periods
T_HS_ZERO = 3 op_pix_clk_periods
T_BGAP_LSB = 3
T_CLK_PRE = 3 op_pix_clk periods
T_CLK_POST = 7 op_pix_clk periods
T_BGAP_MSB = 0 -> T_BGAP = 3
T_LPX = 3 op_pix_clk periods
T_WAKEUP = 8192 * 4 * op_pix_clk
CONT_TX_CLK = 0
HEAVE_LP_LOAD = 0
T_CLK_ZERO = 10 op_pix_clk periods
T_INIT = 1024 * 4 * op_pix_clk

When I set the mipi timings to the default for the sensor, I get some data coming through. I've also tried setting the MIPI timing the same as the AR0521 sensor (which is working), but that doesn't make a difference.

		AR0521		AR0822
T_HS_PREPARE	2		8
T_HS_TRAIL	9		13
T_CLK_TRAIL	10		14
T_CLK_PREPARE	2		8
T_HS_EXIT	13		18
T_HS_ZERO	17		17
T_BGAP		10		13
T_CLK_PRE	1		3
T_CLK_POST	13 (001101b)	16
T_LPX		7		10
T_WAKEUP	15		21
T_CLK_ZERO	34		50
T_INIT		12		17

With the default timings, I get 0.02 fps, I'm not sure if I get a complete picture or not. I'm guessing the MIPI timing isn't correct, I'm just not sure how to improve it yet. The sensor is sending at 10 fps.

Regards,

Bas Vermeulen

Hello,

Bas Vermeulen said:

With the default timings, I get 0.02 fps, I'm not sure if I get a complete picture or not.

Are you able to view the captured image using a tool such as pixelviewer?

Regards,

Jianzhong

If I use v4l2-ctl -d 3 --stream-mmap --stream-to out.raw --stream-count 1 I get the following output:

-rw-r--r-- 1 vermes domain users 614400 jul 10 08:41 out.raw

The file only contains a couple of lines, and those lines don't look valid.

k3-am62-phyboard-lyra-ar0822-mipi.dtso

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2022 PHYTEC Messtechnik GmbH
 * Author: Wadim Egorov <w.egorov@phytec.de>
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>

&{/} {
        clk_cam: clk-cam {
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <27000000>;
        };
};

&main_i2c1 {
        pinctrl-names = "default";
        pinctrl-0 = <&main_i2c1_pins_default>;
        clock-frequency = <400000>;
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";

        ar0822_mipi: ar0822-mipi@10 {
                compatible = "onnn,ar0822";
                reg = <0x10>;

                clocks = <&clk_cam>;
                clock-names = "extclk";

                port {
                        ar0822_mipi_ep: endpoint {
                                remote-endpoint = <&csi2rx0_in_sensor>;
                                clock-lanes = <0>;
                                data-lanes = <1 2 3 4>;
                                clock-noncontinuous = <1>;
                                bus-type = <4>; /* MIPI_CSI2_DPHY */
                                link-frequencies = /bits/ 64 <192000000>;
                        };
                };
        };
};

&csi0_port0 {
        status = "okay";

        csi2rx0_in_sensor: endpoint {
                remote-endpoint = <&ar0822_mipi_ep>;
                bus-type = <4>; /* CSI2 DPHY. */
                clock-lanes = <0>;
                data-lanes = <1 2 3 4>;
        };
};

&dphy0 {
        status = "okay";
};

&ti_csi2rx0 {
        status = "okay";
};

HI Suren,

What is the best way to swap the polarity of the lane data pins?

Regards,

Bas Vermeulen

Please refer to this thread: e2e.ti.com/.../sk-am62a-lp-csi-2-d-phy-clock-and-data-lane-polarity-inversion-swap

Understood. I've modified the polarity for all of them (bits 8 to 0 = 1), and then the DPHY_LANE register no longer sees the clock, so the clock was correct.

What is the best way to debug something like this? We've verified the signal integrity of all the lanes, and those all look ok, including the low speed start and stop sections. When I enable a test pattern with a solid color, I see the pixels being the value I expect (255, 255, 251).

I just don't see any frames coming in on the am62a.

When running my current driver (432 MHz line frequency, pixel clock of 144 MHz) the sensor sends 30 fps (verified with an osciloscope on the 4 lanes), and the DPHY has the following register values:

DPHY_RX_CMN0_CMN_DIG_TBIT2 (0x30110020) =  0x00000429
DPHY_RX_CMN0_CMN_DIG_TBIT10 (0x30110040) =  0x00800000
DPHY_RX_CMN0_CMN_DIG_TBIT13 (0x3011004c) =  0x00000000
DPHY_RX_CMN0_CMN_DIG_TBIT14 (0x30110050) =  0x00000000
DPHY_RX_PCS_TX_DIG_TBIT0 (0x30110b00) =  0x000001CE
DPHY_RX_PCS_TX_DIG_TBIT1 (0x30110b04) =  0x00000000
DPHY_RX_PCS_TX_DIG_TBIT2 (0x30110b08) =  0xAAAAAAAA
DPHY_RX_PCS_TX_DIG_TBIT3 (0x30110b0c) =  0x000000AA
DPHY_ISO_DL_CTRL_L (0x30110c10) =  0x0000002D
DPHY_ISO_DL_CTRL_L0 (0x30110c14) =  0x00000005
DPHY_ISO_DL_CTRL_L1 (0x30110c20) =  0x0000000D
DPHY_ISO_DL_CTRL_L2 (0x30110c30) =  0x0000000D
DPHY_ISO_DL_CTRL_L3 (0x30110c3c) =  0x00000005
DPHY_RX_lane (0x30111000) =  0xC0800000

I believe bit 0 being set on DPHY_ISO_DL_CTRL_L* means that the lane is ready. Does this mean that the D-PHY detects data on those lanes?

Why am I seeing different values for DPHY_ISO_DL_CTRL_L0/L3 and DPHY_ISO_DL_CTRL_L1/L2?

What does bit 3 mean in those registers?

Are bits 0-3 from those registers defined anywhere?

The frame start sequence

Frame start with first data

Hello Bas,

There are a couple of things to try:

1. You can add a few debug prints in your sensor driver's streaming function and see if the function is called and finished.

2. Add a debug print to see if DMA is requested by the CSI-2 Rx driver: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c?h=ti-linux-6.1.y#n713 

Also, can you share the command you used to capture?

Regards,

Jianzhong

Hello Jianzhong,

1. You can add a few debug prints in your sensor driver's streaming function and see if the function is called and finished.

I have my driver printing out every register being written to the sensor. The streaming function is being called and finishes (and I see the sensor start streaming, I see the clock starting on the CLKN/CLKP lines, and I see data going on DxN/DxP).

2. Add a debug print to see if DMA is requested by the CSI-2 Rx driver: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c?h=ti-linux-6.1.y#n713 

I have a different sensor where everything works as expected (AR0521 instead of AR0822), so I would expect that to still work. But I'll add a debug print to that line to make sure.

I've since added the print here, and I see 4 dma transfers being started when streaming starts

[   71.727415] j721e-csi2rx 30102000.ticsi2rx: calling ti_csi2rx_start_dma(0000000049d94dfe, 000000006bfb314b)
[   71.737213] j721e-csi2rx 30102000.ticsi2rx: calling ti_csi2rx_start_dma(0000000049d94dfe, 000000001295ad20)
[   71.746951] j721e-csi2rx 30102000.ticsi2rx: calling ti_csi2rx_start_dma(0000000049d94dfe, 000000004e745a9c)
[   71.756682] j721e-csi2rx 30102000.ticsi2rx: calling ti_csi2rx_start_dma(0000000049d94dfe, 00000000324344f9)

Also, can you share the command you used to capture?

I am using v4l2-ctl -d 3 --stream-mmap to capture, mostly to easily see the frame rate. Once that is working I'll integrate things into my streaming script.

Could you tell me what the lower 4 bits are in DPHY_ISO_DL_CTRL_L0/L1/L2/L3 (0x30110c14)? I see the value 5 for lane 0 and 3, and the value D for lanes 1 and 2, and I'm not sure what that means. I know bit 0 is the LANE_READY bit, as that's in the driver.

I would also like to know the meaning of the first 6 bits in DPHY_ISO_DL_CTRL_L (0x30110c10).

Regards,

Bas Vermeulen

Bas Vermeulen said:

I've since added the print here, and I see 4 dma transfers being started when streaming starts

Ok. So the CSI-2 RX driver started DMA but the transfer never completed. Can you add a debug print to ti_csi2rx_dma_callback() just to confirm this callback isn't executed?

The fact that DMA wasn't completed probably indicates that the DPHY wasn't able to process the incoming data. A few things to check:

1. Link frequency. From the device tree you provided, the link frequency is set to 192MHz. The corresponding pixel rate is: link_freq * 2 * number_of_lanes / bits_per_pixel = 192000000*2*4/12 = 128000000. This pixel rate is below your resolution and frame rate: 3840*2160*30 = 248832000, not even counting the blanking pixels. This means 192MHz link frequency can't support 3840x2160@30fps. You'll need to use a higher frequency. Please check the sensor data sheet.

2. What's the virtual channel id and data type used to send data from the sensor?

3. What are the main differences between AR0521 and AR0822? Are you reusing the AR0521 driver for AR0822?

Bas Vermeulen said:

Could you tell me what the lower 4 bits are in DPHY_ISO_DL_CTRL_L0/L1/L2/L3 (0x30110c14)?

I can't find these registers from the AM62A TRM. Can you point to me where you got these registers?

Regards,

Jianzhong

Jianzhong Xu said:

Ok. So the CSI-2 RX driver started DMA but the transfer never completed. Can you add a debug print to ti_csi2rx_dma_callback() just to confirm this callback isn't executed?

I'll give that a go and let you know.

Jianzhong Xu said:

The fact that DMA wasn't completed probably indicates that the DPHY wasn't able to process the incoming data. A few things to check:

1. Link frequency. From the device tree you provided, the link frequency is set to 192MHz. The corresponding pixel rate is: link_freq * 2 * number_of_lanes / bits_per_pixel = 192000000*2*4/12 = 128000000. This pixel rate is below your resolution and frame rate: 3840*2160*30 = 248832000, not even counting the blanking pixels. This means 192MHz link frequency can't support 3840x2160@30fps. You'll need to use a higher frequency. Please check the sensor data sheet.

I get around 5 fps with the 192 MHz link frequency on the onsemi baseboard. I currently have my driver set up to use 492.5 MHz and 985 Mbps bandwidth, and that gets 30 fps on the onsemi baseboard. So the link frequency is covered. The only reason I switched to 192 MHz was because I wanted to get as close to the working link frequency of the AR0512 as possible.

Jianzhong Xu said:

2. What's the virtual channel id and data type used to send data from the sensor?

I'm not sure, but that's not something I've changed. How can I check? The sensor documentation doesn't mention this either.

Jianzhong Xu said:

3. What are the main differences between AR0521 and AR0822? Are you reusing the AR0521 driver for AR0822?

I've re-used the bones of the AR0521 driver to write the AR0822 driver. But it's currently boiled down to resetting the sensor on power up, and setting PLL, MIPI timings and stream start when we start streaming. Once I have a working setup, I will have to do some rewriting to get everything working more flexibly. Currently I only support one resolution/link frequency and use a fixed 4 lanes.

Jianzhong Xu said:

Bas Vermeulen said:

Could you tell me what the lower 4 bits are in DPHY_ISO_DL_CTRL_L0/L1/L2/L3 (0x30110c14)?

I can't find these registers from the AM62A TRM. Can you point to me where you got these registers?

I got those registers from the driver: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/phy/cadence/cdns-dphy-rx.c?h=ti-linux-6.1.y#n42

That defines one bit (bit 0) in that register, but I see the first 4 bits being used for DPHY_ISO_DL_CTRL_Lx, and the first 6 bits for DPHY_ISO_DL_CTRL_L (I think that's the clock lane).

Is there a way to see what the DPHY is doing? I was hoping that the above registers might give some insight.

Regards,

Bas Vermeulen

Jianzhong Xu said:

Can you check the error status registers in Table 14-24592. VBUS2APB_WRAP_VBUSP_APB_CSI2RX of the TRM from https://www.ti.com/product/AM62A7?

dphy_status (0x30101048) =  0x00222206
dphy_err_status_irq (0x3010104c) =  0x00000000
error_debug (0x30101074) =  0x00000000

I'm looking into the virtual channel and data ID, but those are not used for the onsemi sensors (at least in the two drivers that I've seen (ar0521 and ar0144).

Jianzhong Xu said:

About virtual channel id and data type, please refer to IMX219 driver: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/media/i2c/imx219.c?h=ti-linux-6.1.y#n871. Specifically, please look at:

	fd->entry[fd->num_entries].bus.csi2.vc = 0;
	if (imx219->fmt.code == MEDIA_BUS_FMT_SRGGB8_1X8)
		fd->entry[fd->num_entries].bus.csi2.dt = 0x2a; /* SRGGB8 */
	else if (imx219->fmt.code == MEDIA_BUS_FMT_SRGGB10_1X10)
		fd->entry[fd->num_entries].bus.csi2.dt = 0x2b; /* SRGGB10 */

We looked at the MIPI CSI2 signal, and that shows me we are sending DT 0x2C. Looking at the signal of the AR0521 (where the driver only supports 8 bit), the DT is 0x2A. The virtual channel is 0 on both.

I'm currently compiling a modified driver that sets the DT to 0x2C. My guess is that 0x2A is the default value here?

Right. I've looked at the registers for the SHIM, and for the ar0822 I see the data type being requested as 0x1E (YUV422 8-bit) (in 0x30102020 bits 0-5).

What is the right way to start streaming SGRBG12_1X12/3840x2160 with v4l2-ctl --stream-mmap?

I currently do the following:

media-ctl -V '"ar0822 1-0010":0 [fmt:SGRBG12_1X12/3840x2160 field:none]'
v4l2-ctl -d 3 --stream-mmap

if I do that, the DATTYP_CFG in 0x30102020 gets set to 0x1E, instead of the 0x2C that it should be configured according to j721e-csi2rx.c.

What do I need to configure before calling v4l2-ctl -d 3 --stream-mmap to make this work correctly?

I can stream correctly if I run this:

media-ctl -V '"ar0822 1-0010":0 [fmt:SGRBG12_1X12/3840x2160 field:none]'
gst-launch-1.0 v4l2src device=/dev/video3 io-mode=dmabuf ! video/x-bayer, width=3840, height=2160, framerate=30/1, format=grbg12 ! fakesink

Once that has ran, v4l2-ctl -d 3 --stream-mmap works correctly (because DATTYP_CFG is set to 0x2C instead of 0x1E).

I would like to be able to run v4l2-ctl --stream-mmap without having to run gst-launch.

PS: I'll be on vacation for the next three weeks. I'll get back to this topic after that.

Can you please provide "media-ctl -p" before and after you run this command?

media-ctl -V '"ar0822 1-0010":0 [fmt:SGRBG12_1X12/3840x2160 field:none]'

Bas Vermeulen said:

What do I need to configure before calling v4l2-ctl -d 3 --stream-mmap to make this work correctly?

Please try also to set the format for ticsi2rx:

media-ctl -V '"30102000.ticsi2rx":0 [fmt:SGRBG12_1X12/3840x2160 field:none]'

If I run media-ctl -V '"ar0822 1-0010":0 [fmt:SGRBG12_1X12/3840x2160 field:none]',  this changes the source and sink of entity 15 (ar0822) and entity 9 (cdns_csi2rx.30101000.csi-bridge), but doesn't change the format of entity 1 (30102000.ticsi2rx). I believe that's my problem.

Output of media-ctl -p at boot:

root@4kcam-phyboard-2:~# media-ctl -p
Media controller API version 6.1.69

Media device information
------------------------
driver          j721e-csi2rx
model           TI-CSI2RX
serial
bus info        platform:30102000.ticsi2rx
hw revision     0x1
driver version  6.1.69

Device topology
- entity 1: 30102000.ticsi2rx (7 pads, 7 links, 1 route)
            type V4L2 subdev subtype Unknown flags 0
            device node name /dev/v4l-subdev0
        routes:
                0/0 -> 1/0 [ACTIVE]
        pad0: Sink
                [stream:0 fmt:UYVY8_1X16/640x480 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:lim-range]
                <- "cdns_csi2rx.30101000.csi-bridge":1 [ENABLED,IMMUTABLE]
        pad1: Source
                [stream:0 fmt:UYVY8_1X16/640x480 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:lim-range]
                -> "30102000.ticsi2rx context 0":0 [ENABLED,IMMUTABLE]
        pad2: Source
                -> "30102000.ticsi2rx context 1":0 [ENABLED,IMMUTABLE]
        pad3: Source
                -> "30102000.ticsi2rx context 2":0 [ENABLED,IMMUTABLE]
        pad4: Source
                -> "30102000.ticsi2rx context 3":0 [ENABLED,IMMUTABLE]
        pad5: Source
                -> "30102000.ticsi2rx context 4":0 [ENABLED,IMMUTABLE]
        pad6: Source
                -> "30102000.ticsi2rx context 5":0 [ENABLED,IMMUTABLE]

- entity 9: cdns_csi2rx.30101000.csi-bridge (5 pads, 2 links, 1 route)
            type V4L2 subdev subtype Unknown flags 0
            device node name /dev/v4l-subdev1
        routes:
                0/0 -> 1/0 [ACTIVE]
        pad0: Sink
                [stream:0 fmt:UYVY8_1X16/640x480 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:lim-range]
                <- "ar0822 1-0010":0 [ENABLED,IMMUTABLE]
        pad1: Source
                [stream:0 fmt:UYVY8_1X16/640x480 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:lim-range]
                -> "30102000.ticsi2rx":0 [ENABLED,IMMUTABLE]
        pad2: Source
        pad3: Source
        pad4: Source

- entity 15: ar0822 1-0010 (1 pad, 1 link, 0 route)
             type V4L2 subdev subtype Sensor flags 0
             device node name /dev/v4l-subdev2
        pad0: Source
                [stream:0 fmt:SGRBG12_1X12/3840x2160 field:none colorspace:srgb quantization:full-range]
                -> "cdns_csi2rx.30101000.csi-bridge":0 [ENABLED,IMMUTABLE]

- entity 21: 30102000.ticsi2rx context 0 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video3
        pad0: Sink
                <- "30102000.ticsi2rx":1 [ENABLED,IMMUTABLE]

- entity 27: 30102000.ticsi2rx context 1 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video4
        pad0: Sink
                <- "30102000.ticsi2rx":2 [ENABLED,IMMUTABLE]

- entity 33: 30102000.ticsi2rx context 2 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video5
        pad0: Sink
                <- "30102000.ticsi2rx":3 [ENABLED,IMMUTABLE]

- entity 39: 30102000.ticsi2rx context 3 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video6
        pad0: Sink
                <- "30102000.ticsi2rx":4 [ENABLED,IMMUTABLE]

- entity 45: 30102000.ticsi2rx context 4 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video7
        pad0: Sink
                <- "30102000.ticsi2rx":5 [ENABLED,IMMUTABLE]

- entity 51: 30102000.ticsi2rx context 5 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video8
        pad0: Sink
                <- "30102000.ticsi2rx":6 [ENABLED,IMMUTABLE]

root@4kcam-phyboard-2:~#

Output of media-ctl -p after running media-ctl -V '"ar0822 1-0010":0 [fmt:SGRBG12_1X12/3840x2160 field:none]':

root@4kcam-phyboard-2:~# media-ctl -V '"ar0822 1-0010":0 [fmt:SGRBG12_1X12/3840x2160 field:none]'
root@4kcam-phyboard-2:~# media-ctl -p
Media controller API version 6.1.69

Media device information
------------------------
driver          j721e-csi2rx
model           TI-CSI2RX
serial
bus info        platform:30102000.ticsi2rx
hw revision     0x1
driver version  6.1.69

Device topology
- entity 1: 30102000.ticsi2rx (7 pads, 7 links, 1 route)
            type V4L2 subdev subtype Unknown flags 0
            device node name /dev/v4l-subdev0
        routes:
                0/0 -> 1/0 [ACTIVE]
        pad0: Sink
                [stream:0 fmt:UYVY8_1X16/640x480 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:lim-range]
                <- "cdns_csi2rx.30101000.csi-bridge":1 [ENABLED,IMMUTABLE]
        pad1: Source
                [stream:0 fmt:UYVY8_1X16/640x480 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:lim-range]
                -> "30102000.ticsi2rx context 0":0 [ENABLED,IMMUTABLE]
        pad2: Source
                -> "30102000.ticsi2rx context 1":0 [ENABLED,IMMUTABLE]
        pad3: Source
                -> "30102000.ticsi2rx context 2":0 [ENABLED,IMMUTABLE]
        pad4: Source
                -> "30102000.ticsi2rx context 3":0 [ENABLED,IMMUTABLE]
        pad5: Source
                -> "30102000.ticsi2rx context 4":0 [ENABLED,IMMUTABLE]
        pad6: Source
                -> "30102000.ticsi2rx context 5":0 [ENABLED,IMMUTABLE]

- entity 9: cdns_csi2rx.30101000.csi-bridge (5 pads, 2 links, 1 route)
            type V4L2 subdev subtype Unknown flags 0
            device node name /dev/v4l-subdev1
        routes:
                0/0 -> 1/0 [ACTIVE]
        pad0: Sink
                [stream:0 fmt:SGRBG12_1X12/3840x2160 field:none colorspace:srgb quantization:full-range]
                <- "ar0822 1-0010":0 [ENABLED,IMMUTABLE]
        pad1: Source
                [stream:0 fmt:SGRBG12_1X12/3840x2160 field:none colorspace:srgb quantization:full-range]
                -> "30102000.ticsi2rx":0 [ENABLED,IMMUTABLE]
        pad2: Source
        pad3: Source
        pad4: Source

- entity 15: ar0822 1-0010 (1 pad, 1 link, 0 route)
             type V4L2 subdev subtype Sensor flags 0
             device node name /dev/v4l-subdev2
        pad0: Source
                [stream:0 fmt:SGRBG12_1X12/3840x2160 field:none colorspace:srgb quantization:full-range]
                -> "cdns_csi2rx.30101000.csi-bridge":0 [ENABLED,IMMUTABLE]

- entity 21: 30102000.ticsi2rx context 0 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video3
        pad0: Sink
                <- "30102000.ticsi2rx":1 [ENABLED,IMMUTABLE]

- entity 27: 30102000.ticsi2rx context 1 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video4
        pad0: Sink
                <- "30102000.ticsi2rx":2 [ENABLED,IMMUTABLE]

- entity 33: 30102000.ticsi2rx context 2 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video5
        pad0: Sink
                <- "30102000.ticsi2rx":3 [ENABLED,IMMUTABLE]

- entity 39: 30102000.ticsi2rx context 3 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video6
        pad0: Sink
                <- "30102000.ticsi2rx":4 [ENABLED,IMMUTABLE]

- entity 45: 30102000.ticsi2rx context 4 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video7
        pad0: Sink
                <- "30102000.ticsi2rx":5 [ENABLED,IMMUTABLE]

- entity 51: 30102000.ticsi2rx context 5 (1 pad, 1 link, 0 route)
             type Node subtype V4L flags 0
             device node name /dev/video8
        pad0: Sink
                <- "30102000.ticsi2rx":6 [ENABLED,IMMUTABLE]

root@4kcam-phyboard-2:~#

I believe we have the following chain:

ar0822 pad 0 (Source) -> cdns_csi2rx.30101000.csi-bridge pad 0 (Sink) -> cdns_csi2rx.30101000.csi-bridge pad 1 (Source) -> 30102000.ticsi2rx pad 0 (Sink)

Is there a way to automatically propagate the format from cdns_csi2rx.30101000.csi-bridge pad 1 (which is set correctly) to the connected pad 0 from 30102000.ticsi2rx? If you can point me in the right direction I can probably make the changes myself.

Hi Jianzhong Xu,

If I configure 30102000.ticsi2rx pad 0 with that format, v4l2-ctl -d 3 --stream-mmap still doesn't work the way it is supposed to.

If I run gst-launch-1.0 v4l2src device=/dev/video3 io-mode=dmabuf ! video/x-bayer, width=3840, height=2160, framerate=30/1, format=grbg12 ! fakesink, this will make v4l2-ctl -d 3 --stream-mmap work as expected. There is no visible difference in the media-ctl -p output (I saved before and after to a file and ran diff).

Do you have any idea what gets changed by using gst-launch and the v4l2src plugin?

Can you share the full log of both gst-launch and v4l2-ctl --stream-mmap?