[FAQ] AM62x, AM64x, AM243x, Custom board hardware design – How to handle Used / Unused Pins / Peripherals ? (e.g. GPIOs, SERDES, USB, CSI, MMC (eMMC, SD-card), CSI, OLDI, DSI, CAP_VDDSx, .....)

Hi Board designers, 

Handling of the Used IOs or Peripherals and Unused IOs or Peripherals depends on the family of processors. 

The Following documents could be references

Device specific data sheet 

Device specific Errata 

Hardware Design Guide for family of devices 

Schematic Design and Review Checklist for family of devices 

These documents are available on the device specific product folder on TI.com. The product folder has many ore documents and tools that makes designing customer board simpler.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1455706/faq-am625-am623-am625sip-am620-q1-am625-q1-design-recommendations-custom-board-hardware-design---custom-board-schematics-self-review

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1456132/faq-am62a3-am62a7-am62a7-q1-am62a3-am62a3-q1-am62d-q1-design-recommendations-custom-board-hardware-design---custom-board-schematics-self-review

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1456130/faq-am62p-am62p-q1-design-recommendations-custom-board-hardware-design---custom-board-schematics-self-review

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1456123/faq-am6442-am6441-am6422-am6421-am6412-am6411-am243x-design-recommendations-custom-board-hardware-design---custom-board-schematics-self-review

if you have any questions or not able to find the right collateral, reach out to TI support over E2E.

The assigned TI expert can point you to the required collaterals and also provide additional guidance.

Additional references

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1337814/faq-am625-am623-am62a-am62p-design-recommendations-commonly-observed-errors-during-custom-board-hardware-design-soc-unused-peripherals-and-ios

Regards,

Sreenivasa

Additional inputs for Decoupling caps on CAP_VDDSx

Customer's asking what will happen if the decoupling caps on the CAP* nets below are not installed correctly? Will the device's behavior be well defined in this case (i.e. fail to boot etc) or would it be more sporadic based on operating mode? They are preparing manufacturing test definition and wondering about scenarios such as

DNP incorrectly.  
One or more of the caps are damaged due to handling and result in:
open
short
Is there any defined behavior for wrong values  of the capacitors that can be captured in testing?
Refer below FAQ

e2e.ti.com/.../4747088

Regards,

Sreenivasa

Additional inputs for handling RSVD pins 

If these signals are short-circuited, what will happen? I am thinking of cases such as a short circuit on each terminal in terms of functional safety. If there is no error in the functional test, there is no issue with the shorted RSVD pins or we don't have any shorts?

 Most of the reserved pins are analog test pins which are not driven during normal operation. These pins should always be in normal operation mode in a customer’s system since we do not allow customers to access the test functions associated with the analog test pins. Therefore, we do not anticipate an issue if they were accidently shorted to an adjacent ball.
This comment does not give customers permission to connect any signal traces to these pins.
There could be an issue if these pins were shorted to a power supply of higher potential. For example, a 1.8V power rail may be connected to a 3.3V power source via the pin’s ESD clamp circuit if one of the pins were shorted to 3.3V. In this case, the internal clamp diode would be forward biased and the higher potential would flow through the clamp diode and raise the potential applied to the 1.8v power rail. This could potentially create multiple EOS issues for the device.

Regards,

Sreenivasa