AM6421: GPMC 32-bit A/D non-multiplexed interface

Hello Huynh,

I am looking at your queries and you may expect reply in one or two days .

Regards,

Anil.

Thank you and while waiting for the confirmation and Sysconfig update, I think the pin assignments for BE2 and BE3 are :

iGPMC1.BE2n.$assign     = "PRG1_PRU0_GPO16";

iGPMC1.BE3n.$assign     = "PRG1_PRU1_GPO17";

Regards,

Huynh

Hello Huynh,

As per TRM, the 32bit NAND device is not supported.

SOC can support either 8 bit or 16 bit mode only for NAND devices.

Regards,

Anil.

No. We are using SRAM/FPGA interface and supported herein .

Please see the following forum link and see the answer by James, TI technical support:

e2e.ti.com/.../4479732

Hello Huynh,

Sorry for confusing. I thought you were going with 32bit NAND devices.

So, if you are going with PSRAM/PFGA, then 32bit is fine, but it works in Multiplexed mode only and will not work in Non-Multiplexed mode.

Please look at the image below.

You can check the link below for more details about how much memory size can connect to AM64X devices.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1349234/faq-am24x-am64x-am62x-what-are-the-maximum-sizes-of-nand-or-nor-or-psram-memories-that-can-be-connected-to-gpmc-for-the-am24x-am64x-am62x

Coming to your question, to read the first LSB 16bit  or MSB 16 bit value or 32bit value, GPMC need to control these BE0 to BE3 bits.

For the first LSB 16 bit read, GPMC control BE bits as below .

BE 0:3 → BE 0:1 → 11

And, the next MSB 16 bit read , GPMC control BE bits as below .

BE 0:3 → BE 3:2 → 11

So, it is not possible to control these pins from system cfg. Since, currently in MCU_SDK we support, 8bit and 16Bit NAND and NOR/PSRAM respectively.

If you want to go with the 32bit support, it is not supported by system cfg.

So, you need to do 32bit configuration manually.

For example, you can take  PSRAM example from MCU+SDK , which supports 16bit and BE0 and BE1 pins are enabled from the system cfg.

For 32 bit support, you need to set pin mux settings for remain address and data lines and BE lines as similar how the application is done from the generated code.

Regards,

Anil.

Hi,

I don't think that is the correct answer. The sysconfig allows me to configure for 32-bit non-multiplexed A/D mode, except the BE3 and BE2 are greyed out.

The resulting header and C files were given correct information and only need to edit for those 2 bits.

Please read the similar question posted here and answered by James (JJD - TI-Guru) : 

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1188914/am6411-processor-peripherals-gpmc-32-bit-a-d-non-multiplexed-interface/4479732?tisearch=e2e-sitesearch&keymatch=Asynchronous%25252520SRAM%25252520like%25252520memories%25252520GPMC%25252520interface#4479732

Thanks,

Huynh