TDA4VM-Q1: EMMC RESET Control

Hi, TI team,

Could you pay attention to this? Thank you.

Best Regards

Juanli Zhang

Hi Juanli,

Juanli Zhang said:

The reset of  EMMC comes out from T6 of TDA4VM

Can you further explain what you mean by this?

Juanli Zhang said:

The below is our test waveform. After power-on, RST will be briefly pulled high (lasting about 140~200us) and then pulled low. After being low for about 9.5ms, it will be pulled high again, and will continue to be pulled high for 360~380ms. It will be briefly pulled low (lasting 140us) and then pulled high again (always high).

Does this happen on every power-on after reset? 

Is it consistently pulling low and high again in these time frames?

Juanli Zhang said:

Q2: Can we control this pin?

Are you using a TI EVM or modified version of your own EVM? 

Best Regards,

Matt

Hi Matt，

Matt Park said:

Juanli Zhang said:

The reset of  EMMC comes out from T6 of TDA4VM

Can you further explain what you mean by this?

The eMMC RESET as below picture:

Matt Park said:

Does this happen on every power-on after reset? 

Yes, this happen on every power-on after reset.

Matt Park said:

Is it consistently pulling low and high again in these time frames?

This pulling low and high again only happen once at power-on.

I have no EVM board.

Best Regards

Juanli Zhang

Hi Juanli,

Juanli Zhang said:

I have no EVM board.

Are you using your own evaluation board with TDA4VM then?

What is your concern for RST on eMMC pulling low temporarily, then back to high?

Best Regards,

Matt

Hi Matt,

Yes, I use our own board for testing.

 I am confused，the eMMC has been powered on and the reset has been pulled high,why it has to be pulled low and then high again in 400ms. I don't know the reason for this.

Best Regards

Juanli Zhang

Hi Juanli,

It is hard to tell for sure the reason for this currently as you are using your own board.

Can you share the schematic?

Do you have multiple boards to replicate and try this on?

What is your use case for the eMMC?

Best Regards,

Matt

2678.EMMC.pdf

Hi Matt,

The schematic as attached. Thank you

Best Regards

Juanli Zhang

In the attached schematic, you only provided the eMMC connection, but not the source of the reset signal.  I assume its sourced from RESETSTATz (as mentioned in the thread).  The RESETSTATz signals is a reset output of the processor indicating both external reset and internal reset conditions.  I believe your scope is showing eMMC Reset - as the voltage is 1.8V.  Step 1 would be to make sure the same is being seen on RESETSTATz (just to ensure not issue with the level translator and or voltage rail).  If the same is seen on RESETSTATz, then next step is to determine why a reset is occurring after the initial de-assertion.  Verify not external reset input is being issued (MCU_PORz, PORz, MCU_RESETz, RESET_REQz, etc).  The reset could also be internally (processor generated).  If so - then need to determine cause of internal reset.

Juanli,

I tested an EVM and did not see the low pulse at 400ms. It makes me wonder if there is some software aspect in-play?

Kevin

4452.EMMC.pdf

Hi Kevin,

Pls see our schematic.

Best Regards

Juanli Zhang

Hi Kevin and Matt

One more thing to added. The T6: RESETSTATz  belong to output. Our software did not do anything.

Best Regards

Juanli Zhang

As previously mentioned, RESETSTATz is an reset output from the processor and can be asserted from both external and internal reset sources. The RESETSTATz connection with the eMMC RST pin is NOT causing the RESETSTATz signals to be asserted/deasserted.  There is something else cause the reset.  Please check all reset input sources as well as internal registers which track some internal reset assertions.