AM6548: Routing UART1 Interrupt to R50 MCU Using Interrupt Router

Benjamin Roytburd

Part Number: AM6548

Tool/software:

Hello,

I am attempting to trigger an interrupt using the UART1 peripheral on the Cortex-R5F. I am able to use the UART using TI's DRV functions, but using the A53 specific interrupts (CSL_GIC0_INTR_USART1_BUS_USART_IRQ) does not work.

So we looked into using an interrupt routing method similar to what this post describes: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/779597/am6526-creating-an-interrupt-from-pru-to-r5f. But have ran into issues.

We are using SR2.0 and attempting to configure the interrupt routing using the CSL library, the code to do so looks like this:

/* Configure MAIN2MCU_LVL_INTRTR0 interrupt router */
int32_t configureIntrRouter(
    uint32_t intrRtrInIntNum, 
    uint32_t intrRtrOutIntNum
)
{
    CSL_IntrRouterCfg intrRouterMain2MCUCfg;
    int32_t retVal;

    /* Initialize Main to MCU Interrupt Router config structure */
    intrRouterMain2MCUCfg.pIntrRouterRegs = (CSL_intr_router_cfgRegs *)(uintptr_t)(CSL_MAIN2MCU_LVL_INTRTR0_CFG_BASE);
    intrRouterMain2MCUCfg.pIntdRegs       = (CSL_intr_router_intd_cfgRegs *)(uintptr_t)NULL;
    intrRouterMain2MCUCfg.numInputIntrs   = 192;
    intrRouterMain2MCUCfg.numOutputIntrs  = 64;

    retVal = CSL_intrRouterCfgMux(&intrRouterMain2MCUCfg, intrRtrInIntNum, intrRtrOutIntNum);
    if (retVal < 0) 
    {
        return -1;
    }
    
    return 0;
}

And we are calling it like so:

configureIntrRouter(CSLR_MAIN2MCU_LVL_INTRTR0_IN_UART1_USART_IRQ_0, 2);

From what we can tell, we are trying to route the interrupt CSLR_MAIN2MCU_LVL_INTRTR0_IN_UART1_USART_IRQ_0 to interrupt 2 so that the TI UART driver can attach an OSAL interrupt to it.

The issue is, is that our code is hitting a data abort handler at the function CSL_intrRouterCfgMux, specifically at the line where we attempt to disable the interrupt output:

regVal &= ~INTR_ROUTER_CFG_MUXCNTL_INT_ENABLE;
CSL_REG32_WR( &pCfg->pIntrRouterRegs->MUXCNTL[outputIntrNum], regVal );

Does TI know why this is happening? Is our approach to triggering an interrupt in the R5F from UART1 correct?

Thanks,
Ben

over 1 year ago

0 Vaibhav Kumar over 1 year ago

TI__Mastermind 47787 points

Hi Ben,

Allow me sometime to look into this as I need to understand and read through the TRM specifications for AM65x. I would be mostly looking for a section which describes interrupts and interrupt routing.

Regards,

Vaibhav

0 Benjamin Roytburd over 1 year ago in reply to Vaibhav Kumar

Intellectual 300 points

We did also try with the sciclient, with this code:

int32_t configureIntrRouter(uint32_t armss0cpu0InIrqNum)
{
    struct tisci_msg_rm_irq_set_req rmIrqReq;
    struct tisci_msg_rm_irq_set_resp rmIrqResp;
    int32_t status;

    rmIrqReq.src_id = TISCI_DEV_UART1;
    rmIrqReq.src_index = CSLR_MAIN2MCU_LVL_INTRTR0_IN_UART1_USART_IRQ_0;
    rmIrqReq.dst_id = TISCI_DEV_MAIN2MCU_LVL_INTRTR0;
    rmIrqReq.dst_host_irq = armss0cpu0InIrqNum;
    rmIrqReq.valid_params = 0x3;    /* bit mask for dst_id & dst_host_irq */
    status = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, 0xFFFFFFFFU);
    if (status != CSL_PASS)
    {
        return -1;
    }

    return 0;    
}

configureIntrRouter(2);

But this also failed. It did not cause a data abort though. Is one method preferential to the other? Based on my understanding I thought both would work.

0 Benjamin Roytburd over 1 year ago in reply to Benjamin Roytburd

Intellectual 300 points

Seems that I have figured this one out actually, the sciclient was the correct way to do this. Below is the code I used to accomplish this:

int32_t configureIntrRouter(uint32_t armss0cpu0InIrqNum)
{
    struct tisci_msg_rm_irq_set_req rmIrqReq;
    struct tisci_msg_rm_irq_set_resp rmIrqResp;
    int32_t status;

    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
    rmIrqReq.src_id = TISCI_DEV_UART1; 
    rmIrqReq.src_index = 0;
    rmIrqReq.dst_id = TISCI_DEV_MCU_ARMSS0_CPU0;
    rmIrqReq.valid_params = 0x3;    /* bit mask for dst_id & dst_host_irq */
    status = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, 0xFFFFFFFFU);
    if (status != CSL_PASS)
    {
        return -1;
    }

    return 0;    
}

Then I passed the value CSL_MCU0_INTR_MAIN2MCU_LVL_INTR0_OUTL_18 to this function, I also had to go into the UART driver code and update the interrupt number to CSL_MCU0_INTR_MAIN2MCU_LVL_INTR0_OUTL_18. Although this could probably be done through the UART driver APIs.

I am able to trigger read and write callbacks now.

The sciclient docs were helpful here: software-dl.ti.com/.../interrupt_cfg.html

Processors

Processors forum

AM6548: Routing UART1 Interrupt to R50 MCU Using Interrupt Router