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TDA4VH-Q1: ethernet native driver

Part Number: TDA4VH-Q1

Tool/software:

HI:

we now use the ethernat native driver base on SDK9.1 , but counter some problem:

- config Serdes1 LN2 and LN3 for SGMII-1 and SGMII2 ,Serdes2 LN0 for SGMII5 , now linux can detect phy and linked normal, but ping not work

some infomatione as folw:

- sch

serdes1-ln2 for SGMII1 - phy dp83tg720

serdes1-ln3 for SGMII2 - phy dp83tg720

serdes2-ln0 for SGMII5 - phy dp83tc812

- ethfw status

now disabled

- patch code

&serdes_refclk {
	clock-frequency = <100000000>;
};

&serdes_ln_ctrl {
	idle-states = <J784S4_SERDES0_LANE0_IP4_UNUSED>, <J784S4_SERDES0_LANE1_IP1_UNUSED>,
				<J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_IP4_UNUSED>,
				<J784S4_SERDES1_LANE0_IP3_UNUSED>, <J784S4_SERDES1_LANE1_IP3_UNUSED>,
				<J784S4_SERDES1_LANE2_QSGMII_LANE1>, <J784S4_SERDES1_LANE3_QSGMII_LANE2>,
				<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_IP3_UNUSED>,
				<J784S4_SERDES2_LANE2_IP3_UNUSED>, <J784S4_SERDES2_LANE3_IP3_UNUSED>;
};

&serdes_wiz1 {
	status = "okay";
};

&serdes1 {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	serdes1_sgmii_link: phy@0 {
		reg = <2>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets =  <&serdes_wiz1 3>,<&serdes_wiz1 4>;
	};
};

&serdes_wiz2 {
	status = "okay";
};

&serdes2 {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	serdes2_sgmii_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets =  <&serdes_wiz2 1>;
	};
};

&main_cpsw0 {
	status = "okay";
};

&main_cpsw0_port1 {
	status = "okay";
	phy-handle = <&cpsw9g_phy0>;
	phy-mode = "sgmii";
	mac-address = [00 00 00 00 00 01];
	phys = <&cpsw0_phy_gmii_sel 1>, <&serdes1_sgmii_link>;
	phy-names = "portmode", "serdes-phy";
};

&main_cpsw0_port2 {
	status = "okay";
	phy-handle = <&cpsw9g_phy1>;
	phy-mode = "sgmii";
	mac-address = [00 00 00 00 00 02];
	phys = <&cpsw0_phy_gmii_sel 2>, <&serdes1_sgmii_link>;
	phy-names = "portmode", "serdes-phy";
};

&main_cpsw0_port5 {
	status = "okay";
	phy-handle = <&cpsw9g_phy2>;
	phy-mode = "sgmii";
	mac-address = [00 00 00 00 00 03];
	phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_link>;
	phy-names = "portmode", "serdes-phy";
};


&main_cpsw0_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio0_pins_default>;

	cpsw9g_phy0: ethernet-phy@10 {
		reg = <10>;
		compatible = "ethernet-phy-ieee802.3-c22";
		ethphy-mode = "master";
		ethphy-speed = <1000>;
	};

	cpsw9g_phy1: ethernet-phy@4 {
		reg = <4>;
		compatible = "ethernet-phy-ieee802.3-c22";
		ethphy-mode = "master";
		ethphy-speed = <1000>;
	};

	cpsw9g_phy2: ethernet-phy@8 {
		reg = <8>;
		compatible = "ethernet-phy-ieee802.3-c22";
		ethphy-mode = "master";
		ethphy-speed = <100>;
	};
};

- dts

&serdes_refclk {
	clock-frequency = <100000000>;
};

&serdes_ln_ctrl {
	idle-states = <J784S4_SERDES0_LANE0_IP4_UNUSED>, <J784S4_SERDES0_LANE1_IP1_UNUSED>,
				<J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_IP4_UNUSED>,
				<J784S4_SERDES1_LANE0_IP3_UNUSED>, <J784S4_SERDES1_LANE1_IP3_UNUSED>,
				<J784S4_SERDES1_LANE2_QSGMII_LANE1>, <J784S4_SERDES1_LANE3_QSGMII_LANE2>,
				<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_IP3_UNUSED>,
				<J784S4_SERDES2_LANE2_IP3_UNUSED>, <J784S4_SERDES2_LANE3_IP3_UNUSED>;
};

&serdes_wiz1 {
	status = "okay";
};

&serdes1 {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	serdes1_sgmii_link: phy@0 {
		reg = <2>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets =  <&serdes_wiz1 3>,<&serdes_wiz1 4>;
	};
};

&serdes_wiz2 {
	status = "okay";
};

&serdes2 {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	serdes2_sgmii_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets =  <&serdes_wiz2 1>;
	};
};

&main_cpsw0 {
	status = "okay";
};

&main_cpsw0_port1 {
	status = "okay";
	phy-handle = <&cpsw9g_phy0>;
	phy-mode = "sgmii";
	mac-address = [00 00 00 00 00 01];
	phys = <&cpsw0_phy_gmii_sel 1>, <&serdes1_sgmii_link>;
	phy-names = "portmode", "serdes-phy";
};

&main_cpsw0_port2 {
	status = "okay";
	phy-handle = <&cpsw9g_phy1>;
	phy-mode = "sgmii";
	mac-address = [00 00 00 00 00 02];
	phys = <&cpsw0_phy_gmii_sel 2>, <&serdes1_sgmii_link>;
	phy-names = "portmode", "serdes-phy";
};

&main_cpsw0_port5 {
	status = "okay";
	phy-handle = <&cpsw9g_phy2>;
	phy-mode = "sgmii";
	mac-address = [00 00 00 00 00 03];
	phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_link>;
	phy-names = "portmode", "serdes-phy";
};


&main_cpsw0_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio0_pins_default>;

	cpsw9g_phy0: ethernet-phy@10 {
		reg = <10>;
		compatible = "ethernet-phy-ieee802.3-c22";
		ethphy-mode = "master";
		ethphy-speed = <1000>;
	};

	cpsw9g_phy1: ethernet-phy@4 {
		reg = <4>;
		compatible = "ethernet-phy-ieee802.3-c22";
		ethphy-mode = "master";
		ethphy-speed = <1000>;
	};

	cpsw9g_phy2: ethernet-phy@8 {
		reg = <8>;
		compatible = "ethernet-phy-ieee802.3-c22";
		ethphy-mode = "master";
		ethphy-speed = <100>;
	};
};

- network card

eth0      Link encap:Ethernet  HWaddr 00:00:00:00:00:01
          inet addr:172.16.0.1  Bcast:172.16.15.255  Mask:255.255.240.0
          inet6 addr: fe80::200:ff:fe00:1/64 Scope:Link
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:22 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:1744 (1.7 KiB)

eth1      Link encap:Ethernet  HWaddr 00:00:00:00:00:02
          inet addr:198.18.36.1  Bcast:198.18.255.255  Mask:255.255.0.0
          inet6 addr: fe80::200:ff:fe00:2/64 Scope:Link
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:168 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:7876 (7.6 KiB)

eth2      Link encap:Ethernet  HWaddr 00:00:00:00:00:03
          UP BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

lo        Link encap:Local Loopback
          inet addr:127.0.0.1  Mask:255.0.0.0
          inet6 addr: ::1/128 Scope:Host
          UP LOOPBACK RUNNING  MTU:65536  Metric:1
          RX packets:2182 errors:0 dropped:0 overruns:0 frame:0
          TX packets:2182 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:190896 (186.4 KiB)  TX bytes:190896 (186.4 KiB)

- ethtool info

Settings for eth0:
        Supported ports: [ TP    MII ]
        Supported link modes:   1000baseT/Full
        Supported pause frame use: Symmetric
        Supports auto-negotiation: No
        Supported FEC modes: Not reported
        Advertised link modes:  Not reported
        Advertised pause frame use: Symmetric
        Advertised auto-negotiation: No
        Advertised FEC modes: Not reported
        Speed: 1000Mb/s
        Duplex: Full
        Auto-negotiation: off
        master-slave cfg: forced master
        master-slave status: master
        Port: Twisted Pair
        PHYAD: 10
        Transceiver: external
        MDI-X: Unknown
        Supports Wake-on: d
        Wake-on: d
        Current message level: 0x000020f7 (8439)
                               drv probe link ifdown ifup rx_err tx_err hw
        Link detected: yes
        SQI: 7/7

- regster dump

[0x00104080] SERDES0_LN0_CTRL                 : 0x00000003
[0x00104084] SERDES0_LN1_CTRL                 : 0x00000000
[0x00104088] SERDES0_LN2_CTRL                 : 0x00000002
[0x0010408C] SERDES0_LN3_CTRL                 : 0x00000003
[0x00104090] SERDES1_LN0_CTRL                 : 0x00000002
[0x00104094] SERDES1_LN1_CTRL                 : 0x00000002
[0x00104098] SERDES1_LN2_CTRL                 : 0x00000000
[0x0010409C] SERDES1_LN3_CTRL                 : 0x00000000
[0x001040A0] SERDES2_LN0_CTRL                 : 0x00000000
[0x001040A4] SERDES2_LN1_CTRL                 : 0x00000002
[0x001040A8] SERDES2_LN2_CTRL                 : 0x00000002
[0x001040AC] SERDES2_LN3_CTRL                 : 0x00000002
[0x001040C0] SERDES4_LN0_CTRL                 : 0x00000000
[0x001040C4] SERDES4_LN1_CTRL                 : 0x00000000
[0x001040C8] SERDES4_LN2_CTRL                 : 0x00000000
[0x001040CC] SERDES4_LN3_CTRL                 : 0x00000000
[0x001040E0] SERDES0_CTRL                     : 0x00000000
[0x001040E4] SERDES1_CTRL                     : 0x00000000
[0x001040E8] SERDES2_CTRL                     : 0x00000000
[0x001040F0] SERDES4_CTRL                     : 0x00000000
[0x0c000078] CPSW9_STATUS_SGMII_LINK          : 0x00000000
[0x0c000100] CPSW9_SGMII_IDVER0               : 0x00000000
[0x0c000200] CPSW9_SGMII_IDVER1               : 0x00000000
[0x0c000300] CPSW9_SGMII_IDVER2               : 0x4EC21102
[0x0c000400] CPSW9_SGMII_IDVER3               : 0x4EC21102
[0x0c000500] CPSW9_SGMII_IDVER4               : 0x00000000
[0x0c000600] CPSW9_SGMII_IDVER5               : 0x4EC21102
[0x0c000700] CPSW9_SGMII_IDVER6               : 0x4EC21102
[0x0c000800] CPSW9_SGMII_IDVER7               : 0x4EC21102
[0x0c000104] CPSW9_SGMII_SOFT_RST0            : 0x00000000
[0x0c000204] CPSW9_SGMII_SOFT_RST1            : 0x00000000
[0x0c000304] CPSW9_SGMII_SOFT_RST2            : 0x00000000
[0x0c000404] CPSW9_SGMII_SOFT_RST3            : 0x00000000
[0x0c000504] CPSW9_SGMII_SOFT_RST4            : 0x00000000
[0x0c000604] CPSW9_SGMII_SOFT_RST5            : 0x00000000
[0x0c000704] CPSW9_SGMII_SOFT_RST6            : 0x00000000
[0x0c000804] CPSW9_SGMII_SOFT_RST7            : 0x00000000
[0x0c000110] CPSW9_SGMII_CTRL0                : 0x00000000
[0x0c000210] CPSW9_SGMII_CTRL1                : 0x00000000
[0x0c000310] CPSW9_SGMII_CTRL2                : 0x00000000
[0x0c000410] CPSW9_SGMII_CTRL3                : 0x00000000
[0x0c000510] CPSW9_SGMII_CTRL4                : 0x00000000
[0x0c000610] CPSW9_SGMII_CTRL5                : 0x00000000
[0x0c000710] CPSW9_SGMII_CTRL6                : 0x00000000
[0x0c000810] CPSW9_SGMII_CTRL7                : 0x00000000
[0x0c000114] CPSW9_SGMII_STATUS0              : 0x00000000
[0x0c000214] CPSW9_SGMII_STATUS1              : 0x00000000
[0x0c000314] CPSW9_SGMII_STATUS2              : 0x00000028
[0x0c000414] CPSW9_SGMII_STATUS3              : 0x00000020
[0x0c000514] CPSW9_SGMII_STATUS4              : 0x00000000
[0x0c000614] CPSW9_SGMII_STATUS5              : 0x00000022
[0x0c000714] CPSW9_SGMII_STATUS6              : 0x00000020
[0x0c000814] CPSW9_SGMII_STATUS7              : 0x00000020
[0x0c000118] CPSW9_SGMII_MR_ADV_ABLT0         : 0x00000000
[0x0c000218] CPSW9_SGMII_MR_ADV_ABLT1         : 0x00000000
[0x0c000318] CPSW9_SGMII_MR_ADV_ABLT2         : 0x00000000
[0x0c000418] CPSW9_SGMII_MR_ADV_ABLT3         : 0x00000000
[0x0c000518] CPSW9_SGMII_MR_ADV_ABLT4         : 0x00000000
[0x0c000618] CPSW9_SGMII_MR_ADV_ABLT5         : 0x00000000
[0x0c000718] CPSW9_SGMII_MR_ADV_ABLT6         : 0x00000000
[0x0c000818] CPSW9_SGMII_MR_ADV_ABLT7         : 0x00000000
[0x0c00011C] CPSW9_SGMII_MR_NP_TX0            : 0x00000000
[0x0c00021C] CPSW9_SGMII_MR_NP_TX1            : 0x00000000
[0x0c00031C] CPSW9_SGMII_MR_NP_TX2            : 0x00000000
[0x0c00041C] CPSW9_SGMII_MR_NP_TX3            : 0x00000000
[0x0c00051C] CPSW9_SGMII_MR_NP_TX4            : 0x00000000
[0x0c00061C] CPSW9_SGMII_MR_NP_TX5            : 0x00000000
[0x0c00071C] CPSW9_SGMII_MR_NP_TX6            : 0x00000000
[0x0c00081C] CPSW9_SGMII_MR_NP_TX7            : 0x00000000
[0x0c000120] CPSW9_SGMII_MR_LP_ADV_ABLT0      : 0x00000000
[0x0c000220] CPSW9_SGMII_MR_LP_ADV_ABLT1      : 0x00000000
[0x0c000320] CPSW9_SGMII_MR_LP_ADV_ABLT2      : 0x00000213
[0x0c000420] CPSW9_SGMII_MR_LP_ADV_ABLT3      : 0x00000000
[0x0c000520] CPSW9_SGMII_MR_LP_ADV_ABLT4      : 0x00000000
[0x0c000620] CPSW9_SGMII_MR_LP_ADV_ABLT5      : 0x000080C6
[0x0c000720] CPSW9_SGMII_MR_LP_ADV_ABLT6      : 0x00000000
[0x0c000820] CPSW9_SGMII_MR_LP_ADV_ABLT7      : 0x00000000
[0x0c000124] CPSW9_SGMII_MR_LP_NP_RX0         : 0x00000000
[0x0c000224] CPSW9_SGMII_MR_LP_NP_RX1         : 0x00000000
[0x0c000324] CPSW9_SGMII_MR_LP_NP_RX2         : 0x00000160
[0x0c000424] CPSW9_SGMII_MR_LP_NP_RX3         : 0x00000000
[0x0c000524] CPSW9_SGMII_MR_LP_NP_RX4         : 0x00000000
[0x0c000624] CPSW9_SGMII_MR_LP_NP_RX5         : 0x00000013
[0x0c000724] CPSW9_SGMII_MR_LP_NP_RX6         : 0x00000000
[0x0c000824] CPSW9_SGMII_MR_LP_NP_RX7         : 0x00000000
[0x0c000140] CPSW9_SGMII_DIAG0                : 0x00000000
[0x0c000240] CPSW9_SGMII_DIAG1                : 0x00000000
[0x0c000340] CPSW9_SGMII_DIAG2                : 0x00000000
[0x0c000440] CPSW9_SGMII_DIAG3                : 0x00000000
[0x0c000540] CPSW9_SGMII_DIAG4                : 0x00000000
[0x0c000640] CPSW9_SGMII_DIAG5                : 0x00000000
[0x0c000740] CPSW9_SGMII_DIAG6                : 0x00000000
[0x0c000840] CPSW9_SGMII_DIAG7                : 0x00000000
[0x0c000144] CPSW9_SGMII_DIAG_CTRL0           : 0x00000000
[0x0c000244] CPSW9_SGMII_DIAG_CTRL1           : 0x00000000
[0x0c000344] CPSW9_SGMII_DIAG_CTRL2           : 0x00000000
[0x0c000444] CPSW9_SGMII_DIAG_CTRL3           : 0x00000000
[0x0c000544] CPSW9_SGMII_DIAG_CTRL4           : 0x00000000
[0x0c000644] CPSW9_SGMII_DIAG_CTRL5           : 0x00000000
[0x0c000744] CPSW9_SGMII_DIAG_CTRL6           : 0x00000000
[0x0c000844] CPSW9_SGMII_DIAG_CTRL7           : 0x00000000
[0x0c000148] CPSW9_SGMII_DIAG_STATUS0         : 0x00000000
[0x0c000248] CPSW9_SGMII_DIAG_STATUS1         : 0x00000000
[0x0c000348] CPSW9_SGMII_DIAG_STATUS2         : 0x00000004
[0x0c000448] CPSW9_SGMII_DIAG_STATUS3         : 0x00000000
[0x0c000548] CPSW9_SGMII_DIAG_STATUS4         : 0x00000000
[0x0c000648] CPSW9_SGMII_DIAG_STATUS5         : 0x00000680
[0x0c000748] CPSW9_SGMII_DIAG_STATUS6         : 0x00000000
[0x0c000848] CPSW9_SGMII_DIAG_STATUS7         : 0x00000000
[0x00104044] ENET1_CTRL                       : 0x00000003
[0x00104048] ENET2_CTRL                       : 0x00000003
[0x0010404C] ENET3_CTRL                       : 0x00000002
[0x00104050] ENET4_CTRL                       : 0x00000002
[0x00104054] ENET5_CTRL                       : 0x00000003
[0x00104058] ENET6_CTRL                       : 0x00000002
[0x0010405C] ENET7_CTRL                       : 0x00000002
[0x00104060] ENET8_CTRL                       : 0x00000002
[0x0c021014] PORT0_VLAN_REG                   : 0x00000000
[0x0c022014] PORT1_VLAN_REG                   : 0x00000000
[0x0c023014] PORT2_VLAN_REG                   : 0x00000000
[0x0c024014] PORT3_VLAN_REG                   : 0x00000000
[0x0c025014] PORT4_VLAN_REG                   : 0x00000000
[0x0c026014] PORT5_VLAN_REG                   : 0x00000000
[0x0c027014] PORT6_VLAN_REG                   : 0x00000000
[0x0c028014] PORT7_VLAN_REG                   : 0x00000000
[0x0c029014] PORT8_VLAN_REG                   : 0x00000000
[0x01008400] CTRL_MMR_SERDES0_CLKSEL          : 0x00000000
[0x01008410] CTRL_MMR_SERDES1_CLKSEL          : 0x00000000
[0x01008420] CTRL_MMR_SERDES2_CLKSEL          : 0x00000000
[0x01008440] CTRL_MMR_SERDES4_CLKSEL          : 0x00000000
[0x05060408] SERDES0_TOP_CTRL                 : 0x08000000
[0x0506040C] SERDES0_RST                      : 0x00000000
[0x05060480] SERDES0_CONFIG_LANECTL0T         : 0x00000000
[0x0506C01C] SERDES0_PHY_PLL_CFG              : 0x00000001
[0x05060340] SERDES0_CMN_PDIAG_PLL0_CTRL_M0   : 0x00000000
[0x050641C8] SERDES0_XCVR_DIAG_XDP_PWRI_STAT0 : 0x00000000
[0x050645C8] SERDES0_XCVR_DIAG_XDP_PWRI_STAT1 : 0x00000000
[0x050649C8] SERDES0_XCVR_DIAG_XDP_PWRI_STAT2 : 0x00000000
[0x05064DC8] SERDES0_XCVR_DIAG_XDP_PWRI_STAT3 : 0x00000000
[0x050641CC] SERDES0_XCVR_DIAG_HSCLK_SEL0     : 0x00000000
[0x050645CC] SERDES0_XCVR_DIAG_HSCLK_SEL1     : 0x00000000
[0x050649CC] SERDES0_XCVR_DIAG_HSCLK_SEL2     : 0x00000000
[0x05064DCC] SERDES0_XCVR_DIAG_HSCLK_SEL3     : 0x00000000
[0x05060104] SERDES0_CMN_PLL0_VCOCAL_TCTRL    : 0x00000000
[0x05060184] SERDES0_CMN_PLL1_VCOCAL_TCTRL    : 0x00000000
[0x05064200] SERDES0_TX_PSC_A1__TX_PSC_A0_0   : 0x00000000
[0x05064600] SERDES0_TX_PSC_A1__TX_PSC_A0_1   : 0x00000000
[0x05064a00] SERDES0_TX_PSC_A1__TX_PSC_A0_2   : 0x00000000
[0x05064e00] SERDES0_TX_PSC_A1__TX_PSC_A0_3   : 0x00000000
[0x05064204] SERDES0_TX_PSC_A3__TX_PSC_A2_0   : 0x00000000
[0x05064604] SERDES0_TX_PSC_A3__TX_PSC_A2_1   : 0x00000000
[0x05064a04] SERDES0_TX_PSC_A3__TX_PSC_A2_2   : 0x00000000
[0x05064e04] SERDES0_TX_PSC_A3__TX_PSC_A2_3   : 0x00000000
[0x05068000] SERDES0_RX_PSC_A1__RX_PSC_A0_0   : 0x00000000
[0x05068400] SERDES0_RX_PSC_A1__RX_PSC_A0_1   : 0x00000000
[0x05068800] SERDES0_RX_PSC_A1__RX_PSC_A0_2   : 0x00000000
[0x05068B00] SERDES0_RX_PSC_A1__RX_PSC_A0_3   : 0x00000000
[0x05068004] SERDES0_RX_PSC_A3__RX_PSC_A2_0   : 0x00000000
[0x05068404] SERDES0_RX_PSC_A3__RX_PSC_A2_1   : 0x00000000
[0x05068804] SERDES0_RX_PSC_A3__RX_PSC_A2_2   : 0x00000000
[0x05068B04] SERDES0_RX_PSC_A3__RX_PSC_A2_3   : 0x00000000
[0x05064098] SERDES0_TX_TXCC_CPOST_MULT_00_0  : 0x00000000
[0x05064498] SERDES0_TX_TXCC_CPOST_MULT_00_1  : 0x00000000
[0x05064898] SERDES0_TX_TXCC_CPOST_MULT_00_2  : 0x00000000
[0x05064B98] SERDES0_TX_TXCC_CPOST_MULT_00_3  : 0x00000000
[0x0506418c] SERDES0_DRV_DIAG_TX_DRV_0        : 0x00000000
[0x0506458c] SERDES0_DRV_DIAG_TX_DRV_1        : 0x00000000
[0x0506498c] SERDES0_DRV_DIAG_TX_DRV_2        : 0x00000000
[0x05064D8c] SERDES0_DRV_DIAG_TX_DRV_3        : 0x00000000
[0x05068210] SERDES0_RX_REE_GCSM1_CTRL_0      : 0x00000000
[0x05068610] SERDES0_RX_REE_GCSM1_CTRL_1      : 0x00000000
[0x05068a10] SERDES0_RX_REE_GCSM1_CTRL_2      : 0x00000000
[0x05068e10] SERDES0_RX_REE_GCSM1_CTRL_3      : 0x00000000
[0x05068214] SERDES0_RX_REE_GCSM1_EQENM_PH2_0 : 0x00000000
[0x05068614] SERDES0_RX_REE_GCSM1_EQENM_PH2_1 : 0x00000000
[0x05068a14] SERDES0_RX_REE_GCSM1_EQENM_PH2_2 : 0x00000000
[0x05068e14] SERDES0_RX_REE_GCSM1_EQENM_PH2_3 : 0x00000000
[0x050683c0] SERDES0_RX_DIAG_DFE_CTRL_0       : 0x4DDD0004
[0x050687c0] SERDES0_RX_DIAG_DFE_CTRL_1       : 0x4DDD0004
[0x05068bc0] SERDES0_RX_DIAG_DFE_CTRL_2       : 0x4DDD0004
[0x05068fc0] SERDES0_RX_DIAG_DFE_CTRL_3       : 0x4DDD0004
[0x050682e0] SERDES0_RX_REE_ADDR_CFG_0        : 0x00000000
[0x050686e0] SERDES0_RX_REE_ADDR_CFG_1        : 0x00000000
[0x05068ae0] SERDES0_RX_REE_ADDR_CFG_2        : 0x00000000
[0x05068ee0] SERDES0_RX_REE_ADDR_CFG_3        : 0x00000000
[0x050682e4] SERDES0_RX_REE_TAP2TON_CLIP_0    : 0x00000000
[0x050686e4] SERDES0_RX_REE_TAP2TON_CLIP_1    : 0x00000000
[0x05068ae4] SERDES0_RX_REE_TAP2TON_CLIP_2    : 0x00000000
[0x05068ee4] SERDES0_RX_REE_TAP2TON_CLIP_3    : 0x00000000
[0x050683c8] SERDES0_RX_DIAG_REE_DAC_CTRL_0   : 0x0B980004
[0x050687c8] SERDES0_RX_DIAG_REE_DAC_CTRL_1   : 0x0B980004
[0x05068bc8] SERDES0_RX_DIAG_REE_DAC_CTRL_2   : 0x0B980004
[0x05068fc8] SERDES0_RX_DIAG_REE_DAC_CTRL_3   : 0x0B980004
[0x050683c4] SERDES0_RX_DIAG_DFE_AMP_TUNE_2_0 : 0x00000C01
[0x050687c4] SERDES0_RX_DIAG_DFE_AMP_TUNE_2_1 : 0x00000C01
[0x05068bc4] SERDES0_RX_DIAG_DFE_AMP_TUNE_2_2 : 0x00000C01
[0x05068fc4] SERDES0_RX_DIAG_DFE_AMP_TUNE_2_3 : 0x00000C01
[0x050683e8] SERDES0_RX_DIAG_PI_RATE_0        : 0x00000311
[0x050687e8] SERDES0_RX_DIAG_PI_RATE_1        : 0x00000311
[0x05068be8] SERDES0_RX_DIAG_PI_RATE_2        : 0x00000311
[0x05068fe8] SERDES0_RX_DIAG_PI_RATE_3        : 0x00000311
[0x050683fc] SERDES0_RX_DIAG_DCYA_0           : 0x00000000
[0x050687fc] SERDES0_RX_DIAG_DCYA_1           : 0x00000000
[0x05068bfc] SERDES0_RX_DIAG_DCYA_2           : 0x00000000
[0x05068ffc] SERDES0_RX_DIAG_DCYA_3           : 0x00000000
[0x05068100] SERDES0_RX_CDRLF_CNFG_0          : 0x00000000
[0x05068500] SERDES0_RX_CDRLF_CNFG_1          : 0x00000000
[0x05068900] SERDES0_RX_CDRLF_CNFG_2          : 0x00000000
[0x05068d00] SERDES0_RX_CDRLF_CNFG_3          : 0x00000000
[0x050603c0] SERDES0_CMN_DIAG_BANDGAP_OVRD    : 0x36000005
[0x05060204] SERDES0_CMN_TXPUCAL_START        : 0x00000000
[0x05060214] SERDES0_CMN_TXPDCAL_START        : 0x00000000
[0x05070408] SERDES1_TOP_CTRL                 : 0x18100000
[0x0507040C] SERDES1_RST                      : 0x22800000
[0x05070480] SERDES1_CONFIG_LANECTL0T         : 0x30000000
[0x0507C01C] SERDES1_PHY_PLL_CFG              : 0x00000001
[0x05070340] SERDES1_CMN_PDIAG_PLL0_CTRL_M0   : 0x06011012
[0x050741C8] SERDES1_XCVR_DIAG_XDP_PWRI_STAT0 : 0x00120024
[0x050745C8] SERDES1_XCVR_DIAG_XDP_PWRI_STAT1 : 0x00120024
[0x050749C8] SERDES1_XCVR_DIAG_XDP_PWRI_STAT2 : 0x00120024
[0x05074DC8] SERDES1_XCVR_DIAG_XDP_PWRI_STAT3 : 0x00120024
[0x050741CC] SERDES1_XCVR_DIAG_HSCLK_SEL0     : 0x00010000
[0x050745CC] SERDES1_XCVR_DIAG_HSCLK_SEL1     : 0x00010000
[0x050749CC] SERDES1_XCVR_DIAG_HSCLK_SEL2     : 0x00010000
[0x05074DCC] SERDES1_XCVR_DIAG_HSCLK_SEL3     : 0x00010000
[0x05070104] SERDES1_CMN_PLL0_VCOCAL_TCTRL    : 0x00000004
[0x05070184] SERDES1_CMN_PLL1_VCOCAL_TCTRL    : 0x00000004
[0x05074200] SERDES1_TX_PSC_A1__TX_PSC_A0_0   : 0x04AF00FF
[0x05074600] SERDES1_TX_PSC_A1__TX_PSC_A0_1   : 0x04AF00FF
[0x05074a00] SERDES1_TX_PSC_A1__TX_PSC_A0_2   : 0x04AF00FF
[0x05074e00] SERDES1_TX_PSC_A1__TX_PSC_A0_3   : 0x04AF00FF
[0x05074204] SERDES1_TX_PSC_A3__TX_PSC_A2_0   : 0x04AE04AE
[0x05074604] SERDES1_TX_PSC_A3__TX_PSC_A2_1   : 0x04AE04AE
[0x05074a04] SERDES1_TX_PSC_A3__TX_PSC_A2_2   : 0x04AE04AE
[0x05074e04] SERDES1_TX_PSC_A3__TX_PSC_A2_3   : 0x04AE04AE
[0x05078000] SERDES1_RX_PSC_A1__RX_PSC_A0_0   : 0x091D091D
[0x05078400] SERDES1_RX_PSC_A1__RX_PSC_A0_1   : 0x091D091D
[0x05078800] SERDES1_RX_PSC_A1__RX_PSC_A0_2   : 0x091D091D
[0x05078B00] SERDES1_RX_PSC_A1__RX_PSC_A0_3   : 0x00000000
[0x05078004] SERDES1_RX_PSC_A3__RX_PSC_A2_0   : 0x00000900
[0x05078404] SERDES1_RX_PSC_A3__RX_PSC_A2_1   : 0x00000900
[0x05078804] SERDES1_RX_PSC_A3__RX_PSC_A2_2   : 0x00000900
[0x05078B04] SERDES1_RX_PSC_A3__RX_PSC_A2_3   : 0x00000000
[0x05074098] SERDES1_TX_TXCC_CPOST_MULT_00_0  : 0x0011001C
[0x05074498] SERDES1_TX_TXCC_CPOST_MULT_00_1  : 0x0011001C
[0x05074898] SERDES1_TX_TXCC_CPOST_MULT_00_2  : 0x0011001C
[0x05074B98] SERDES1_TX_TXCC_CPOST_MULT_00_3  : 0x00000000
[0x0507418c] SERDES1_DRV_DIAG_TX_DRV_0        : 0x000000A3
[0x0507458c] SERDES1_DRV_DIAG_TX_DRV_1        : 0x000000A3
[0x0507498c] SERDES1_DRV_DIAG_TX_DRV_2        : 0x000000A3
[0x05074D8c] SERDES1_DRV_DIAG_TX_DRV_3        : 0x000000A3
[0x05078210] SERDES1_RX_REE_GCSM1_CTRL_0      : 0x03E70009
[0x05078610] SERDES1_RX_REE_GCSM1_CTRL_1      : 0x03E70009
[0x05078a10] SERDES1_RX_REE_GCSM1_CTRL_2      : 0x03E70009
[0x05078e10] SERDES1_RX_REE_GCSM1_CTRL_3      : 0x03E70009
[0x05078214] SERDES1_RX_REE_GCSM1_EQENM_PH2_0 : 0x000001E7
[0x05078614] SERDES1_RX_REE_GCSM1_EQENM_PH2_1 : 0x000001E7
[0x05078a14] SERDES1_RX_REE_GCSM1_EQENM_PH2_2 : 0x000001E7
[0x05078e14] SERDES1_RX_REE_GCSM1_EQENM_PH2_3 : 0x000001E7
[0x050783c0] SERDES1_RX_DIAG_DFE_CTRL_0       : 0x4DDD0004
[0x050787c0] SERDES1_RX_DIAG_DFE_CTRL_1       : 0x4DDD0004
[0x05078bc0] SERDES1_RX_DIAG_DFE_CTRL_2       : 0x4DDD0004
[0x05078fc0] SERDES1_RX_DIAG_DFE_CTRL_3       : 0x4DDD0004
[0x050782e0] SERDES1_RX_REE_ADDR_CFG_0        : 0x05190101
[0x050786e0] SERDES1_RX_REE_ADDR_CFG_1        : 0x05190101
[0x05078ae0] SERDES1_RX_REE_ADDR_CFG_2        : 0x05190101
[0x05078ee0] SERDES1_RX_REE_ADDR_CFG_3        : 0x05190101
[0x050782e4] SERDES1_RX_REE_TAP2TON_CLIP_0    : 0x40000519
[0x050786e4] SERDES1_RX_REE_TAP2TON_CLIP_1    : 0x40000519
[0x05078ae4] SERDES1_RX_REE_TAP2TON_CLIP_2    : 0x40000519
[0x05078ee4] SERDES1_RX_REE_TAP2TON_CLIP_3    : 0x40000519
[0x050783c8] SERDES1_RX_DIAG_REE_DAC_CTRL_0   : 0x0B980004
[0x050787c8] SERDES1_RX_DIAG_REE_DAC_CTRL_1   : 0x0B980004
[0x05078bc8] SERDES1_RX_DIAG_REE_DAC_CTRL_2   : 0x0B980004
[0x05078fc8] SERDES1_RX_DIAG_REE_DAC_CTRL_3   : 0x0B980004
[0x050783c4] SERDES1_RX_DIAG_DFE_AMP_TUNE_2_0 : 0x00000C01
[0x050787c4] SERDES1_RX_DIAG_DFE_AMP_TUNE_2_1 : 0x00000C01
[0x05078bc4] SERDES1_RX_DIAG_DFE_AMP_TUNE_2_2 : 0x00000C01
[0x05078fc4] SERDES1_RX_DIAG_DFE_AMP_TUNE_2_3 : 0x00000C01
[0x050783e8] SERDES1_RX_DIAG_PI_RATE_0        : 0x00000311
[0x050787e8] SERDES1_RX_DIAG_PI_RATE_1        : 0x00000311
[0x05078be8] SERDES1_RX_DIAG_PI_RATE_2        : 0x00000311
[0x05078fe8] SERDES1_RX_DIAG_PI_RATE_3        : 0x00000311
[0x050783fc] SERDES1_RX_DIAG_DCYA_0           : 0x00000000
[0x050787fc] SERDES1_RX_DIAG_DCYA_1           : 0x00000000
[0x05078bfc] SERDES1_RX_DIAG_DCYA_2           : 0x00000000
[0x05078ffc] SERDES1_RX_DIAG_DCYA_3           : 0x00000000
[0x05078100] SERDES1_RX_CDRLF_CNFG_0          : 0x0A33018C
[0x05078500] SERDES1_RX_CDRLF_CNFG_1          : 0x0A33018C
[0x05078900] SERDES1_RX_CDRLF_CNFG_2          : 0x0A33018C
[0x05078d00] SERDES1_RX_CDRLF_CNFG_3          : 0x0A33018C
[0x050703c0] SERDES1_CMN_DIAG_BANDGAP_OVRD    : 0x36000005
[0x05070204] SERDES1_CMN_TXPUCAL_START        : 0x0000002D
[0x05070214] SERDES1_CMN_TXPDCAL_START        : 0x0000802D
[0x05020408] SERDES2_TOP_CTRL                 : 0x18100000
[0x0502040C] SERDES2_RST                      : 0x22800000
[0x05020480] SERDES2_CONFIG_LANECTL0T         : 0x30000000
[0x0502C01C] SERDES2_PHY_PLL_CFG              : 0x00000001
[0x05020340] SERDES2_CMN_PDIAG_PLL0_CTRL_M0   : 0x06011012
[0x050241C8] SERDES2_XCVR_DIAG_XDP_PWRI_STAT0 : 0x00120024
[0x050245C8] SERDES2_XCVR_DIAG_XDP_PWRI_STAT1 : 0x00120024
[0x050249C8] SERDES2_XCVR_DIAG_XDP_PWRI_STAT2 : 0x00120024
[0x05024DC8] SERDES2_XCVR_DIAG_XDP_PWRI_STAT3 : 0x00120024
[0x050241CC] SERDES2_XCVR_DIAG_HSCLK_SEL0     : 0x00010000
[0x050245CC] SERDES2_XCVR_DIAG_HSCLK_SEL1     : 0x00010000
[0x050249CC] SERDES2_XCVR_DIAG_HSCLK_SEL2     : 0x00010000
[0x05024DCC] SERDES2_XCVR_DIAG_HSCLK_SEL3     : 0x00010000
[0x05020104] SERDES2_CMN_PLL0_VCOCAL_TCTRL    : 0x00000004
[0x05020184] SERDES2_CMN_PLL1_VCOCAL_TCTRL    : 0x00000004
[0x05024200] SERDES2_TX_PSC_A1__TX_PSC_A0_0   : 0x04AF00FF
[0x05024600] SERDES2_TX_PSC_A1__TX_PSC_A0_1   : 0x04AF00FF
[0x05024a00] SERDES2_TX_PSC_A1__TX_PSC_A0_2   : 0x04AF00FF
[0x05024e00] SERDES2_TX_PSC_A1__TX_PSC_A0_3   : 0x04AF00FF
[0x05024204] SERDES2_TX_PSC_A3__TX_PSC_A2_0   : 0x04AE04AE
[0x05024604] SERDES2_TX_PSC_A3__TX_PSC_A2_1   : 0x04AE04AE
[0x05024a04] SERDES2_TX_PSC_A3__TX_PSC_A2_2   : 0x04AE04AE
[0x05024e04] SERDES2_TX_PSC_A3__TX_PSC_A2_3   : 0x04AE04AE
[0x05028000] SERDES2_RX_PSC_A1__RX_PSC_A0_0   : 0x091D091D
[0x05028400] SERDES2_RX_PSC_A1__RX_PSC_A0_1   : 0x091D091D
[0x05028800] SERDES2_RX_PSC_A1__RX_PSC_A0_2   : 0x091D091D
[0x05028B00] SERDES2_RX_PSC_A1__RX_PSC_A0_3   : 0x00000000
[0x05028004] SERDES2_RX_PSC_A3__RX_PSC_A2_0   : 0x00000900
[0x05028404] SERDES2_RX_PSC_A3__RX_PSC_A2_1   : 0x00000900
[0x05028804] SERDES2_RX_PSC_A3__RX_PSC_A2_2   : 0x00000900
[0x05028B04] SERDES2_RX_PSC_A3__RX_PSC_A2_3   : 0x00000000
[0x05024098] SERDES2_TX_TXCC_CPOST_MULT_00_0  : 0x0011001C
[0x05024498] SERDES2_TX_TXCC_CPOST_MULT_00_1  : 0x0011001C
[0x05024898] SERDES2_TX_TXCC_CPOST_MULT_00_2  : 0x0011001C
[0x05024B98] SERDES2_TX_TXCC_CPOST_MULT_00_3  : 0x00000000
[0x0502418c] SERDES2_DRV_DIAG_TX_DRV_0        : 0x000000A3
[0x0502458c] SERDES2_DRV_DIAG_TX_DRV_1        : 0x000000A3
[0x0502498c] SERDES2_DRV_DIAG_TX_DRV_2        : 0x000000A3
[0x05024D8c] SERDES2_DRV_DIAG_TX_DRV_3        : 0x000000A3
[0x05028210] SERDES2_RX_REE_GCSM1_CTRL_0      : 0x03E70009
[0x05028610] SERDES2_RX_REE_GCSM1_CTRL_1      : 0x03E70009
[0x05028a10] SERDES2_RX_REE_GCSM1_CTRL_2      : 0x03E70009
[0x05028e10] SERDES2_RX_REE_GCSM1_CTRL_3      : 0x03E70009
[0x05028214] SERDES2_RX_REE_GCSM1_EQENM_PH2_0 : 0x000001E7
[0x05028614] SERDES2_RX_REE_GCSM1_EQENM_PH2_1 : 0x000001E7
[0x05028a14] SERDES2_RX_REE_GCSM1_EQENM_PH2_2 : 0x000001E7
[0x05028e14] SERDES2_RX_REE_GCSM1_EQENM_PH2_3 : 0x000001E7
[0x050283c0] SERDES2_RX_DIAG_DFE_CTRL_0       : 0x4DDD0004
[0x050287c0] SERDES2_RX_DIAG_DFE_CTRL_1       : 0x4DDD0004
[0x05028bc0] SERDES2_RX_DIAG_DFE_CTRL_2       : 0x4DDD0004
[0x05028fc0] SERDES2_RX_DIAG_DFE_CTRL_3       : 0x4DDD0004
[0x050282e0] SERDES2_RX_REE_ADDR_CFG_0        : 0x05190101
[0x050286e0] SERDES2_RX_REE_ADDR_CFG_1        : 0x05190101
[0x05028ae0] SERDES2_RX_REE_ADDR_CFG_2        : 0x05190101
[0x05028ee0] SERDES2_RX_REE_ADDR_CFG_3        : 0x05190101
[0x050282e4] SERDES2_RX_REE_TAP2TON_CLIP_0    : 0x40000519
[0x050286e4] SERDES2_RX_REE_TAP2TON_CLIP_1    : 0x40000519
[0x05028ae4] SERDES2_RX_REE_TAP2TON_CLIP_2    : 0x40000519
[0x05028ee4] SERDES2_RX_REE_TAP2TON_CLIP_3    : 0x40000519
[0x050283c8] SERDES2_RX_DIAG_REE_DAC_CTRL_0   : 0x0B980004
[0x050287c8] SERDES2_RX_DIAG_REE_DAC_CTRL_1   : 0x0B980004
[0x05028bc8] SERDES2_RX_DIAG_REE_DAC_CTRL_2   : 0x0B980004
[0x05028fc8] SERDES2_RX_DIAG_REE_DAC_CTRL_3   : 0x0B980004
[0x050283c4] SERDES2_RX_DIAG_DFE_AMP_TUNE_2_0 : 0x00000C01
[0x050287c4] SERDES2_RX_DIAG_DFE_AMP_TUNE_2_1 : 0x00000C01
[0x05028bc4] SERDES2_RX_DIAG_DFE_AMP_TUNE_2_2 : 0x00000C01
[0x05028fc4] SERDES2_RX_DIAG_DFE_AMP_TUNE_2_3 : 0x00000C01
[0x050283e8] SERDES2_RX_DIAG_PI_RATE_0        : 0x00000311
[0x050287e8] SERDES2_RX_DIAG_PI_RATE_1        : 0x00000311
[0x05028be8] SERDES2_RX_DIAG_PI_RATE_2        : 0x00000311
[0x05028fe8] SERDES2_RX_DIAG_PI_RATE_3        : 0x00000311
[0x050283fc] SERDES2_RX_DIAG_DCYA_0           : 0x00000000
[0x050287fc] SERDES2_RX_DIAG_DCYA_1           : 0x00000000
[0x05028bfc] SERDES2_RX_DIAG_DCYA_2           : 0x00000000
[0x05028ffc] SERDES2_RX_DIAG_DCYA_3           : 0x00000000
[0x05028100] SERDES2_RX_CDRLF_CNFG_0          : 0x0A33018C
[0x05028500] SERDES2_RX_CDRLF_CNFG_1          : 0x0A33018C
[0x05028900] SERDES2_RX_CDRLF_CNFG_2          : 0x0A33018C
[0x05028d00] SERDES2_RX_CDRLF_CNFG_3          : 0x0A33018C
[0x050203c0] SERDES2_CMN_DIAG_BANDGAP_OVRD    : 0x36000005
[0x05020204] SERDES2_CMN_TXPUCAL_START        : 0x0000002D
[0x05020214] SERDES2_CMN_TXPDCAL_START        : 0x0000802D
[0x05050408] SERDES4_TOP_CTRL                 : 0x30000000
[0x0505040C] SERDES4_RST                      : 0x2A800000
[0x05050480] SERDES4_CONFIG_LANECTL0T         : 0x70000000
[0x0505C01C] SERDES4_PHY_PLL_CFG              : 0x00000000
[0x05050340] SERDES4_CMN_PDIAG_PLL0_CTRL_M0   : 0x07011012
[0x050541C8] SERDES4_XCVR_DIAG_XDP_PWRI_STAT0 : 0x00010024
[0x050545C8] SERDES4_XCVR_DIAG_XDP_PWRI_STAT1 : 0x00010024
[0x050549C8] SERDES4_XCVR_DIAG_XDP_PWRI_STAT2 : 0x00010024
[0x05054DC8] SERDES4_XCVR_DIAG_XDP_PWRI_STAT3 : 0x00010024
[0x050541CC] SERDES4_XCVR_DIAG_HSCLK_SEL0     : 0x00010000
[0x050545CC] SERDES4_XCVR_DIAG_HSCLK_SEL1     : 0x00010000
[0x050549CC] SERDES4_XCVR_DIAG_HSCLK_SEL2     : 0x00010000
[0x05054DCC] SERDES4_XCVR_DIAG_HSCLK_SEL3     : 0x00010000
[0x05050104] SERDES4_CMN_PLL0_VCOCAL_TCTRL    : 0x00000003
[0x05050184] SERDES4_CMN_PLL1_VCOCAL_TCTRL    : 0x00000003
[0x05054200] SERDES4_TX_PSC_A1__TX_PSC_A0_0   : 0x04AF00FB
[0x05054600] SERDES4_TX_PSC_A1__TX_PSC_A0_1   : 0x04AF00FB
[0x05054a00] SERDES4_TX_PSC_A1__TX_PSC_A0_2   : 0x04AF00FB
[0x05054e00] SERDES4_TX_PSC_A1__TX_PSC_A0_3   : 0x04AF00FB
[0x05054204] SERDES4_TX_PSC_A3__TX_PSC_A2_0   : 0x04AA04AA
[0x05054604] SERDES4_TX_PSC_A3__TX_PSC_A2_1   : 0x04AA04AA
[0x05054a04] SERDES4_TX_PSC_A3__TX_PSC_A2_2   : 0x04AA04AA
[0x05054e04] SERDES4_TX_PSC_A3__TX_PSC_A2_3   : 0x04AA04AA
[0x05058000] SERDES4_RX_PSC_A1__RX_PSC_A0_0   : 0x091D0000
[0x05058400] SERDES4_RX_PSC_A1__RX_PSC_A0_1   : 0x091D0000
[0x05058800] SERDES4_RX_PSC_A1__RX_PSC_A0_2   : 0x091D0000
[0x05058B00] SERDES4_RX_PSC_A1__RX_PSC_A0_3   : 0x00000000
[0x05058004] SERDES4_RX_PSC_A3__RX_PSC_A2_0   : 0x00000000
[0x05058404] SERDES4_RX_PSC_A3__RX_PSC_A2_1   : 0x00000000
[0x05058804] SERDES4_RX_PSC_A3__RX_PSC_A2_2   : 0x00000000
[0x05058B04] SERDES4_RX_PSC_A3__RX_PSC_A2_3   : 0x00000000
[0x05054098] SERDES4_TX_TXCC_CPOST_MULT_00_0  : 0x0011001C
[0x05054498] SERDES4_TX_TXCC_CPOST_MULT_00_1  : 0x0011001C
[0x05054898] SERDES4_TX_TXCC_CPOST_MULT_00_2  : 0x0011001C
[0x05054B98] SERDES4_TX_TXCC_CPOST_MULT_00_3  : 0x00000000
[0x0505418c] SERDES4_DRV_DIAG_TX_DRV_0        : 0x000000A3
[0x0505458c] SERDES4_DRV_DIAG_TX_DRV_1        : 0x000000A3
[0x0505498c] SERDES4_DRV_DIAG_TX_DRV_2        : 0x000000A3
[0x05054D8c] SERDES4_DRV_DIAG_TX_DRV_3        : 0x000000A3
[0x05058210] SERDES4_RX_REE_GCSM1_CTRL_0      : 0x03E70000
[0x05058610] SERDES4_RX_REE_GCSM1_CTRL_1      : 0x03E70000
[0x05058a10] SERDES4_RX_REE_GCSM1_CTRL_2      : 0x03E70000
[0x05058e10] SERDES4_RX_REE_GCSM1_CTRL_3      : 0x03E70000
[0x05058214] SERDES4_RX_REE_GCSM1_EQENM_PH2_0 : 0x000001E7
[0x05058614] SERDES4_RX_REE_GCSM1_EQENM_PH2_1 : 0x000001E7
[0x05058a14] SERDES4_RX_REE_GCSM1_EQENM_PH2_2 : 0x000001E7
[0x05058e14] SERDES4_RX_REE_GCSM1_EQENM_PH2_3 : 0x000001E7
[0x050583c0] SERDES4_RX_DIAG_DFE_CTRL_0       : 0x4DDD0004
[0x050587c0] SERDES4_RX_DIAG_DFE_CTRL_1       : 0x4DDD0004
[0x05058bc0] SERDES4_RX_DIAG_DFE_CTRL_2       : 0x4DDD0004
[0x05058fc0] SERDES4_RX_DIAG_DFE_CTRL_3       : 0x4DDD0004
[0x050582e0] SERDES4_RX_REE_ADDR_CFG_0        : 0x05190101
[0x050586e0] SERDES4_RX_REE_ADDR_CFG_1        : 0x05190101
[0x05058ae0] SERDES4_RX_REE_ADDR_CFG_2        : 0x05190101
[0x05058ee0] SERDES4_RX_REE_ADDR_CFG_3        : 0x05190101
[0x050582e4] SERDES4_RX_REE_TAP2TON_CLIP_0    : 0x40000519
[0x050586e4] SERDES4_RX_REE_TAP2TON_CLIP_1    : 0x40000519
[0x05058ae4] SERDES4_RX_REE_TAP2TON_CLIP_2    : 0x40000519
[0x05058ee4] SERDES4_RX_REE_TAP2TON_CLIP_3    : 0x40000519
[0x050583c8] SERDES4_RX_DIAG_REE_DAC_CTRL_0   : 0x0B980004
[0x050587c8] SERDES4_RX_DIAG_REE_DAC_CTRL_1   : 0x0B980004
[0x05058bc8] SERDES4_RX_DIAG_REE_DAC_CTRL_2   : 0x0B980004
[0x05058fc8] SERDES4_RX_DIAG_REE_DAC_CTRL_3   : 0x0B980004
[0x050583c4] SERDES4_RX_DIAG_DFE_AMP_TUNE_2_0 : 0x00000C01
[0x050587c4] SERDES4_RX_DIAG_DFE_AMP_TUNE_2_1 : 0x00000C01
[0x05058bc4] SERDES4_RX_DIAG_DFE_AMP_TUNE_2_2 : 0x00000C01
[0x05058fc4] SERDES4_RX_DIAG_DFE_AMP_TUNE_2_3 : 0x00000C01
[0x050583e8] SERDES4_RX_DIAG_PI_RATE_0        : 0x00000311
[0x050587e8] SERDES4_RX_DIAG_PI_RATE_1        : 0x00000311
[0x05058be8] SERDES4_RX_DIAG_PI_RATE_2        : 0x00000311
[0x05058fe8] SERDES4_RX_DIAG_PI_RATE_3        : 0x00000311
[0x050583fc] SERDES4_RX_DIAG_DCYA_0           : 0x00000000
[0x050587fc] SERDES4_RX_DIAG_DCYA_1           : 0x00000000
[0x05058bfc] SERDES4_RX_DIAG_DCYA_2           : 0x00000000
[0x05058ffc] SERDES4_RX_DIAG_DCYA_3           : 0x00000000
[0x05058100] SERDES4_RX_CDRLF_CNFG_0          : 0x0A33018C
[0x05058500] SERDES4_RX_CDRLF_CNFG_1          : 0x0A33018C
[0x05058900] SERDES4_RX_CDRLF_CNFG_2          : 0x0A33018C
[0x05058d00] SERDES4_RX_CDRLF_CNFG_3          : 0x0A33018C
[0x050503c0] SERDES4_CMN_DIAG_BANDGAP_OVRD    : 0x36000005
[0x05050204] SERDES4_CMN_TXPUCAL_START        : 0x0000002D
[0x05050214] SERDES4_CMN_TXPDCAL_START        : 0x0000802D

- boot log

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[    0.000000] Linux version 6.1.46-g5892b80d6b (root@5c99d703c1e0) (aarch64-oe-linux-gcc (GCC) 11.4.0, GNU ld (GNU Binutils) 2.38.20220708) #1 SMP PREEMPT Sun Jul 21 14:10:05 UTC 2024
[    0.000000] Machine model: Texas Instruments J784S4 EVM
[    0.000000] efi: UEFI not found.
[    0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a0000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a0100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a1000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a1100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 12 MiB
[    0.000000] OF: reserved mem: initialized node freetech_shared-memories_mcu@a2000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2c00000, size 4 MiB
[    0.000000] OF: reserved mem: initialized node freetech_shared-memories_product@a2c00000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a3000000, size 16 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-core-heap-memory-lo-mcu@a3000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a4000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 47 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a4100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a7000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7100000, size 23 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a7100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8800000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a8800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8900000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a8900000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000aa800000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@aa800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000aa900000, size 23 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@aa900000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ac000000, size 48 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-rtos-ipc-memory-region@ac000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000af000000, size 48 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-dma-memory@af000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b2000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71-dma-memory@b2000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b2100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71_0-memory@b2100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b4000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71_1-dma-memory@b4000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b4100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71_1-memory@b4100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b6000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71_2-dma-memory@b6000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b6100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71_2-memory@b6100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b8000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71_3-dma-memory@b8000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b8100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71_3-memory@b8100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ba000000, size 8 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-virtual-eth-queues@ba000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ba800000, size 24 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-virtual-eth-buffers@ba800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000bc000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@bc000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000bc100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@bc100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000be000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@be000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000be100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@be100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000880000000, size 800 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-core-heap-memory-hi@880000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000008fa000000, size 96 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-core-heap-memory-lo-main@8fa000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: initialized node vision_apps_shared-memories, compatible id dma-heap-carveout
[    0.000000] Reserved memory: created DMA memory pool at 0x000000093c000000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node freetech_shared-memories_mem@93c000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000940000000, size 352 MiB
[    0.000000] OF: reserved mem: initialized node linux-cma-buffers@940000000, compatible id shared-dma-pool
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000000080000000-0x00000000ffffffff]
[    0.000000]   DMA32    empty
[    0.000000]   Normal   [mem 0x0000000100000000-0x00000009ffffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000080000000-0x000000009e7fffff]
[    0.000000]   node   0: [mem 0x000000009e800000-0x00000000bfffffff]
[    0.000000]   node   0: [mem 0x00000000c0000000-0x00000000ffffffff]
[    0.000000]   node   0: [mem 0x0000000880000000-0x00000008b1ffffff]
[    0.000000]   node   0: [mem 0x00000008b2000000-0x00000008f9ffffff]
[    0.000000]   node   0: [mem 0x00000008fa000000-0x00000008ffffffff]
[    0.000000]   node   0: [mem 0x0000000900000000-0x000000093bffffff]
[    0.000000]   node   0: [mem 0x000000093c000000-0x000000093fffffff]
[    0.000000]   node   0: [mem 0x0000000940000000-0x00000009ffffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000009ffffffff]
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.4
[    0.000000] percpu: Embedded 19 pages/cpu s38376 r8192 d31256 u77824
[    0.000000] Detected PIPT I-cache on CPU0
[    0.000000] CPU features: detected: GIC system register CPU interface
[    0.000000] CPU features: detected: Spectre-v3a
[    0.000000] CPU features: detected: Spectre-BHB
[    0.000000] CPU features: kernel page table isolation forced ON by KASLR
[    0.000000] CPU features: detected: Kernel page table isolation (KPTI)
[    0.000000] CPU features: detected: ARM erratum 1742098
[    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[    0.000000] alternatives: applying boot alternatives
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2064384
[    0.000000] Kernel command line: root=/dev/mmcblk1p2 loglevel=7 rw rootfstype=ext4 rootwait nokaslr gpt
[    0.000000] Unknown kernel command line parameters "nokaslr", will be passed to user space.
[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] software IO TLB: area num 8.
[    0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB)
[    0.000000] Memory: 5269588K/8388608K available (11712K kernel code, 1256K rwdata, 3796K rodata, 1984K init, 427K bss, 2758572K reserved, 360448K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
[    0.000000]  Trampoline variant of Tasks RCU enabled.
[    0.000000]  Tracing variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: [Firmware Bug]: GICR region 0x0000000001900000 has overlapping address
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: 960 SPIs implemented
[    0.000000] GICv3: 0 Extended SPIs implemented
[    0.000000] Root IRQ handler: gic_handle_irq
[    0.000000] GICv3: GICv3 features: 16 PPIs
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000
[    0.000000] ITS [mem 0x01820000-0x0182ffff]
[    0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
[    0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19
[    0.000000] ITS@0x0000000001820000: allocated 524288 Devices @8b2800000 (flat, esz 8, psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GICv3: using LPI property table @0x00000008b2050000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] GICv3: CPU0: using allocated LPI pending table @0x00000008b2060000
[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0x3ffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
[    0.000000] sched_clock: 58 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
[    0.000242] Console: colour dummy device 80x25
[    0.000792] printk: console [tty0] enabled
[    0.000825] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
[    0.000836] pid_max: default: 32768 minimum: 301
[    0.000864] LSM: Security Framework initializing
[    0.000934] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
[    0.000961] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
[    0.002022] cblist_init_generic: Setting adjustable number of callback queues.
[    0.002039] cblist_init_generic: Setting shift to 3 and lim to 1.
[    0.002091] cblist_init_generic: Setting adjustable number of callback queues.
[    0.002098] cblist_init_generic: Setting shift to 3 and lim to 1.
[    0.002194] rcu: Hierarchical SRCU implementation.
[    0.002201] rcu:     Max phase no-delay instances is 1000.
[    0.002377] Platform MSI: msi-controller@1820000 domain created
[    0.002550] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created
[    0.002722] EFI services will not be available.
[    0.002986] smp: Bringing up secondary CPUs ...
[    0.012736] Detected PIPT I-cache on CPU1
[    0.012800] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000
[    0.012814] GICv3: CPU1: using allocated LPI pending table @0x00000008b2070000
[    0.012848] CPU1: Booted secondary processor 0x0000000001 [0x411fd080]
[    0.022568] Detected PIPT I-cache on CPU2
[    0.022619] GICv3: CPU2: found redistributor 2 region 0:0x0000000001940000
[    0.022633] GICv3: CPU2: using allocated LPI pending table @0x00000008b2080000
[    0.022659] CPU2: Booted secondary processor 0x0000000002 [0x411fd080]
[    0.032338] Detected PIPT I-cache on CPU3
[    0.032388] GICv3: CPU3: found redistributor 3 region 0:0x0000000001960000
[    0.032401] GICv3: CPU3: using allocated LPI pending table @0x00000008b2090000
[    0.032426] CPU3: Booted secondary processor 0x0000000003 [0x411fd080]
[    0.042415] Detected PIPT I-cache on CPU4
[    0.042499] GICv3: CPU4: found redistributor 100 region 0:0x0000000001980000
[    0.042513] GICv3: CPU4: using allocated LPI pending table @0x00000008b20a0000
[    0.042548] CPU4: Booted secondary processor 0x0000000100 [0x411fd080]
[    0.052188] Detected PIPT I-cache on CPU5
[    0.052248] GICv3: CPU5: found redistributor 101 region 0:0x00000000019a0000
[    0.052262] GICv3: CPU5: using allocated LPI pending table @0x00000008b20b0000
[    0.052288] CPU5: Booted secondary processor 0x0000000101 [0x411fd080]
[    0.061990] Detected PIPT I-cache on CPU6
[    0.062050] GICv3: CPU6: found redistributor 102 region 0:0x00000000019c0000
[    0.062064] GICv3: CPU6: using allocated LPI pending table @0x00000008b20c0000
[    0.062090] CPU6: Booted secondary processor 0x0000000102 [0x411fd080]
[    0.071772] Detected PIPT I-cache on CPU7
[    0.071831] GICv3: CPU7: found redistributor 103 region 0:0x00000000019e0000
[    0.071844] GICv3: CPU7: using allocated LPI pending table @0x00000008b20d0000
[    0.071869] CPU7: Booted secondary processor 0x0000000103 [0x411fd080]
[    0.071920] smp: Brought up 1 node, 8 CPUs
[    0.072015] SMP: Total of 8 processors activated.
[    0.072021] CPU features: detected: 32-bit EL0 Support
[    0.072026] CPU features: detected: CRC32 instructions
[    0.072083] CPU: All CPU(s) started at EL2
[    0.072088] alternatives: applying system-wide alternatives
[    0.073275] devtmpfs: initialized
[    0.080148] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.080187] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
[    0.085151] pinctrl core: initialized pinctrl subsystem
[    0.085499] DMI not present or invalid.
[    0.085883] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    0.086811] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
[    0.087030] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[    0.087220] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.087299] audit: initializing netlink subsys (disabled)
[    0.087462] audit: type=2000 audit(0.080:1): state=initialized audit_enabled=0 res=1
[    0.087686] thermal_sys: Registered thermal governor 'step_wise'
[    0.087691] thermal_sys: Registered thermal governor 'power_allocator'
[    0.087808] cpuidle: using governor menu
[    0.087925] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.088055] ASID allocator initialised with 32768 entries
[    0.096442] KASLR disabled on command line
[    0.099194] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
[    0.099211] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
[    0.099217] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
[    0.099223] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
[    0.099228] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
[    0.099234] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
[    0.099239] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
[    0.099244] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
[    0.100125] k3-chipinfo 43000014.chipid: Family:J784S4 rev:SR1.0 JTAGID[0x0bb8002f] Detected
[    0.101066] iommu: Default domain type: Translated
[    0.101081] iommu: DMA domain TLB invalidation policy: strict mode
[    0.101221] SCSI subsystem initialized
[    0.101482] pps_core: LinuxPPS API ver. 1 registered
[    0.101491] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.101502] PTP clock support registered
[    0.101580] EDAC MC: Ver: 3.0.0
[    0.102115] FPGA manager framework
[    0.102603] clocksource: Switched to clocksource arch_sys_counter
[    0.102773] VFS: Disk quotas dquot_6.6.0
[    0.102805] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    0.105793] Carveout Heap: Exported 960 MiB at 0x0000000900000000
[    0.105879] NET: Registered PF_INET protocol family
[    0.106154] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[    0.108917] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
[    0.108995] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[    0.109014] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
[    0.109248] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
[    0.110195] TCP: Hash tables configured (established 65536 bind 65536)
[    0.110326] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
[    0.110429] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
[    0.110689] NET: Registered PF_UNIX/PF_LOCAL protocol family
[    0.111015] RPC: Registered named UNIX socket transport module.
[    0.111027] RPC: Registered udp transport module.
[    0.111032] RPC: Registered tcp transport module.
[    0.111036] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.111044] NET: Registered PF_XDP protocol family
[    0.111060] PCI: CLS 0 bytes, default 64
[    0.111779] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available
[    0.112716] Initialise system trusted keyrings
[    0.112859] workingset: timestamp_bits=46 max_order=21 bucket_order=0
[    0.114990] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.115308] NFS: Registering the id_resolver key type
[    0.115330] Key type id_resolver registered
[    0.115336] Key type id_legacy registered
[    0.115368] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    0.115376] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    0.135158] Key type asymmetric registered
[    0.135171] Asymmetric key parser 'x509' registered
[    0.135215] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[    0.135329] io scheduler mq-deadline registered
[    0.135338] io scheduler kyber registered
[    0.137646] pinctrl-single 4301c000.pinctrl: 13 pins, size 52
[    0.137743] pinctrl-single 4301c038.pinctrl: 11 pins, size 44
[    0.137858] pinctrl-single 4301c068.pinctrl: 72 pins, size 288
[    0.137937] pinctrl-single 4301c190.pinctrl: 1 pins, size 4
[    0.138071] pinctrl-single 11c000.pinctrl: 72 pins, size 288
[    0.141688] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    0.147074] loop: module loaded
[    0.147883] megasas: 07.719.03.00-rc1
[    0.149464] tun: Universal TUN/TAP device driver, 1.6
[    0.149832] thunder_xcv, ver 1.0
[    0.149856] thunder_bgx, ver 1.0
[    0.149873] nicpf, ver 1.0
[    0.149960] e1000: Intel(R) PRO/1000 Network Driver
[    0.149965] e1000: Copyright (c) 1999-2006 Intel Corporation.
[    0.149991] e1000e: Intel(R) PRO/1000 Network Driver
[    0.149996] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[    0.150014] igb: Intel(R) Gigabit Ethernet Network Driver
[    0.150021] igb: Copyright (c) 2007-2014 Intel Corporation.
[    0.150036] igbvf: Intel(R) Gigabit Virtual Function Network Driver
[    0.150044] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[    0.150110] sky2: driver version 1.30
[    0.150501] VFIO - User Level meta-driver version: 0.3
[    0.150921] i2c_dev: i2c /dev entries driver
[    0.151517] sdhci: Secure Digital Host Controller Interface driver
[    0.151528] sdhci: Copyright(c) Pierre Ossman
[    0.151645] sdhci-pltfm: SDHCI platform and OF driver helper
[    0.152104] ledtrig-cpu: registered to indicate activity on CPUs
[    0.152228] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    0.152896] optee: probing for conduit method.
[    0.152925] optee: revision 4.0 (2a5b1d12)
[    0.169377] optee: dynamic shared memory is enabled
[    0.169619] optee: initialized driver
[    0.170477] Initializing XFRM netlink socket
[    0.170512] NET: Registered PF_PACKET protocol family
[    0.170557] Key type dns_resolver registered
[    0.170827] registered taskstats version 1
[    0.170853] Loading compiled-in X.509 certificates
[    0.178434] ti-sci 44083000.system-controller: ABI: 3.1 (firmware rev 0x0009 '9.1.2--v09.01.02 (Kool Koala)')
[    0.529425] omap_i2c 42120000.i2c: bus 1 rev0.12 at 400 kHz
[    0.530487] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 177 domain created
[    0.531347] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 10 domain created
[    0.532111] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 283 domain created
[    0.533815] ti-sci-inta 33d00000.msi-controller: Interrupt Aggregator domain 321 created
[    0.544255] ti-udma 311a0000.dma-controller: Number of rings: 48
[    0.546577] ti-udma 311a0000.dma-controller: Channels: 24 (bchan: 0, tchan: 8, rchan: 16)
[    0.548407] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:328
[    0.548427] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
[    0.548434] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[    0.550646] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[878,128] sci-dev-id:315
[    0.550662] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[    0.550668] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[    0.551890] 2850000.serial: ttyS3 at MMIO 0x2850000 (irq = 213, base_baud = 3000000) is a 8250
[    0.553131] 2880000.serial: ttyS0 at MMIO 0x2880000 (irq = 214, base_baud = 3000000) is a 8250
[    2.671681] printk: console [ttyS0] enabled
[    2.714617] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    3.423776] davinci_mdio c000f00.mdio: phy[4]: device c000f00.mdio:04, driver TI DP83TG720CS1.1
[    3.432475] davinci_mdio c000f00.mdio: phy[8]: device c000f00.mdio:08, driver TI DP83TC814CS2.0
[    3.441159] davinci_mdio c000f00.mdio: phy[10]: device c000f00.mdio:0a, driver TI DP83TG720CS1.1
[    3.449953] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA03102, cpsw version 0x6BA82902 Ports: 9 quirks:00000000
[    3.462770] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.5
[    3.469898] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
[    3.477711] am65-cpsw-nuss c000000.ethernet: CPTS ver 0x4e8a010c, freq:250000000, add_val:3 pps:0
[    3.497789] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010c, freq:250000000, add_val:3 pps:0
[    3.514504] mmc0: CQHCI version 5.10
[    3.518345] mmc1: CQHCI version 5.10
[    3.559081] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit
[    3.559099] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit
[    3.606970] mmc1: new high speed SDHC card at address 0001
[    3.612922] mmcblk1: mmc1:0001 SD32G 29.1 GiB
[    3.619596]  mmcblk1: p1 p2
[    3.813577] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fca100
[    3.821880] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fca100
[    3.830181] omap-mailbox 31f82000.mailbox: omap mailbox rev 0x66fca100
[    3.838466] omap-mailbox 31f83000.mailbox: omap mailbox rev 0x66fca100
[    3.846773] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fca100
[    3.855048] omap-mailbox 31f85000.mailbox: omap mailbox rev 0x66fca100
[    3.871536] ti-udma 285c0000.dma-controller: Channels: 22 (tchan: 11, rchan: 11, gp-rflow: 8)
[    3.887721] ti-udma 31150000.dma-controller: Channels: 66 (tchan: 33, rchan: 33, gp-rflow: 16)
[    3.898045] mmc0: Command Queue Engine enabled
[    3.902522] mmc0: new HS200 MMC card at address 0001
[    3.907961] mmcblk0: mmc0:0001 A8A58B 29.1 GiB
[    3.914888]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 p23 p24 p25 p26
[    3.926890] mmcblk0boot0: mmc0:0001 A8A58B 31.9 MiB
[    3.932608] mmcblk0boot1: mmc0:0001 A8A58B 31.9 MiB
[    3.938207] mmcblk0rpmb: mmc0:0001 A8A58B 4.00 MiB, chardev (240:0)
[    3.942637] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    4.653705] davinci_mdio c000f00.mdio: phy[4]: device c000f00.mdio:04, driver TI DP83TG720CS1.1
[    4.662407] davinci_mdio c000f00.mdio: phy[8]: device c000f00.mdio:08, driver TI DP83TC814CS2.0
[    4.671091] davinci_mdio c000f00.mdio: phy[10]: device c000f00.mdio:0a, driver TI DP83TG720CS1.1
[    4.679885] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA03102, cpsw version 0x6BA82902 Ports: 9 quirks:00000000
[    4.692708] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.5
[    4.699837] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
[    4.707718] am65-cpsw-nuss c000000.ethernet: CPTS ver 0x4e8a010c, freq:250000000, add_val:3 pps:0
[    4.725892] am65-cpsw-nuss c000000.ethernet: set new flow-id-base 82
[    4.740911] debugfs: Directory 'pd:74' with parent 'pm_genpd' already present!
[    4.748176] debugfs: Directory 'pd:73' with parent 'pm_genpd' already present!
[    4.755475] debugfs: Directory 'pd:72' with parent 'pm_genpd' already present!
[    4.763266] debugfs: Directory 'pd:335' with parent 'pm_genpd' already present!
[    4.770598] debugfs: Directory 'pd:333' with parent 'pm_genpd' already present!
[    4.777919] debugfs: Directory 'pd:332' with parent 'pm_genpd' already present!
[    5.050089] EXT4-fs (mmcblk1p2): recovery complete
[    5.055935] EXT4-fs (mmcblk1p2): mounted filesystem with ordered data mode. Quota mode: none.
[    5.064499] VFS: Mounted root (ext4 filesystem) on device 179:2.
[    5.071474] devtmpfs: mounted
[    5.075244] Freeing unused kernel memory: 1984K
[    5.079891] Run /sbin/init as init process
[    5.453765] systemd[1]: System time before build time, advancing clock.
[    5.526249] NET: Registered PF_INET6 protocol family
[    5.531995] Segment Routing with IPv6
[    5.535689] In-situ OAM (IOAM) with IPv6
[    5.567646] systemd[1]: systemd 250.5+ running in system mode (+PAM -AUDIT -SELINUX -APPARMOR +IMA -SMACK +SECCOMP -GCRYPT -GNUTLS -OPENSSL +ACL +BLKID -CURL -ELFUTILS -FIDO2 -IDN2 -IDN -IPTC +KMOD -LIBCRYPTSETUP +LIBFDISK -PCRE2 -PWQUALITY -P11KIT -QRENCODE -BZIP2 -LZ4 -XZ -ZLIB +ZSTD -BPF_FRAMEWORK +XKBCOMMON +UTMP +SYSVINIT default-hierarchy=hybrid)
[    5.599245] systemd[1]: Detected architecture arm64.

Welcome to Arago 2023.10!

[    5.671522] systemd[1]: Hostname set to <j784s4-evm>.
[    5.930737] systemd[1]: Configuration file /etc/systemd/system/app_init.service is marked executable. Please remove executable permission bits. Proceeding anyway.
[    5.998263] systemd[1]: Queued start job for default target Multi-User System.
[    6.043211] systemd[1]: Created slice Slice /system/getty.
[  OK  ] Created slice Slice /system/getty.
[    6.063638] systemd[1]: Created slice Slice /system/modprobe.
[  OK  ] Created slice Slice /system/modprobe.
[    6.087464] systemd[1]: Created slice Slice /system/serial-getty.
[  OK  ] Created slice Slice /system/serial-getty.
[    6.111312] systemd[1]: Created slice User and Session Slice.
[  OK  ] Created slice User and Session Slice.
[    6.134797] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[  OK  ] Started Dispatch Password …ts to Console Directory Watch.
[    6.158760] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[  OK  ] Started Forward Password R…uests to Wall Directory Watch.
[    6.182772] systemd[1]: Reached target Path Units.
[  OK  ] Reached target Path Units.
[    6.198666] systemd[1]: Reached target Remote File Systems.
[  OK  ] Reached target Remote File Systems.
[    6.218645] systemd[1]: Reached target Slice Units.
[  OK  ] Reached target Slice Units.
[    6.234666] systemd[1]: Reached target Swaps.
[  OK  ] Reached target Swaps.
[    6.253548] systemd[1]: Listening on Process Core Dump Socket.
[  OK  ] Listening on Process Core Dump Socket.
[    6.274835] systemd[1]: Listening on initctl Compatibility Named Pipe.
[  OK  ] Listening on initctl Compatibility Named Pipe.
[    6.299024] systemd[1]: Listening on Journal Audit Socket.
[  OK  ] Listening on Journal Audit Socket.
[    6.318887] systemd[1]: Listening on Journal Socket (/dev/log).
[  OK  ] Listening on Journal Socket (/dev/log).
[    6.338876] systemd[1]: Listening on Journal Socket.
[  OK  ] Listening on Journal Socket.
[    6.354920] systemd[1]: Listening on Network Service Netlink Socket.
[  OK  ] Listening on Network Service Netlink Socket.
[    6.378935] systemd[1]: Listening on udev Control Socket.
[  OK  ] Listening on udev Control Socket.
[    6.398803] systemd[1]: Listening on udev Kernel Socket.
[  OK  ] Listening on udev Kernel Socket.
[    6.418827] systemd[1]: Listening on User Database Manager Socket.
[  OK  ] Listening on User Database Manager Socket.
[    6.458922] systemd[1]: Mounting Huge Pages File System...
         Mounting Huge Pages File System...
[    6.477145] systemd[1]: Mounting POSIX Message Queue File System...
         Mounting POSIX Message Queue File System...
[    6.501134] systemd[1]: Mounting Kernel Debug File System...
         Mounting Kernel Debug File System...
[    6.518924] systemd[1]: Kernel Trace File System was skipped because of a failed condition check (ConditionPathExists=/sys/kernel/tracing).
[    6.534964] systemd[1]: Mounting Temporary Directory /tmp...
         Mounting Temporary Directory /tmp...
[    6.553475] systemd[1]: Starting Create List of Static Device Nodes...
         Starting Create List of Static Device Nodes...
[    6.577376] systemd[1]: Starting Load Kernel Module configfs...
         Starting Load Kernel Module configfs...
[    6.597257] systemd[1]: Starting Load Kernel Module drm...
         Starting Load Kernel Module drm...
[    6.617520] systemd[1]: Starting Load Kernel Module fuse...
         Starting Load Kernel Module fuse...
[    6.634819] systemd[1]: File System Check on Root Device was skipped because of a failed condition check (ConditionPathIsReadWrite=!/).
[    6.651537] systemd[1]: Starting Journal Service...
         Starting Journal Service...
[    6.656773] fuse: init (API version 7.37)
[    6.668693] systemd[1]: Load Kernel Modules was skipped because all trigger condition checks failed.
[    6.680944] systemd[1]: Starting Generate network units from Kernel command line...
         Starting Generate network …ts from Kernel command line...
[    6.747268] systemd[1]: Starting Remount Root and Kernel File Systems...
         Starting Remount Root and Kernel File Systems EXT4-fs (mmcblk1p2): re-mounted. Quota mode: none.
[0m...
[    6.777630] systemd[1]: Starting Apply Kernel Variables...
         Starting Apply Kernel Variables...
[    6.797684] systemd[1]: Starting Coldplug All udev Devices...
         Starting Coldplug All udev Devices...
[    6.819174] systemd[1]: Started Journal Service.
[  OK  ] Started Journal Service.
[  OK  ] Mounted Huge Pages File System.
[  OK  ] Mounted POSIX Message Queue File System.
[  OK  ] Mounted Kernel Debug File System.
[  OK  ] Mounted Temporary Directory /tmp.
[  OK  ] Finished Create List of Static Device Nodes.
[  OK  ] Finished Load Kernel Module configfs.
[  OK  ] Finished Load Kernel Module drm.
[  OK  ] Finished Load Kernel Module fuse.
[  OK  ] Finished Generate network units from Kernel command line.
[  OK  ] Finished Remount Root and Kernel File Systems.
[  OK  ] Finished Apply Kernel Variables.
[  OK  ] Reached target Preparation for Network.
         Mounting FUSE Control File System...
         Mounting Kernel Configuration File System...
         Starting Flush Journal to Persistent Storage...
[    7.115760] systemd-journald[207]: Received client request to flush runtime journal.
         Starting Create Static Device Nodes in /dev...
[  OK  ] Mounted FUSE Control File System.
[  OK  ] Mounted Kernel Configuration File System.
[  OK  ] Finished Flush Journal to Persistent Storage.
[  OK  ] Finished Create Static Device Nodes in /dev.
[  OK  ] Reached target Preparation for Local File Systems.
         Mounting /media/ram...
         Mounting /var/volatile...
[    7.288920] audit: type=1334 audit(1651167746.832:2): prog-id=5 op=LOAD
[    7.295606] audit: type=1334 audit(1651167746.840:3): prog-id=6 op=LOAD
         Starting Rule-based Manage…for Device Events and Files...
[  OK  ] Finished Coldplug All udev Devices.
[  OK  ] Mounted /media/ram.
[  OK  ] Mounted /var/volatile.
         Starting Load/Save Random Seed...
[  OK  ] Reached target Local File Systems.
         Starting Create Volatile Files and Directories...
[  OK  ] Started Rule-based Manager for Device Events and Files.
         Starting Network Configuration...
[    7.486051] random: crng init done
[  OK  ] Finished Create Volatile Files and [    7.500279] mc: Linux media interface: v0.10
Directories.
[  OK  ] Found device /dev/ttyS0.
         Starting Network Time Synchronization...
         Starting Record System Boot/Shutdown in UTMP...
[    7.621923] videodev: Linux video capture interface: v2.00
[    7.623801] pvrsrvkm: loading out-of-tree module taints kernel.
[    7.629466] k3_r5_rproc bus@100000:bus@28380000:r5fss@41000000: MCU cluster requires both R5F cores to be enabled but num_cores is set to = 0
[  OK  ] Finished Record System Boot/Shutdown in UTMP.
[    7.662444] platform 5c00000.r5f: R5F core may have been powered on by a different host, programmed state (0) != actual state (1)
[    7.676412] PVR_K:  254: Device: 4e20000000.gpu
[    7.678356] platform 5c00000.r5f: configured R5F for IPC-only mode
[    7.687758] platform 5c00000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@a4000000
[    7.689676] PVR_K:  254: Read BVNC 36.53.104.796 from HW device registers
[    7.689819] k3-dsp-rproc 64800000.dsp: assigned reserved memory node vision-apps-c71-dma-memory@b2000000
[    7.691298] k3-dsp-rproc 64800000.dsp: configured DSP for IPC-only mode
[    7.692533] remoteproc remoteproc1: 64800000.dsp is available
[    7.692598] remoteproc remoteproc1: attaching to 64800000.dsp
[    7.693376] remoteproc remoteproc1: unsupported resource 65538
[    7.693489] k3-dsp-rproc 64800000.dsp: DSP initialized in IPC-only mode
[    7.693502] rproc-virtio rproc-virtio.5.auto: assigned reserved memory node vision-apps-c71-dma-memory@b2000000
[    7.693588] rproc-virtio rproc-virtio.5.auto: registered virtio0 (type 7)
[    7.693595] remoteproc remoteproc1: remote processor 64800000.dsp is now attached
[    7.695096] k3-dsp-rproc 65800000.dsp: assigned reserved memory node vision-apps-c71_1-dma-memory@b4000000
[    7.697003] k3-dsp-rproc 65800000.dsp: configured DSP for IPC-only mode
[    7.705624] PVR_K:  254: RGX Device registered BVNC 36.53.104.796 with 1 core in the system
[    7.716145] remoteproc remoteproc0: 5c00000.r5f is available
[    7.761683] remoteproc remoteproc2: 65800000.dsp is available
[    7.771072] remoteproc remoteproc0: attaching to 5c00000.r5f
[    7.776222] [drm] Initialized pvr 23.2.6460340 20170530 for 4e20000000.gpu on minor 0
[    7.778301] remoteproc remoteproc2: attaching to 65800000.dsp
[    7.786172] platform 5c00000.r5f: R5F core initialized in IPC-only mode
[    7.795140] remoteproc remoteproc2: unsupported resource 65538
[    7.799117] rproc-virtio rproc-virtio.6.auto: assigned reserved memory node vision-apps-r5f-dma-memory@a4000000
[    7.805773] k3-dsp-rproc 65800000.dsp: DSP initialized in IPC-only mode
[    7.811039] rproc-virtio rproc-virtio.6.auto: registered virtio1 (type 7)
[    7.819382] rproc-virtio rproc-virtio.7.auto: assigned reserved memory node vision-apps-c71_1-dma-memory@b4000000
[    7.824410] remoteproc remoteproc0: remote processor 5c00000.r5f is now attached
[    7.830777] rproc-virtio rproc-virtio.7.auto: registered virtio2 (type 7)
[    7.837844] platform 5d00000.r5f: R5F core may have been powered on by a different host, programmed state (0) != actual state (1)
[    7.846674] remoteproc remoteproc2: remote processor 65800000.dsp is now attached
[    7.856239] platform 5d00000.r5f: configured R5F for IPC-only mode
[    7.871916] k3-dsp-rproc 66800000.dsp: assigned reserved memory node vision-apps-c71_2-dma-memory@b6000000
[    7.878088] platform 5d00000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@a7000000
[    7.890051] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[    7.898179] k3-dsp-rproc 66800000.dsp: configured DSP for IPC-only mode
[    7.899595] remoteproc remoteproc3: 5d00000.r5f is available
[    7.899666] remoteproc remoteproc3: attaching to 5d00000.r5f
[    7.900097] platform 5d00000.r5f: R5F core initialized in IPC-only mode
[    7.900117] rproc-virtio rproc-virtio.8.auto: assigned reserved memory node vision-apps-r5f-dma-memory@a7000000
[    7.900188] rproc-virtio rproc-virtio.8.auto: registered virtio3 (type 7)
[    7.900194] remoteproc remoteproc3: remote processor 5d00000.r5f is now attached
[    7.906796] platform 5e00000.r5f: R5F core may have been powered on by a different host, programmed state (0) != actual state (1)
[    7.910122] remoteproc remoteproc4: 66800000.dsp is available
[    7.923370] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[    7.924099] platform 5e00000.r5f: configured R5F for IPC-only mode
[    7.924305] platform 5e00000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@bc000000
[    7.924975] remoteproc remoteproc5: 5e00000.r5f is available
[    7.925028] remoteproc remoteproc5: attaching to 5e00000.r5f
[    7.925607] platform 5e00000.r5f: R5F core initialized in IPC-only mode
[    7.925622] rproc-virtio rproc-virtio.9.auto: assigned reserved memory node vision-apps-r5f-dma-memory@bc000000
[    7.925690] rproc-virtio rproc-virtio.9.auto: registered virtio4 (type 7)
[    7.925697] remoteproc remoteproc5: remote processor 5e00000.r5f is now attached
[    7.927037] platform 5f00000.r5f: R5F core may have been powered on by a different host, programmed state (0) != actual state (1)
[    7.929085] remoteproc remoteproc4: attaching to 66800000.dsp
[    7.929439] platform 5f00000.r5f: configured R5F for IPC-only mode
[    7.929744] platform 5f00000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@be000000
[    7.933720] remoteproc remoteproc6: 5f00000.r5f is available
[    7.933783] remoteproc remoteproc6: attaching to 5f00000.r5f
[    7.936891] platform 5f00000.r5f: R5F core initialized in IPC-only mode
[    7.945429] remoteproc remoteproc4: unsupported resource 65538
[    7.949922] rproc-virtio rproc-virtio.10.auto: assigned reserved memory node vision-apps-r5f-dma-memory@be000000
[    7.954898] k3-dsp-rproc 66800000.dsp: DSP initialized in IPC-only mode
[    7.961909] rproc-virtio rproc-virtio.10.auto: registered virtio5 (type 7)
[    7.971642] rproc-virtio rproc-virtio.11.auto: assigned reserved memory node vision-apps-c71_2-dma-memory@b6000000
[    7.971787] rproc-virtio rproc-virtio.11.auto: registered virtio6 (type 7)
[    7.978552] remoteproc remoteproc6: remote processor 5f00000.r5f is now attached
[    7.998755] platform 5900000.r5f: R5F core may have been powered on by a different host, programmed state (0) != actual state (1)
[    8.003443] remoteproc remoteproc4: remote processor 66800000.dsp is now attached
[    8.012181] platform 5900000.r5f: configured R5F for IPC-only mode
[    8.025943] omap_rng 4e10000.rng: Random Number Generator ver. 241b34c
[    8.031424] k3-dsp-rproc 67800000.dsp: assigned reserved memory node vision-apps-c71_3-dma-memory@b8000000
[    8.031441] platform 5900000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@a8800000
[    8.033459] remoteproc remoteproc7: 5900000.r5f is available
[    8.033538] remoteproc remoteproc7: attaching to 5900000.r5f
[    8.033995] platform 5900000.r5f: R5F core initialized in IPC-only mode
[    8.034015] rproc-virtio rproc-virtio.12.auto: assigned reserved memory node vision-apps-r5f-dma-memory@a8800000
[    8.034188] rproc-virtio rproc-virtio.12.auto: registered virtio7 (type 7)
[    8.034196] remoteproc remoteproc7: remote processor 5900000.r5f is now attached
[    8.035095] platform 5a00000.r5f: R5F core may have been powered on by a different host, programmed state (0) != actual state (1)
[    8.037067] platform 5a00000.r5f: configured R5F for IPC-only mode
[    8.045153] k3-dsp-rproc 67800000.dsp: configured DSP for IPC-only mode
[    8.054034] platform 5a00000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@aa800000
[    8.060447] remoteproc remoteproc8: 67800000.dsp is available
[    8.069505] remoteproc remoteproc9: 5a00000.r5f is available
[    8.079506] remoteproc remoteproc8: attaching to 67800000.dsp
[    8.085221] remoteproc remoteproc9: attaching to 5a00000.r5f
[    8.091679] remoteproc remoteproc8: unsupported resource 65538
[    8.100749] platform 5a00000.r5f: R5F core initialized in IPC-only mode
[    8.106124] k3-dsp-rproc 67800000.dsp: DSP initialized in IPC-only mode
[    8.111728] rproc-virtio rproc-virtio.14.auto: assigned reserved memory node vision-apps-r5f-dma-memory@aa800000
[    8.118328] rproc-virtio rproc-virtio.13.auto: assigned reserved memory node vision-apps-c71_3-dma-memory@b8000000
[    8.124226] rproc-virtio rproc-virtio.14.auto: registered virtio8 (type 7)
[    8.134355] rproc-virtio rproc-virtio.13.auto: registered virtio9 (type 7)
[    8.140916] remoteproc remoteproc9: remote processor 5a00000.r5f is now attached
[    8.147772] remoteproc remoteproc8: remote processor 67800000.dsp is now attached
[    8.184597] virtio_rpmsg_bus virtio0: rpmsg host is online
[    8.199148] virtio_rpmsg_bus virtio0: creating channel rpmsg_chrdev addr 0xd
[    8.204980] virtio_rpmsg_bus virtio1: rpmsg host is online
[    8.220369] virtio_rpmsg_bus virtio1: creating channel rpmsg_chrdev addr 0xd
[    8.223739] virtio_rpmsg_bus virtio2: rpmsg host is online
[    8.235052] virtio_rpmsg_bus virtio2: creating channel rpmsg_chrdev addr 0xd
[    8.241680] virtio_rpmsg_bus virtio3: rpmsg host is online
[    8.254508] virtio_rpmsg_bus virtio3: creating channel rpmsg_chrdev addr 0xd
[    8.258705] virtio_rpmsg_bus virtio4: rpmsg host is online
[    8.271138] virtio_rpmsg_bus virtio4: creating channel rpmsg_chrdev addr 0xd
[    8.277604] virtio_rpmsg_bus virtio5: rpmsg host is online
[    8.289942] virtio_rpmsg_bus virtio5: creating channel rpmsg_chrdev addr 0xd
[    8.290385] virtio_rpmsg_bus virtio6: rpmsg host is online
[    8.299830] virtio_rpmsg_bus virtio6: creating channel rpmsg_chrdev addr 0xd
[    8.305148] virtio_rpmsg_bus virtio7: rpmsg host is online
[    8.317055] virtio_rpmsg_bus virtio7: creating channel rpmsg_chrdev addr 0xd
[    8.322201] virtio_rpmsg_bus virtio8: rpmsg host is online
[    8.328267] am65-cpsw-nuss c000000.ethernet eth2: PHY [c000f00.mdio:08] driver [TI DP83TC814CS2.0] (irq=POLL)
[    8.334214] virtio_rpmsg_bus virtio8: creating channel rpmsg_chrdev addr 0xd
[    8.334717] virtio_rpmsg_bus virtio9: rpmsg host is online
[    8.340929] am65-cpsw-nuss c000000.ethernet eth2: configuring for phy/sgmii link mode
[    8.343907] virtio_rpmsg_bus virtio9: creating channel rpmsg_chrdev addr 0xd
[    8.344087] virtio_rpmsg_bus virtio9: creating channel rpmsg_chrdev addr 0x15
[    8.344191] virtio_rpmsg_bus virtio0: creating channel rpmsg_chrdev addr 0x15
[    8.344307] virtio_rpmsg_bus virtio2: creating channel rpmsg_chrdev addr 0x15
[    8.344373] virtio_rpmsg_bus virtio6: creating channel rpmsg_chrdev addr 0x15
[    8.344437] virtio_rpmsg_bus virtio4: creating channel rpmsg_chrdev addr 0x15
[    8.344532] virtio_rpmsg_bus virtio1: creating channel rpmsg_chrdev addr 0x15
[    8.344609] virtio_rpmsg_bus virtio5: creating channel rpmsg_chrdev addr 0x15
[    8.344675] virtio_rpmsg_bus virtio8: creating channel rpmsg_chrdev addr 0x15
[    8.344812] virtio_rpmsg_bus virtio3: creating channel rpmsg_chrdev addr 0x15
[    8.344988] virtio_rpmsg_bus virtio7: creating channel rpmsg_chrdev addr 0x15
[    8.345056] virtio_rpmsg_bus virtio2: creating channel rpmsg_chrdev addr 0x17
[    8.345135] virtio_rpmsg_bus virtio0: creating channel rpmsg_chrdev addr 0x17
[    8.345196] virtio_rpmsg_bus virtio9: creating channel rpmsg_chrdev addr 0x17
[    8.345258] virtio_rpmsg_bus virtio1: creating channel rpmsg_chrdev addr 0x17
[    8.345319] virtio_rpmsg_bus virtio4: creating channel rpmsg_chrdev addr 0x17
[    8.345379] virtio_rpmsg_bus virtio5: creating channel rpmsg_chrdev addr 0x17
[    8.345432] virtio_rpmsg_bus virtio3: creating channel rpmsg_chrdev addr 0x17
[    8.345485] virtio_rpmsg_bus virtio7: creating channel rpmsg_chrdev addr 0x17
[    8.345540] virtio_rpmsg_bus virtio8: creating channel rpmsg_chrdev addr 0x17
[    8.345645] virtio_rpmsg_bus virtio6: creating channel rpmsg_chrdev addr 0x17
[    8.347149] virtio_rpmsg_bus virtio0: creating channel ti.ipc4.ping-pong addr 0xe
[    8.348344] virtio_rpmsg_bus virtio8: creating channel ti.ipc4.ping-pong addr 0xe
[    8.348705] virtio_rpmsg_bus virtio4: creating channel ti.ipc4.ping-pong addr 0xe
[    8.348785] virtio_rpmsg_bus virtio5: creating channel ti.ipc4.ping-pong addr 0xe
[    8.365362] virtio_rpmsg_bus virtio9: creating channel ti.ipc4.ping-pong addr 0xe
[    8.368326] am65_cpsw_nuss_mac_config writel addr 0x:e600518 value:9801
[  OK  ] Finished Load/Save Random Seed.[    8.719949] virtio_rpmsg_bus virtio6: creating channel ti.ipc4.ping-pong addr 0xe

[    8.733025] virtio_rpmsg_bus virtio2: creating channel ti.ipc4.ping-pong addr 0xe
[    8.740665] virtio_rpmsg_bus virtio3: creating channel ti.ipc4.ping-pong addr 0xe
[    8.748350] virtio_rpmsg_bus virtio7: creating channel ti.ipc4.ping-pong addr 0xe
[    8.756016] virtio_rpmsg_bus virtio1: creating channel ti.ipc4.ping-pong addr 0xe
[  OK  ] Started Network Time Synchronization.
[  OK  ] Started Network Configuration.
[  OK  ] Reached target System Initialization.
[  OK  ] Started Daily Cleanup of Temporary Directories.
[  OK  ] Reached target System Time Set.
[  OK  ] Reached target Timer Units.[    9.058994] am65-cpsw-nuss c000000.ethernet eth1: PHY [c000f00.mdio:04] driver [TI DP83TG720CS1.1] (irq=POLL)

[    9.069855] am65-cpsw-nuss c000000.ethernet eth1: configuring for phy/sgmii link mode
[    9.077820] am65_cpsw_nuss_mac_config writel addr 0x:e600218 value:9801
[  OK  ] Listening on D-Bus System Message B[    9.087282] am65-cpsw-nuss c000000.ethernet eth1: Link is Up - 1Gbps/Full - flow control off
us Socket.
[  OK  ] Reached target Socket Units.
[  OK  ] Reached target Basic System.
[  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.
         Starting app-init...
         Starting D-Bus System Message Bus...
[    9.286352] audit: type=1334 audit(1651186240.044:4): prog-id=7 op=LOAD
[    9.293077] audit: type=1334 audit(1651186240.052:5): prog-id=8 op=LOAD
         Starting User Login Management...
         Starting Network Name Resolution...
[    9.445743] am65-cpsw-nuss c000000.ethernet eth0: PHY [c000f00.mdio:0a] driver [TI DP83TG720CS1.1] (irq=POLL)
[    9.455683] am65-cpsw-nuss c000000.ethernet eth0: configuring for phy/sgmii link mode
[    9.463530] am65_cpsw_nuss_mac_config writel addr 0x:e600118 value:9801
[    9.473220] am65-cpsw-nuss c000000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
[  OK  ] Started Network Name Resolution.
[  OK  ] Reached target Network.
[  OK  ] Reached target Host and Network Nam[    9.543753] FAT-fs (mmcblk1p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
e Lookups.
[    9.585287] EXT4-fs (mmcblk0p18): recovery complete
[    9.590231] EXT4-fs (mmcblk0p18): mounted filesystem with ordered data mode. Quota mode: none.
         Starting Permit User Sessions...
[  OK  ] Started D-Bus System Message Bus.
[  OK  ] Finished app-init.
[  OK  ] Finished Permit User Sessions.
[  OK  ] Started Getty on tty1.
[  OK  ] Started Serial Getty on ttyS0.
[  OK  ] Reached target Login Prompts.
[  OK  ] Started User Login Management.
[  OK  ] Reached target Multi-User System.
         Starting Record Runlevel Change in UTMP...
[  OK  ] Finished Record Runlevel Change in UTMP.

- other info 

when we add ethfw code for serdes config, all is ok  

static Board_Serdes_Config gBoardSerdesConfig[]=
{
    {
        .Serdes_Base = CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE,
        .Serdes_Ins = CSL_TORRENT_SERDES1,
        .Serdes_Lane_Count = 2,
        .Serdes_Lane_Num = 2,
        .Serdes_Select_CPSW = 0
    },
    {
        .Serdes_Base = CSL_WIZ16B8M4CT3_2_WIZ16B8M4CT3_BASE,
        .Serdes_Ins = CSL_TORRENT_SERDES2,
        .Serdes_Lane_Count = 1,
        .Serdes_Lane_Num = 0,
        .Serdes_Select_CPSW = 0
    }
};

static Board_STATUS Board_CfgSgmii()
{
    uint32_t i = 0;
    CSL_SerdesResult result;
    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
    CSL_SerdesLaneEnableParams serdesLaneEnableParams;
    
    for (i = 0; i < (sizeof(gBoardSerdesConfig)/sizeof(gBoardSerdesConfig[0U])); i++)
    {   
        uint32_t j = 0;
        uint32_t laneMask = 0;
        memset(&serdesLaneEnableParams, 0, sizeof(serdesLaneEnableParams));
        /* SGMII Config */
        serdesLaneEnableParams.serdesInstance    = gBoardSerdesConfig[i].Serdes_Ins;
        serdesLaneEnableParams.baseAddr          = gBoardSerdesConfig[i].Serdes_Base;
        serdesLaneEnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;
        serdesLaneEnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT0;
        serdesLaneEnableParams.linkRate          = CSL_SERDES_LINK_RATE_1p25G;
        serdesLaneEnableParams.numLanes          = CSL_SERDES_MAX_LANES;
        serdesLaneEnableParams.SSC_mode          = CSL_SERDES_NO_SSC;
        serdesLaneEnableParams.phyType           = CSL_SERDES_PHY_TYPE_SGMII;
        serdesLaneEnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;
        serdesLaneEnableParams.phyInstanceNum    = gBoardSerdesConfig[i].Serdes_Select_CPSW;
        serdesLaneEnableParams.pcieGenType       = CSL_SERDES_PCIE_GEN3;
        for (j =  gBoardSerdesConfig[i].Serdes_Lane_Num; j < gBoardSerdesConfig[i].Serdes_Lane_Num + gBoardSerdesConfig[i].Serdes_Lane_Count; j++)
        {
            serdesLaneEnableParams.laneCtrlRate[j] = CSL_SERDES_LANE_FULL_RATE;
            serdesLaneEnableParams.loopbackMode[j] = CSL_SERDES_LOOPBACK_DISABLED;
            laneMask |= (1<<j);
        }
        serdesLaneEnableParams.laneMask = laneMask;

        CSL_serdesPorReset(serdesLaneEnableParams.baseAddr);

        for (j =  gBoardSerdesConfig[i].Serdes_Lane_Num; j < gBoardSerdesConfig[i].Serdes_Lane_Num + gBoardSerdesConfig[i].Serdes_Lane_Count; j++)
        {
            /* Select the IP type, IP instance num, Serdes Lane Number */
            CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
                            serdesLaneEnableParams.phyType,
                            serdesLaneEnableParams.phyInstanceNum,
                            serdesLaneEnableParams.serdesInstance,
                            j);
        }

        result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
                                    serdesLaneEnableParams.baseAddr,
                                    serdesLaneEnableParams.refClock,
                                    serdesLaneEnableParams.refClkSrc,
                                    serdesLaneEnableParams.serdesInstance,
                                    serdesLaneEnableParams.phyType);

        if (result != CSL_SERDES_NO_ERR)
        {
            return BOARD_FAIL;
        }
        /* Assert PHY reset and disable all lanes */
        CSL_serdesDisablePllAndLanes(serdesLaneEnableParams.baseAddr,
                                    serdesLaneEnableParams.numLanes,
                                    serdesLaneEnableParams.laneMask);

        /* Load the Serdes Config File */
        result = CSL_serdesEthernetInit(&serdesLaneEnableParams);
        /* Return error if input params are invalid */
        if (result != CSL_SERDES_NO_ERR)
        {
            return BOARD_FAIL;
        }

        /* Common Lane Enable API for lane enable, pll enable etc */
        laneRetVal = CSL_serdesLaneEnable(&serdesLaneEnableParams);
        if (laneRetVal != 0)
        {
            return BOARD_FAIL;
        }
    }

    return BOARD_SOK;
}

  • Correction patch Code

    diff --git a/board-support/ti-linux-kernel-6.1.46+gitAUTOINC+5892b80d6b-g5892b80d6b/drivers/phy/ti/phy-gmii-sel.c b/board-support/ti-linux-kernel-6.1.46+gitAUTOINC+5892b80d6b-g5892b80d6b/drivers/phy/ti/phy-gmii-sel.c
    index bc847d387..f1409ba96 100644
    --- a/board-support/ti-linux-kernel-6.1.46+gitAUTOINC+5892b80d6b-g5892b80d6b/drivers/phy/ti/phy-gmii-sel.c
    +++ b/board-support/ti-linux-kernel-6.1.46+gitAUTOINC+5892b80d6b-g5892b80d6b/drivers/phy/ti/phy-gmii-sel.c
    @@ -249,7 +249,7 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
            .use_of_data = true,
            .regfields = phy_gmii_sel_fields_am654,
            .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) |
    -                      BIT(PHY_INTERFACE_MODE_USXGMII),
    +                          BIT(PHY_INTERFACE_MODE_USXGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
            .num_ports = 8,
            .num_qsgmii_main_ports = 2,
     };
    diff --git a/board-support/ti-linux-kernel-6.1.46+gitAUTOINC+5892b80d6b-g5892b80d6b/drivers/phy/ti/phy-j721e-wiz.c b/board-support/ti-linux-kernel-6.1.46+gitAUTOINC+5892b80d6b-g5892b80d6b/drivers/phy/ti/phy-j721e-wiz.c
    index 32cda3d34..1c577f38c 100644
    --- a/board-support/ti-linux-kernel-6.1.46+gitAUTOINC+5892b80d6b-g5892b80d6b/drivers/phy/ti/phy-j721e-wiz.c
    +++ b/board-support/ti-linux-kernel-6.1.46+gitAUTOINC+5892b80d6b-g5892b80d6b/drivers/phy/ti/phy-j721e-wiz.c
    @@ -1238,6 +1238,7 @@ static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
            case J721E_WIZ_10G:
            case J7200_WIZ_10G:
            case J721S2_WIZ_10G:
    +       case J784S4_WIZ_10G:
                    if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
                            return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
                    break;
                    
    diff --git a/board-support/ti-linux-kernel-6.1.46+gitAUTOINC+5892b80d6b-g5892b80d6b/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/board-support/ti-linu
    x-kernel-6.1.46+gitAUTOINC+5892b80d6b-g5892b80d6b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
    index df778857a..97ae5a556 100644
    --- a/board-support/ti-linux-kernel-6.1.46+gitAUTOINC+5892b80d6b-g5892b80d6b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
    +++ b/board-support/ti-linux-kernel-6.1.46+gitAUTOINC+5892b80d6b-g5892b80d6b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
    @@ -1562,9 +1562,10 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in
     
            if (common->pdata.extra_modes & BIT(state->interface)) {
                    if (state->interface == PHY_INTERFACE_MODE_SGMII) {
    -                       writel(ADVERTISE_SGMII,
    +                       writel(0x9801,
                                   port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG);
                            cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN);
    +                       printk("am65_cpsw_nuss_mac_config writel addr 0x:%x value:%x \n",port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG,0x9801);
                    } else {
                            cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN);
                    }
    @@ -2903,7 +2904,7 @@ static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = {
            .quirks = 0,
            .ale_dev_id = "am64-cpswxg",
            .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
    -       .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_USXGMII),
    +       .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_USXGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
     };

  • Hi,

    Can you read the value of the following registers:

    • 0x0507E000
    • 0x0502E000

    Can you also try with the following phy drivers:

    • // SPDX-License-Identifier: GPL-2.0-only
      /* Driver for the Texas Instruments DP83TG720 PHY
       * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
       */
      
      #include <linux/ethtool.h>
      #include <linux/etherdevice.h>
      #include <linux/kernel.h>
      #include <linux/mii.h>
      #include <linux/module.h>
      #include <linux/phy.h>
      #include <linux/netdevice.h>
      
      #define DP83TG720ES1_PHY_ID	0x2000a280
      #define DP83TG720ES2_PHY_ID	0x2000a281
      #define DP83TG720CS_1_0_PHY_ID	0x2000a283
      #define DP83TG720CS_1_1_PHY_ID	0x2000a284
      #define DP83720_DEVADDR		0x1f
      #define DP83720_DEVADDR_MMD1	0x1
      
      #define MII_DP83720_INT_STAT1	0x12
      #define MII_DP83720_INT_STAT2	0x13
      #define MII_DP83720_INT_STAT3	0x18
      #define MII_DP83720_RESET_CTRL	0x1f
      
      #define DP83720_HW_RESET	BIT(15)
      #define DP83720_SW_RESET	BIT(14)
      
      #define DP83720_STRAP		0x45d
      #define DP83720_SGMII_CTRL	0x608
      #define SGMII_CONFIG_VAL	0x027B
      
      /* INT_STAT1 bits */
      #define DP83720_ANEG_COMPLETE_INT_EN	BIT(2)
      #define DP83720_ESD_EVENT_INT_EN	BIT(3)
      #define DP83720_LINK_STAT_INT_EN	BIT(5)
      #define DP83720_ENERGY_DET_INT_EN	BIT(6)
      #define DP83720_LINK_QUAL_INT_EN	BIT(7)
      
      /* INT_STAT2 bits */
      #define DP83720_SLEEP_MODE_INT_EN	BIT(2)
      #define DP83720_OVERTEMP_INT_EN		BIT(3)
      #define DP83720_OVERVOLTAGE_INT_EN	BIT(6)
      #define DP83720_UNDERVOLTAGE_INT_EN	BIT(7)
      
      /* INT_STAT3 bits */
      #define DP83720_LPS_INT_EN	BIT(0)
      #define DP83720_WAKE_REQ_EN	BIT(1)
      #define DP83720_NO_FRAME_INT_EN	BIT(2)
      #define DP83720_POR_DONE_INT_EN	BIT(3)
      
      /* SGMII CTRL bits */
      #define DP83720_SGMII_AUTO_NEG_EN	BIT(0)
      #define DP83720_SGMII_EN		BIT(9)
      
      /* Strap bits */
      #define DP83720_MASTER_MODE	BIT(5)
      #define DP83720_RGMII_IS_EN	BIT(12)
      #define DP83720_SGMII_IS_EN	BIT(13)
      #define DP83720_RX_SHIFT_EN	BIT(14)
      #define DP83720_TX_SHIFT_EN	BIT(15)
      
      /* RGMII ID CTRL */
      #define DP83720_RGMII_ID_CTRL	0x602
      #define DP83720_RX_CLK_SHIFT	BIT(1)
      #define DP83720_TX_CLK_SHIFT	BIT(0)
      
      enum dp83720_chip_type {
      	DP83720_ES1,
      	DP83720_ES2,
      	DP83720_CS1,
      	DP83720_CS1_1,
      };
      
      struct dp83720_init_reg {
      	int reg;
      	int val;
      };
      
      static const struct dp83720_init_reg dp83720_es1_init[] = {
      	{0x182, 0x3000},
      	{0x56a, 0xfc5},
      	{0x510, 0x2d51},
      	{0x408, 0x400},
      	{0x409, 0x2b},
      	{0x509, 0x4c04},
      	{0x8a1, 0xbff},
      	{0x802, 0x422},
      	{0x853, 0x632},
      	{0x824, 0x15e0},
      	{0x86a, 0x106},
      	{0x852, 0x3261},
      	{0x851, 0x5141},
      	{0x852, 0x327a},
      	{0x851, 0x6652},
      	{0x405, 0x1a0},
      	{0x423, 0x2},
      	{0x422, 0x0},
      	{0x420, 0x5510},
      	{0x421, 0x4077},
      	{0x412, 0x10},
      	{0x40f, 0x10},
      	{0x85d, 0x6405},
      	{0x894, 0x5557},
      	{0x892, 0x1b0},
      	{0x877, 0x55},
      	{0x80b, 0x16},
      	{0x864, 0x1fd0},
      	{0x865, 0xa},
      };
      
      static const struct dp83720_init_reg dp83720_es2_master_init[] = {
      	{0x408, 0x580},
      	{0x409, 0x2a},
      	{0x8a1, 0xbff},
      	{0x802, 0x422},
      	{0x840, 0x4120},
      	{0x841, 0x6151},
      	{0x8a3, 0x24e9},
      	{0x800, 0x2090},
      	{0x864, 0x1fd0},
      	{0x865, 0x2},
      	{0x405, 0x6800},
      	{0x420, 0x3310},
      	{0x412, 0x10},
      	{0x40f, 0xe4ce},
      	{0x844, 0x3f10},
      	{0x8a0, 0x1e7},
      	{0x843, 0x327a},
      	{0x842, 0x6652},
      	{0x50b, 0x7e7c},
      	{0x56a, 0x7f41},
      	{0x56b, 0xffb4},
      	{0x813, 0x3fa0},
      	{0x88d, 0x3fa0},
      	{0x899, 0x3fa0},
      };
      
      static const struct dp83720_init_reg dp83720_es2_slave_init[] = {
      	{0x408, 0x580},
      	{0x409, 0x2a},
      	{0x8a1, 0xbff},
      	{0x802, 0x422},
      	{0x853, 0x632},
      	{0x824, 0x15e0},
      	{0x86a, 0x106},
      	{0x852, 0x327a},
      	{0x851, 0x6652},
      	{0x405, 0x6800},
      	{0x420, 0x3310},
      	{0x412, 0x10},
      	{0x40f, 0x10},
      	{0x85d, 0x6405},
      	{0x894, 0x5057},
      	{0x892, 0x1b0},
      	{0x877, 0x55},
      	{0x80b, 0x16},
      	{0x864, 0x1fd0},
      	{0x865, 0x2},
      	{0x50b, 0x7e7c},
      	{0x56a, 0x7f41},
      	{0x56c, 0xffb4},
      	{0x813, 0x3fa0},
      	{0x88d, 0x3fa0},
      	{0x899, 0x3fa0},
      };
      
      static const struct dp83720_init_reg dp83720_cs1_master_init[] = {
      	{0x408, 0x580},
      	{0x409, 0x2a},
      	{0x8a1, 0xbff},
      	{0x802, 0x422},
      	{0x864, 0x1fd0},
      	{0x865, 0x2},
      	{0x8a3, 0x24e9},
      	{0x800, 0x2090},
      	{0x840, 0x4120},
      	{0x841, 0x6151},
      	{0x8a0, 0x01e7},
      	{0x879, 0xe4ce},
      	{0x89f, 0x1},
      	{0x844, 0x3f10},
      	{0x843, 0x327a},
      	{0x842, 0x6652},
      	{0x8a8, 0xe080},
      	{0x8a9, 0x3f0},
      	{0x88d, 0x3fa0},
      	{0x889, 0x3fa0},
      	{0x50b, 0x7e7c},
      	{0x56a, 0x5f41},
      	{0x56b, 0xffb4},
      	{0x56c, 0xffb4},
      	{0x573, 0x1},
      };
      
      static const struct dp83720_init_reg dp83720_cs1_slave_init[] = {
      	{0x408, 0x580},
      	{0x409, 0x2a},
      	{0x8a1, 0xbff},
      	{0x802, 0x422},
      	{0x864, 0x1fd0},
      	{0x865, 0x2},
      	{0x853, 0x632},
      	{0x824, 0x15e0},
      	{0x86a, 0x106},
      	{0x894, 0x5057},
      	{0x85d, 0x6405},
      	{0x892, 0x1b0},
      	{0x852, 0x327a},
      	{0x851, 0x6652},
      	{0x877, 0x55},
      	{0x80b, 0x16},
      	{0x8a8, 0xe080},
      	{0x8a9, 0x3f0},
      	{0x88d, 0x3fa0},
      	{0x899, 0x3fa0},
      	{0x1f, 0x4000},
      	{0x56a, 0x5f41},
      	{0x56b, 0xffb4},
      	{0x56c, 0xffb4},
      	{0x573, 0x1},
      };
      
      static const struct dp83720_init_reg dp83720_cs1_1_master_init[] = {
      	{0x405, 0x5800},
      	{0x8ad, 0x3c51},
      	{0x894, 0x5df7},
      	{0x8a0, 0x9e7},
      	{0x8c0, 0x4000},
      	{0x814, 0x4800},
      	{0x80d, 0x2ebf},
      	{0x8c1, 0xb00},
      	{0x87d, 0x001},
      	{0x82e, 0x000},
      	{0x837, 0x0f4},
      	{0x8be, 0x200},
      	{0x8c5, 0x4000},
      	{0x8c7, 0x2000},
      	{0x8b3, 0x05a},
      	{0x8b4, 0x05a},
      	{0x8b0, 0x202},
      	{0x8b5, 0x0ea},
      	{0x8ba, 0x2828},
      	{0x8bb, 0x6828},
      	{0x8bc, 0x028},
      	{0x8bf, 0x000},
      	{0x8b1, 0x014},
      	{0x8b2, 0x008},
      	{0x8ec, 0x000},
      	{0x8c8, 0x003},
      	{0x8be, 0x201},
      	{0x18c, 0x001},
      };
      
      static const struct dp83720_init_reg dp83720_cs1_1_slave_init[] = {
      	{0x894, 0x5df7},
      	{0x56a, 0x5f40},
      	{0x405, 0x5800},
      	{0x8ad, 0x3c51},
      	{0x894, 0x5df7},
      	{0x8a0, 0x9e7},
      	{0x8c0, 0x4000},
      	{0x814, 0x4800},
      	{0x80d, 0x2ebf},
      	{0x8c1, 0xb00},
      	{0x87d, 0x001},
      	{0x82e, 0x000},
      	{0x837, 0x0f4},
      	{0x8be, 0x200},
      	{0x8c5, 0x4000},
      	{0x8c7, 0x2000},
      	{0x8b3, 0x05a},
      	{0x8b4, 0x05a},
      	{0x8b0, 0x202},
      	{0x8b5, 0x0ea},
      	{0x8ba, 0x2828},
      	{0x8bb, 0x6828},
      	{0x8bc, 0x028},
      	{0x8bf, 0x000},
      	{0x8b1, 0x014},
      	{0x8b2, 0x008},
      	{0x8ec, 0x000},
      	{0x8c8, 0x003},
      	{0x8be, 0x201},
      	{0x56a, 0x5f40},
      	{0x18c, 0x001},
      };
      
      struct dp83720_private {
      	int chip;
      	bool is_master;
      	bool is_rgmii;
      	bool is_sgmii;
      	bool rx_shift;
      	bool tx_shift;
      };
      
      #if 0
      static irqreturn_t dp83720_handle_interrupt(struct phy_device *phydev)
      {
      	int irq_status;
      
      	irq_status = phy_read(phydev, MII_DP83720_INT_STAT1);
      	if (irq_status < 0) {
      		phy_error(phydev);
      		return IRQ_NONE;
      	}
      	if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
      		goto trigger_machine;
      
      	irq_status = phy_read(phydev, MII_DP83720_INT_STAT2);
      	if (irq_status < 0) {
      		phy_error(phydev);
      		return IRQ_NONE;
      	}
      	if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
      		goto trigger_machine;
      
      	irq_status = phy_read(phydev, MII_DP83720_INT_STAT3);
      	if (irq_status < 0) {
      		phy_error(phydev);
      		return IRQ_NONE;
      	}
      	if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
      		goto trigger_machine;
      
      	return IRQ_NONE;
      
      trigger_machine:
      	phy_trigger_machine(phydev);
      
      	return IRQ_HANDLED;
      }
      #endif
      
      static int dp83720_config_intr(struct phy_device *phydev)
      {
      	int misr_status, ret;
      
      	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
      		misr_status = phy_read(phydev, MII_DP83720_INT_STAT1);
      		if (misr_status < 0)
      			return misr_status;
      
      		misr_status |= (DP83720_ANEG_COMPLETE_INT_EN |
      				DP83720_ESD_EVENT_INT_EN |
      				DP83720_LINK_STAT_INT_EN |
      				DP83720_ENERGY_DET_INT_EN |
      				DP83720_LINK_QUAL_INT_EN);
      
      		ret = phy_write(phydev, MII_DP83720_INT_STAT1, misr_status);
      		if (ret < 0)
      			return ret;
      
      		misr_status = phy_read(phydev, MII_DP83720_INT_STAT2);
      		if (misr_status < 0)
      			return misr_status;
      
      		misr_status |= (DP83720_SLEEP_MODE_INT_EN |
      				DP83720_OVERTEMP_INT_EN |
      				DP83720_OVERVOLTAGE_INT_EN |
      				DP83720_UNDERVOLTAGE_INT_EN);
      
      		ret = phy_write(phydev, MII_DP83720_INT_STAT2, misr_status);
      		if (ret < 0)
      			return ret;
      
      		misr_status = phy_read(phydev, MII_DP83720_INT_STAT3);
      		if (misr_status < 0)
      			return misr_status;
      
      		misr_status |= (DP83720_LPS_INT_EN |
      				DP83720_WAKE_REQ_EN |
      				DP83720_NO_FRAME_INT_EN |
      				DP83720_POR_DONE_INT_EN);
      
      		ret = phy_write(phydev, MII_DP83720_INT_STAT3, misr_status);
      
      	} else {
      		ret = phy_write(phydev, MII_DP83720_INT_STAT1, 0);
      		if (ret < 0)
      			return ret;
      
      		ret = phy_write(phydev, MII_DP83720_INT_STAT2, 0);
      		if (ret < 0)
      			return ret;
      
      		ret = phy_write(phydev, MII_DP83720_INT_STAT3, 0);
      		if (ret < 0)
      			return ret;
      
      		ret = phy_read(phydev, MII_DP83720_INT_STAT1);
      		if (ret < 0)
      			return ret;
      
      		ret = phy_read(phydev, MII_DP83720_INT_STAT2);
      		if (ret < 0)
      			return ret;
      
      		ret = phy_read(phydev, MII_DP83720_INT_STAT3);
      		if (ret < 0)
      			return ret;
      
      		ret = 0;
      
      	}
      
      	return ret;
      }
      
      static int dp83720_config_aneg(struct phy_device *phydev)
      {
      	int value, ret;
      
      	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
      		value = phy_read(phydev, DP83720_SGMII_CTRL);
      		ret = phy_write_mmd(phydev, DP83720_DEVADDR, DP83720_SGMII_CTRL,
      				SGMII_CONFIG_VAL);
      		if (ret < 0)
      			return ret;
      	}
      
      	return genphy_config_aneg(phydev);
      }
      
      static int dp83720_read_straps(struct phy_device *phydev)
      {
      	struct dp83720_private *dp83720 = phydev->priv;
      	int strap;
      
      	strap = phy_read_mmd(phydev, DP83720_DEVADDR, DP83720_STRAP);
      	if (strap < 0)
      		return strap;
      
      	if (strap & DP83720_MASTER_MODE)
      		dp83720->is_master = true;
      
      	if (strap & DP83720_RGMII_IS_EN)
      		dp83720->is_rgmii = true;
      
      	if (strap & DP83720_SGMII_IS_EN)
      		dp83720->is_sgmii = true;
      
      	if (strap & DP83720_RX_SHIFT_EN)
      		dp83720->rx_shift = true;
      
      	if (strap & DP83720_TX_SHIFT_EN)
      		dp83720->tx_shift = true;
      
      	return 0;
      };
      
      static int dp83720_reset(struct phy_device *phydev, bool hw_reset)
      {
      	int ret;
      
      	if (hw_reset)
      		ret = phy_write_mmd(phydev, DP83720_DEVADDR, MII_DP83720_RESET_CTRL,
      				DP83720_HW_RESET);
      	else
      		ret = phy_write_mmd(phydev, DP83720_DEVADDR, MII_DP83720_RESET_CTRL,
      				DP83720_SW_RESET);
      	if (ret)
      		return ret;
      
      	mdelay(100);
      
      	return 0;
      }
      
      static int dp83720_phy_reset(struct phy_device *phydev)
      {
      	int ret;
      
      	ret = dp83720_reset(phydev, false);
      	if (ret)
      		return ret;
      
      	ret = dp83720_read_straps(phydev);
      	if (ret)
      		return ret;
      
      	return 0;
      }
      
      static int dp83720_write_seq(struct phy_device *phydev,
      			     const struct dp83720_init_reg *init_data, int size)
      {
      	int ret;
      	int i;
      
      	for (i = 0; i < size; i++) {
      			ret = phy_write_mmd(phydev, DP83720_DEVADDR, init_data[i].reg,
      				init_data[i].val);
      			if (ret)
      					return ret;
      	}
      
      	return 0;
      }
      
      static int dp83720_chip_init(struct phy_device *phydev)
      {
      	struct dp83720_private *dp83720 = phydev->priv;
      	int ret;
      
      	ret = dp83720_reset(phydev, true);
      	if (ret)
      		return ret;
      	
      	phydev->autoneg = AUTONEG_DISABLE;
          phydev->speed = SPEED_1000;
      	phydev->duplex = DUPLEX_FULL;
          linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
                                    phydev->supported);
      
      
      	if (dp83720->chip == DP83720_CS1 && dp83720->is_master) {
      		ret = phy_write_mmd(phydev, DP83720_DEVADDR, MII_BMSR, 0x940);
      		if (ret)
      			return ret;
      
      		ret = phy_write_mmd(phydev, DP83720_DEVADDR, MII_BMSR, 0x140);
      		if (ret)
      			return ret;
      	}
      
      	if (dp83720->is_master)
      	        ret = phy_write_mmd(phydev, DP83720_DEVADDR_MMD1, 0x834,
      				0xc001);
      	else
      	        ret = phy_write_mmd(phydev, DP83720_DEVADDR_MMD1, 0x834,
      				0x8001);
      	if (ret)
      		return ret;
      
      	switch (dp83720->chip) {
      	case DP83720_ES1:
      		ret = dp83720_write_seq(phydev, dp83720_es1_init,
      					ARRAY_SIZE(dp83720_es1_init));
      		break;
      	case DP83720_ES2:
      		if (dp83720->is_master)
      			ret = dp83720_write_seq(phydev, dp83720_es2_master_init,
      						ARRAY_SIZE(dp83720_es2_master_init));
      		else
      			ret = dp83720_write_seq(phydev, dp83720_es2_slave_init,
      						ARRAY_SIZE(dp83720_es2_slave_init));
      		break;
      	case DP83720_CS1:
      		ret = phy_write_mmd(phydev, DP83720_DEVADDR, 0x573, 0x101);
      		if (ret)
      			return ret;
      
      		if (dp83720->is_master)
      			ret = dp83720_write_seq(phydev, dp83720_cs1_master_init,
      						ARRAY_SIZE(dp83720_cs1_master_init));
      		else
      			ret = dp83720_write_seq(phydev, dp83720_cs1_slave_init,
      						ARRAY_SIZE(dp83720_cs1_slave_init));
      		break;
      	case DP83720_CS1_1:
      		ret = phy_write_mmd(phydev, DP83720_DEVADDR, 0x573, 0x101);
      		if (ret)
      			return ret;
      
      		if (dp83720->is_master)
      			ret = dp83720_write_seq(phydev, dp83720_cs1_1_master_init,
      						ARRAY_SIZE(dp83720_cs1_1_master_init));
      		else
      			ret = dp83720_write_seq(phydev, dp83720_cs1_1_slave_init,
      						ARRAY_SIZE(dp83720_cs1_1_slave_init));
      
      		ret = dp83720_reset(phydev, false);
      
      		ret = phy_write_mmd(phydev, DP83720_DEVADDR, 0x573, 0x001);
      	        if (ret)
      	                return ret;
      
      		return phy_write_mmd(phydev, DP83720_DEVADDR, 0x56a, 0x5f41);
      	default:
      		return -EINVAL;
      	};
      
      	if (ret)
      		return ret;
      
      	/* Enable the PHY */
      	ret = phy_write_mmd(phydev, DP83720_DEVADDR, 0x18c, 0x1);
      	if (ret)
      		return ret;
      
      	mdelay(10);
      
      	/* Do a software reset to restart the PHY with the updated values */
      	return dp83720_reset(phydev, false);
      }
      
      static int dp83720_config_init(struct phy_device *phydev)
      {
      	struct device *dev = &phydev->mdio.dev;
      	s32 rx_int_delay;
      	s32 tx_int_delay;
      	int rgmii_delay;
      	int value, ret;
      
      	ret = dp83720_chip_init(phydev);
      	if (ret)
      		return ret;
      
      	if (phy_interface_is_rgmii(phydev)) {
      		rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
      						      true);
      
      		if (rx_int_delay <= 0)
      			rgmii_delay = 0;
      		else
      			rgmii_delay = DP83720_RX_CLK_SHIFT;
      
      		tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
      						      false);
      		if (tx_int_delay <= 0)
      			rgmii_delay &= ~DP83720_TX_CLK_SHIFT;
      		else
      			rgmii_delay |= DP83720_TX_CLK_SHIFT;
      
      		if (rgmii_delay) {
      			ret = phy_set_bits_mmd(phydev, DP83720_DEVADDR_MMD1,
      					       DP83720_RGMII_ID_CTRL,
      					       rgmii_delay);
      			if (ret)
      				return ret;
      		}
      	}
      
      	value = phy_read_mmd(phydev, DP83720_DEVADDR, DP83720_SGMII_CTRL);
      	if (value < 0)
      		return value;
      
      	if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
      		value |= DP83720_SGMII_EN;
      	else
      		value &= ~DP83720_SGMII_EN;
      
      	ret = phy_write_mmd(phydev, DP83720_DEVADDR, DP83720_SGMII_CTRL, value);
      	if (ret < 0)
      		return ret;
      
      	return 0;
      }
      
      static int dp83720_probe(struct phy_device *phydev)
      {
      	struct dp83720_private *dp83720;
      	int ret;
      
      	dp83720 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83720),
      			       GFP_KERNEL);
      	if (!dp83720)
      		return -ENOMEM;
      
      	phydev->priv = dp83720;
      
      	ret = dp83720_read_straps(phydev);
      	if (ret)
      		return ret;
      
      	switch (phydev->phy_id) {
      	case DP83TG720ES1_PHY_ID:
      		dp83720->chip = DP83720_ES1;
      		break;
      	case DP83TG720ES2_PHY_ID:
      		dp83720->chip = DP83720_ES2;
      		break;
      	case DP83TG720CS_1_0_PHY_ID:
      		dp83720->chip = DP83720_CS1;
      		break;
      	case DP83TG720CS_1_1_PHY_ID:
      		dp83720->chip = DP83720_CS1_1;
      		break;
      	default:
      		return -EINVAL;
      	};
      
      	return dp83720_config_init(phydev);
      }
      
      #define DP83720_PHY_DRIVER(_id, _name)				\
      	{							\
      		PHY_ID_MATCH_EXACT(_id),			\
      		.name		= (_name),			\
      		.probe          = dp83720_probe,		\
      		/* PHY_GBIT_FEATURES */				\
      		.soft_reset	= dp83720_phy_reset,		\
      		.config_init	= dp83720_config_init,		\
      		.config_aneg = dp83720_config_aneg,		\
      /*if 0								\
      		.handle_interrupt = dp83720_handle_interrupt,	\
      #endif	*/							\
      		.config_intr = dp83720_config_intr,		\
      		.suspend = genphy_suspend,			\
      		.resume = genphy_resume,			\
      	}
      
      static struct phy_driver dp83720_driver[] = {
      	DP83720_PHY_DRIVER(DP83TG720ES1_PHY_ID, "TI DP83TG720ES1"),
      	DP83720_PHY_DRIVER(DP83TG720ES2_PHY_ID, "TI DP83TG720ES2"),
      	DP83720_PHY_DRIVER(DP83TG720CS_1_0_PHY_ID, "TI DP83TG720CS1.0"),
      	DP83720_PHY_DRIVER(DP83TG720CS_1_1_PHY_ID, "TI DP83TG720CS1.1"),
      };
      module_phy_driver(dp83720_driver);
      
      static struct mdio_device_id __maybe_unused dp83720_tbl[] = {
      	{ PHY_ID_MATCH_EXACT(DP83TG720ES1_PHY_ID) },
      	{ PHY_ID_MATCH_EXACT(DP83TG720ES2_PHY_ID) },
      	{ PHY_ID_MATCH_EXACT(DP83TG720CS_1_0_PHY_ID) },
      	{ PHY_ID_MATCH_EXACT(DP83TG720CS_1_1_PHY_ID) },
      	{ },
      };
      MODULE_DEVICE_TABLE(mdio, dp83720_tbl);
      
      MODULE_DESCRIPTION("Texas Instruments DP83TG720 PHY driver");
      MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
      MODULE_LICENSE("GPL");
      
    • // SPDX-License-Identifier: GPL-2.0
      /*
       * Driver for the Texas Instruments DP83TC812 PHY
       *
       * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
       *
       */
      
      #include <linux/ethtool.h>
      #include <linux/etherdevice.h>
      #include <linux/kernel.h>
      #include <linux/mii.h>
      #include <linux/module.h>
      #include <linux/of.h>
      #include <linux/phy.h>
      #include <linux/netdevice.h>
      
      #define DP83TC812_CS1_0_PHY_ID	0x2000a270
      #define DP83TC812_CS2_0_PHY_ID	0x2000a271
      #define DP83TC813_CS2_0_PHY_ID	0x2000a211
      #define DP83TC814_CS2_0_PHY_ID	0x2000a261
      
      #define DP83812_DEVADDR		0x1f
      #define DP83812_DEVADDR_MMD1	0x1
      
      #define DP83812_STRAP		0x45d
      #define MII_DP83812_SGMII_CTRL	0x608
      #define MII_DP83812_RGMII_CTRL	0x600
      #define MII_DP83812_INT_STAT1	0x12
      #define MII_DP83812_INT_STAT2	0x13
      #define MII_DP83812_INT_STAT3	0x18
      #define MII_DP83812_RESET_CTRL	0x1f
      
      #define DP83812_HW_RESET	BIT(15)
      #define DP83812_SW_RESET	BIT(14)
      
      /* INT_STAT1 bits */
      #define DP83812_RX_ERR_CNT_HALF_FULL_INT_EN	BIT(0)
      #define DP83812_TX_ERR_CNT_HALF_FULL_INT_EN	BIT(1)
      #define DP83812_MS_TRAIN_DONE_INT_EN		BIT(2)
      #define DP83812_ESD_EVENT_INT_EN		BIT(3)
      #define DP83812_LINK_STAT_INT_EN		BIT(5)
      #define DP83812_ENERGY_DET_INT_EN		BIT(6)
      #define DP83812_LINK_QUAL_INT_EN		BIT(7)
      
      /* INT_STAT2 bits */
      #define DP83812_JABBER_INT_EN		BIT(0)
      #define DP83812_POL_INT_EN		BIT(1)
      #define DP83812_SLEEP_MODE_INT_EN	BIT(2)
      #define DP83812_OVERTEMP_INT_EN		BIT(3)
      #define DP83812_FIFO_INT_EN		BIT(4)
      #define DP83812_PAGE_RXD_INT_EN		BIT(5)
      #define DP83812_OVERVOLTAGE_INT_EN	BIT(6)
      #define DP83812_UNDERVOLTAGE_INT_EN	BIT(7)
      
      /* INT_STAT3 bits */
      #define DP83812_LPS_INT_EN		BIT(0)
      #define DP83812_WUP_INT_EN		BIT(1)
      #define DP83812_WAKE_REQ_INT_EN		BIT(2)
      #define DP83811_NO_FRAME_INT_EN		BIT(3)
      #define DP83811_POR_DONE_INT_EN		BIT(4)
      #define DP83812_SLEEP_FAIL_INT_EN	BIT(5)
      
      /* RGMII_CTRL bits */
      #define DP83812_RGMII_EN		BIT(3)
      
      /* SGMII CTRL bits */
      #define DP83812_SGMII_AUTO_NEG_EN	BIT(0)
      #define DP83812_SGMII_EN		BIT(9)
      
      /* Strap bits */
      #define DP83812_MASTER_MODE	BIT(9)
      #define DP83812_RGMII_IS_EN	BIT(7)
      
      enum dp83812_chip_type {
      	DP83812_CS1 = 0,
      	DP83812_CS2,
      	DP83813_CS2,
      	DP83814_CS2,
      };
      
      struct dp83812_init_reg {
      	int	reg;
      	int	val;
      };
      
      static const struct dp83812_init_reg dp83812_master_cs1_0_init[] = {
      	{0x523, 0x0001},
      	{0x800, 0xf864},
      	{0x803, 0x1552},
      	{0x804, 0x1a66},
      	{0x805, 0x1f7b},
      	{0x81f, 0x2a88},
      	{0x825, 0x40e5},
      	{0x82b, 0x7f3f},
      	{0x830, 0x0543},
      	{0x836, 0x5008},
      	{0x83a, 0x08e0},
      	{0x83b, 0x0845},
      	{0x83e, 0x0445},
      	{0x855, 0x9b9a},
      	{0x85f, 0x2010},
      	{0x860, 0x6040},
      	{0x86c, 0x1333},
      	{0x86b, 0x3e10},
      	{0x872, 0x88c0},
      	{0x873, 0x0003},
      	{0x879, 0x000f},
      	{0x87b, 0x0070},
      	{0x87c, 0x003f},
      	{0x89e, 0x00aa},
      	{0x523, 0x0000},
      };
      
      static const struct dp83812_init_reg dp83812_master_cs2_0_init[] = {
      	{0x523, 0x0001},
      	{0x81C, 0x0fe2},
      	{0x872, 0x0300},
      	{0x879, 0x0f00},
      	{0x806, 0x2952},
      	{0x807, 0x3361},
      	{0x808, 0x3D7B},
      	{0x83E, 0x045F},
      	{0x834, 0x8000},
      	{0x862, 0x00E8},
      	{0x896, 0x32CB},
      	{0x03E, 0x0009},
      	{0x01f, 0x4000},
      	{0x523, 0x0000},
      };
      
      static const struct dp83812_init_reg dp83812_slave_cs1_0_init[] = {
      	{0x523, 0x0001},
      	{0x803, 0x1b52},
      	{0x804, 0x216c},
      	{0x805, 0x277b},
      	{0x827, 0x3000},
      	{0x830, 0x0543},
      	{0x83a, 0x0020},
      	{0x83c, 0x0001},
      	{0x855, 0x9b9a},
      	{0x85f, 0x2010},
      	{0x860, 0x6040},
      	{0x86c, 0x0333},
      	{0x872, 0x88c0},
      	{0x873, 0x0021},
      	{0x879, 0x000f},
      	{0x87b, 0x0070},
      	{0x87c, 0x0002},
      	{0x897, 0x003f},
      	{0x89e, 0x00a2},
      	{0x510, 0x000f},
      	{0x523, 0x0000},
      };
      
      static const struct dp83812_init_reg dp83812_slave_cs2_0_init[] = {
      	{0x523, 0x0001},
      	{0x873, 0x0821},
      	{0x896, 0x22ff},
      	{0x89E, 0x0000},
      	{0x01f, 0x4000},
      	{0x523, 0x0000},
      };
      
      struct dp83812_private {
      	int chip;
      	bool is_master;
      	bool is_rgmii;
      	bool is_sgmii;
      };
      
      static int dp83812_read_straps(struct phy_device *phydev)
      {
      	struct dp83812_private *dp83812 = phydev->priv;
      	int strap;
      
      	strap = phy_read_mmd(phydev, DP83812_DEVADDR, DP83812_STRAP);
      	if (strap < 0)
      		return strap;
      
      	printk("%s: Strap is 0x%X\n", __func__, strap);
      	if (strap & DP83812_MASTER_MODE)
      		dp83812->is_master = true;
      
      	if (strap & DP83812_RGMII_IS_EN)
      		dp83812->is_rgmii = true;
      	return 0;
      };
      
      static int dp83812_reset(struct phy_device *phydev, bool hw_reset)
      {
      	int ret;
      
      	if (hw_reset)
      		ret = phy_write_mmd(phydev, DP83812_DEVADDR, MII_DP83812_RESET_CTRL,
      				DP83812_HW_RESET);
      	else
      		ret = phy_write_mmd(phydev, DP83812_DEVADDR, MII_DP83812_RESET_CTRL,
      				DP83812_SW_RESET);
      
      	if (ret)
      		return ret;
      
      	mdelay(100);
      
      	return 0;
      }
      
      static int dp83812_phy_reset(struct phy_device *phydev)
      {
      	int err;
      	int ret;
      
      	err = phy_write_mmd(phydev, DP83812_DEVADDR, MII_DP83812_RESET_CTRL, DP83812_HW_RESET);
      	if (err < 0)
      		return err;
      
      	ret = dp83812_read_straps(phydev);
      	if (ret)
      		return ret;
      
      	return 0;
      }
      
      static int dp83812_write_seq(struct phy_device *phydev, const struct
      				dp83812_init_reg *init_data, int size)
      {
      	int ret;
      	int i;
      
      	for (i = 0; i < size; i++) {
      		ret = phy_write_mmd(phydev, DP83812_DEVADDR, init_data[i].reg,
      					init_data[i].val);
      	if (ret)
      		return ret;
      	}
      	return 0;
      }
      
      static int dp83812_chip_init(struct phy_device *phydev)
      {
      	struct dp83812_private *dp83812 = phydev->priv;
      	int ret;
      
      	ret = dp83812_reset(phydev, true);
      	if (ret)
      		return ret;
      
      	phydev->autoneg = AUTONEG_DISABLE;
      	phydev->speed = SPEED_100;
      	phydev->duplex = DUPLEX_FULL;
      	linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
      		 phydev->supported);
      
      	if (dp83812->is_master)
      		ret = phy_write_mmd(phydev, DP83812_DEVADDR_MMD1, 0x0834, 0xc001);
      		// ret = phy_write_mmd(phydev, DP83812_DEVADDR, 0x0834, 0xc001);
      	else
      		ret = phy_write_mmd(phydev, DP83812_DEVADDR_MMD1, 0x0834, 0x8001);
      		// ret = phy_write_mmd(phydev, DP83812_DEVADDR, 0x0834, 0x8001);
      
      	switch (dp83812->chip) {
      	case DP83812_CS1:
      		if (dp83812->is_master)
      			ret = dp83812_write_seq(phydev,
      						dp83812_master_cs1_0_init,
      						ARRAY_SIZE(dp83812_master_cs1_0_init));
      		else
      			ret = dp83812_write_seq(phydev,
      						dp83812_slave_cs1_0_init,
      						ARRAY_SIZE(dp83812_slave_cs1_0_init));
      	break;
      	case DP83812_CS2:
      		if (dp83812->is_master)
      			ret = dp83812_write_seq(phydev,
      						dp83812_master_cs2_0_init,
      						ARRAY_SIZE(dp83812_master_cs2_0_init));
      		else
      			ret = dp83812_write_seq(phydev,
      						dp83812_slave_cs2_0_init,
      						ARRAY_SIZE(dp83812_slave_cs2_0_init));
      	break;
      	case DP83813_CS2:
      		if (dp83812->is_master)
      			ret = dp83812_write_seq(phydev,
      						dp83812_master_cs2_0_init,
      						ARRAY_SIZE(dp83812_master_cs2_0_init));
      		else
      			ret = dp83812_write_seq(phydev,
      						dp83812_slave_cs2_0_init,
      						ARRAY_SIZE(dp83812_slave_cs2_0_init));
      	break;
      	case DP83814_CS2:
      		if (dp83812->is_master)
      			ret = dp83812_write_seq(phydev,
      						dp83812_master_cs2_0_init,
      						ARRAY_SIZE(dp83812_master_cs2_0_init));
      		else
      			ret = dp83812_write_seq(phydev,
      						dp83812_slave_cs2_0_init,
      						ARRAY_SIZE(dp83812_slave_cs2_0_init));
      	break;
      	default:
      		return -EINVAL;
      	};
      
      	if (ret)
      		return ret;
      
      	mdelay(10);
      	// phy_write_mmd(phydev, DP83812_DEVADDR, 0x523, 0x00);
      	/* Do a soft reset to restart the PHY with updated values */
      	return dp83812_reset(phydev, false);
      }
      
      static int dp83812_config_init(struct phy_device *phydev)
      {
      	int value, err;
      
      	err = dp83812_chip_init(phydev);
      	if (err)
      		return err;
      
      	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
      		value = phy_read(phydev, MII_DP83812_SGMII_CTRL);
      		ret = phy_write_mmd(phydev, DP83812_DEVADDR, MII_DP83812_SGMII_CTRL,
      				SGMII_CONFIG_VAL);
      		if (ret < 0)
      			return ret;
      	}
      
      	if (err < 0)
      
      		return err;
      
      	return 0;
      }
      
      static int dp83812_ack_interrupt(struct phy_device *phydev)
      {
      	int err;
      
      	err = phy_read(phydev, MII_DP83812_INT_STAT1);
      	if (err < 0)
      		return err;
      
      	err = phy_read(phydev, MII_DP83812_INT_STAT2);
      	if (err < 0)
      		return err;
      
      	err = phy_read(phydev, MII_DP83812_INT_STAT3);
      	if (err < 0)
      		return err;
      
      	return 0;
      }
      
      static int dp83812_config_intr(struct phy_device *phydev)
      {
      	int misr_status, err;
      
      	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
      		misr_status = phy_read(phydev, MII_DP83812_INT_STAT1);
      		if (misr_status < 0)
      			return misr_status;
      
      		misr_status |= (DP83812_ESD_EVENT_INT_EN |
      				DP83812_LINK_STAT_INT_EN |
      				DP83812_ENERGY_DET_INT_EN |
      				DP83812_LINK_QUAL_INT_EN);
      
      		err = phy_write(phydev, MII_DP83812_INT_STAT1, misr_status);
      		if (err < 0)
      			return err;
      
      		misr_status = phy_read(phydev, MII_DP83812_INT_STAT2);
      		if (misr_status < 0)
      			return misr_status;
      
      		misr_status |= (DP83812_SLEEP_MODE_INT_EN |
      				DP83812_OVERTEMP_INT_EN |
      				DP83812_OVERVOLTAGE_INT_EN |
      				DP83812_UNDERVOLTAGE_INT_EN);
      
      		err = phy_write(phydev, MII_DP83812_INT_STAT2, misr_status);
      		if (err < 0)
      			return err;
      
      		misr_status = phy_read(phydev, MII_DP83812_INT_STAT3);
      		if (misr_status < 0)
      			return misr_status;
      
      		misr_status |= (DP83812_LPS_INT_EN |
      				DP83812_WAKE_REQ_INT_EN |
      				DP83811_NO_FRAME_INT_EN |
      				DP83811_POR_DONE_INT_EN);
      
      		err = phy_write(phydev, MII_DP83812_INT_STAT3, misr_status);
      
      	} else {
      		err = phy_write(phydev, MII_DP83812_INT_STAT1, 0);
      		if (err < 0)
      			return err;
      
      		err = phy_write(phydev, MII_DP83812_INT_STAT2, 0);
      		if (err < 0)
      			return err;
      
      		err = phy_write(phydev, MII_DP83812_INT_STAT3, 0);
      	}
      
      	return err;
      }
      
      #if 0
      static irqreturn_t dp83812_handle_interrupt(struct phy_device *phydev)
      {
      	bool trigger_machine = false;
      	int irq_status;
      
      	/* The INT_STAT registers 1, 2 and 3 are holding the interrupt status
      	 * in the upper half (15:8), while the lower half (7:0) is used for
      	 * controlling the interrupt enable state of those individual interrupt
      	 * sources. To determine the possible interrupt sources, just read the
      	 * INT_STAT* register and use it directly to know which interrupts have
      	 * been enabled previously or not.
      	 */
      	irq_status = phy_read(phydev, MII_DP83812_INT_STAT1);
      	if (irq_status < 0) {
      		phy_error(phydev);
      		return IRQ_NONE;
      	}
      	if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
      		trigger_machine = true;
      
      	irq_status = phy_read(phydev, MII_DP83812_INT_STAT2);
      	if (irq_status < 0) {
      		phy_error(phydev);
      		return IRQ_NONE;
      	}
      	if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
      		trigger_machine = true;
      
      	irq_status = phy_read(phydev, MII_DP83812_INT_STAT3);
      	if (irq_status < 0) {
      		phy_error(phydev);
      		return IRQ_NONE;
      	}
      	if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
      		trigger_machine = true;
      
      	if (!trigger_machine)
      		return IRQ_NONE;
      
      	phy_trigger_machine(phydev);
      
      	return IRQ_HANDLED;
      }
      #endif
      
      static int dp83812_config_aneg(struct phy_device *phydev)
      {
      	int value, err;
      
      	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
      		value = phy_read(phydev, MII_DP83812_SGMII_CTRL);
      		ret = phy_write_mmd(phydev, DP83812_DEVADDR, MII_DP83812_SGMII_CTRL,
      				SGMII_CONFIG_VAL);
      		if (ret < 0)
      			return ret;
      	}
      	
      	return genphy_config_aneg(phydev);
      }
      
      
      
      static int dp83812_probe(struct phy_device *phydev)
      {
      	struct dp83812_private *dp83812;
      	int ret;
      
      	dp83812 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83812), GFP_KERNEL);
      	if (!dp83812)
      		return -ENOMEM;
      
      	phydev->priv = dp83812;					
      	ret = dp83812_read_straps(phydev);
      	if (ret)
      		return ret;
      
      	switch (phydev->phy_id) {
      	case DP83TC812_CS1_0_PHY_ID:
      		dp83812->chip = DP83812_CS1;
      	break;
      	case DP83TC812_CS2_0_PHY_ID:
      		dp83812->chip = DP83812_CS2;
      	break;
      	case DP83TC813_CS2_0_PHY_ID:
      		dp83812->chip = DP83813_CS2;
      		break;
      	case DP83TC814_CS2_0_PHY_ID:
      		dp83812->chip = DP83814_CS2;
      	break;
      	default:
      	return -EINVAL;
      	};
      /* vikram : above code added to switch between different phy ids */
      
      	return dp83812_config_init(phydev);
      }
      
      #define DP83812_PHY_DRIVER(_id, _name)				\
      	{							\
      		PHY_ID_MATCH_EXACT(_id),			\
      		.name           = (_name),			\
      		.probe          = dp83812_probe,		\
      		/* PHY_BASIC_FEATURES */			\
      		.soft_reset     = dp83812_phy_reset,		\
      		.config_init    = dp83812_config_init,		\
      		.config_aneg = dp83812_config_aneg,		\
      		.ack_interrupt = dp83812_ack_interrupt,		\
      /*if 0								\
      		.handle_interrupt = dp83812_handle_interrupt,	\
      #endif	*/							\
      		.config_intr = dp83812_config_intr,		\
      		.suspend = genphy_suspend,			\
      		.resume = genphy_resume,			\
      	}
      
      static struct phy_driver dp83812_driver[] = {
      	DP83812_PHY_DRIVER(DP83TC812_CS1_0_PHY_ID, "TI DP83TC812CS1.0"),
      	DP83812_PHY_DRIVER(DP83TC812_CS2_0_PHY_ID, "TI DP83TC812CS2.0"),
      	DP83812_PHY_DRIVER(DP83TC813_CS2_0_PHY_ID, "TI DP83TC813CS2.0"),
      	DP83812_PHY_DRIVER(DP83TC814_CS2_0_PHY_ID, "TI DP83TC814CS2.0"),
      	};
      
      module_phy_driver(dp83812_driver);
      
      static struct mdio_device_id __maybe_unused dp83812_tbl[] = {
      	{ PHY_ID_MATCH_EXACT(DP83TC812_CS1_0_PHY_ID) },
      	{ PHY_ID_MATCH_EXACT(DP83TC812_CS2_0_PHY_ID) },
      	{ PHY_ID_MATCH_EXACT(DP83TC813_CS2_0_PHY_ID) },
      	{ PHY_ID_MATCH_EXACT(DP83TC814_CS2_0_PHY_ID) },
      	{ },
      };
      MODULE_DEVICE_TABLE(mdio, dp83812_tbl);									   
      
      MODULE_DESCRIPTION("Texas Instruments DP83TC812 PHY driver");
      MODULE_AUTHOR("Hari Nagalla <hnagalla@ti.com");
      MODULE_LICENSE("GPL");

    Regards,
    Tanmay

  • Hi,

    the dump reg also in  - regster dump tag 

     

  • HI 

      After updating the above drivers, all three network cards work normally.

      my driver comes from TI's github: https://github.com/TexasInstruments/ti-ethernet-software/tree/main/linux_drivers

      so I have never suspected that it is a driver problem. Can TI synchronize the information internally and update the correct driver to github?

      

       Thanks for your help Handshake tone1

  • Hi,

    I will take this action. Thanks for the confirmation.

    Regards,
    Tanmay