AM69: AM69: Limitations of MIPI-DSI and expected improvements

Hi Parth,

Issue is mainly with the DSI to eDP bridge not being able to process EDID from some displays properly. To work around this issue, we have fixed resolution of 800x600.

Fix for this may take a while as we have a couple of backlogs relating to display. However, we will update you with the latest status as they come.

Regards,

Takuma

Hello Takuma Fujiwara,

Thank you for response.

Takuma Fujiwara said:

Issue is mainly with the DSI to eDP bridge not being able to process EDID from some displays properly. To work around this issue, we have fixed resolution of 800x600.

As I have listed above, the issue is not only in processing EDID, there is more to it.
I have observed that DSI0 does not work at all in 4 lanes configuration, even with fixed resolution 800x600.
In addition, there's some dependencies on sync pules for DSI0 to work. It does not work with DRM_MODE_FLAG_PVSYNC and DRM_MODE_FLAG_PVSYNC mode flags. Not all MIPI DSI modes are supported.
The workaround in base TI SW is not only for fixed resolution EDID but to hard code the lanes and mode flags for DSI0.

For our hardware echo system, we have two bridges connected to AM69 DSI0 - LT8912B for HDMI and SN65DSI84 for LVDS designed with 4 lane DSI. Because of the same reasons, we would need AM69 DSI0 to work fully as per the MIPI standards - for all the resolutions, with 4 lanes dsi configs and for all supported DSI modes like sync pule, sync event and burst.

Could you please help provide any approximate timelines of the ETA for the fixes ? This would help us in our internal planning.

Thank you.

Regards,

Parth P

Hi Parth,

For issue tracking, we have next release (which we plan to be mid-August) to be the target for a fix. However, I have some doubts for this date, so I sent our team a query to see if we are still on track, or we will delay to next next release.

Regards,

Takuma

Hi Parth, 

Unlocking the thread. Apologies for my previous statement as I had a lot of misunderstanding, but the issue we are tracking is for EDID issue and not for all of the issues you were mentioning in your initial post. 

In terms of support for burst mode and positive sync modes, I'll check with our internal development team to see if we can provide a timeline, but please expect a considerable amount of time (at the minimum, probably not next next release).

Regards,

Takuma

Hi Parth, 

For your board, is the plan to connect a DSI bridge to some other interface? For example, our reference board connects DSI to a DSI to eDP bridge to get eDP output.

Or is the plan to connect a DSI display directly to DSI? 

I ask because we have some active debugs for connecting DSI display directly to DSI.

Regards,

Takuma

Hello Takuma Fujiwara,

In our reference design, at the moment we have 4 lane DSI to HDMI daughter card with LT8912B bridge chip. In addition, we also support DSI to LVDS daughter card with SN65DSI84 bridge chip.

Both of these bridge chips could not work properly (without any workarounds) with our AM69 based hardware due to the existing DSI0 issues which are mentioned here.

Having said that, we mainly make system on modules and our customers are allowed to directly connect DSI displays at AM69 DSI0 as well according to their system design and need.

Thank you.

Regards,

Parth P

Hi Parth,

Ok, understood that in this particular case there will be a DSI bridge, but direct DSI panel connection is a consideration as well.

It sounds like there are two DSI bridges in consideration: LT8912B and SN65DSI84. However, will these be used at the same time, so there would be need to support both DSI0 and DSI1? There is also some software limitation where we do not have support for DSI1 yet.

Regards,

Takuma

Hi Takuma Fujiwara,

Takuma Fujiwara said:

However, will these be used at the same time, so there would be need to support both DSI0 and DSI1?

No, these two bridges LT8912B and SN65DSI84 are mutually exclusive and not suppose to be working at the same time in parallel for now.

Currently for a short term, we do not plan to test/validate DSI1, however worth mentioning that we do have AM69 DSI1 pins exposed on our system on module for our customers to use if they need.

Regards,

Parth P

Hi Parth,

That is good to know about the plan to test DSI1 in the future. For now, the focus will be for DSI0 with the bridges then. 

Regards,

Takuma