DSI0: No Data on Date Lanes

Attaching the clock dumps when mentioned issue is observed. Just in case if this helps to debug the root cause.

/cfs-file/__key/communityserver-discussions-components-files/791/dsi0_5F00_no_5F00_data_5F00_k3conf_5F00_dump_5F00_clock.txt

Thanks.

Regards,

Parth P

Just to make a note that, in our design we use 24 MHz ref. clock as an external input clock to WKUP_OSCO_XI which is HFOSC_0 (DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT) parent clock for DPHY reference clock (DEV_DPHY_TX0_DPHY_REF_CLK).
Same is also reflecting in shared clock dumps in above response.

Regards,

Parth P

Hi,

Can you please read the value at 0x048000F0 and share it? 

Regards,

Brijesh

Hi Brijesh Jadav,

Please find 0x048000F0 value below.

root@aquila-am69-12345678:~# devmem2 0x048000F0
/dev/mem opened.
Memory mapped at address 0xffff879b6000.
Read at address  0x048000F0 (0xffff879b60f0): 0x00000004

Thanks.

Regards,

Parth P

Hi,

There is definitely error reported by the DSI. This is why probably it's not working. 

Can you please try reducing HFP and BLK_LINE_PULSE by equal amount, by 2 or 4 or 6 and see it helps? I think these parameters are set in the file, drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c.. 

Regards,

Brijesh

Hi Brijesh Jadav

Thanks for quick response.

Could you please be more specific on the suggested changes here ? There are couple of places in /gpu/drm/bridge/cadence/cdns-dsi-core.c mentioning HFP and BLK_LINE_PULSE.

I am also wondering that why I only might need such changes for the PHY driver where as it works fine on the other HWs ?, I assume.

Thank you.

Regards,

Parth P

Can you try changing it in cdns_dsi_bridge_enable API? 

Regards,

Brijesh

Hello Brijesh Jadav

I have tried changing HFP and BLK_LINE_PULSE as per your suggestion and this did not help any. Please see below logs.

----------------------HFP, BLK_LINE_PULSE_PKT_LEN Reduced by 2 --------------------------------------
[    7.235394] ### DBG: TI dsi_cfg.hfp = 114 cdns_dsi_bridge_early_enable
[    7.235407] ### DBG: TI dsi_cfg.hsa = 128 cdns_dsi_bridge_early_enable
[    7.235409] ### DBG: TI dsi_cfg.hbp = 636 cdns_dsi_bridge_early_enable
[    7.235411] ### DBG: TI dsi_cfg.hact = 2400 cdns_dsi_bridge_early_enable
[    7.235413] ### DBG: TI dsi_cfg.htotal = 2400 cdns_dsi_bridge_early_enable
[    7.235415] ### DBG: TI before dsi_cfg.hfp = 114 HBP_LEN(dsi_cfg.hfp) = 7471104 cdns_dsi_bridge_early_enable
[    7.235418] ### DBG: TI after dsi_cfg.hfp = 112 HBP_LEN(dsi_cfg.hfp) = 7340032 cdns_dsi_bridge_early_enable
[    7.235421] ### DBG: TI before tmp = 3020 BLK_LINE_PULSE_PKT_LEN(tmp)=3020 cdns_dsi_bridge_early_enable
[    7.235423] ### DBG: TI after tmp = 3018 BLK_LINE_PULSE_PKT_LEN(tmp)=3018 cdns_dsi_bridge_early_enable

----------------------HFP, BLK_LINE_PULSE_PKT_LEN Reduced by 4 --------------------------------------
[    7.680607] ### DBG: TI dsi_cfg.hfp = 114 cdns_dsi_bridge_early_enable
[    7.680612] ### DBG: TI dsi_cfg.hsa = 128 cdns_dsi_bridge_early_enable
[    7.680614] ### DBG: TI dsi_cfg.hbp = 636 cdns_dsi_bridge_early_enable
[    7.680617] ### DBG: TI dsi_cfg.hact = 2400 cdns_dsi_bridge_early_enable
[    7.680618] ### DBG: TI dsi_cfg.htotal = 2400 cdns_dsi_bridge_early_enable
[    7.680621] ### DBG: TI before dsi_cfg.hfp = 114 HBP_LEN(dsi_cfg.hfp) = 7471104 cdns_dsi_bridge_early_enable
[    7.680623] ### DBG: TI after dsi_cfg.hfp = 110 HBP_LEN(dsi_cfg.hfp) = 7208960 cdns_dsi_bridge_early_enable
[    7.680627] ### DBG: TI before tmp = 3020 BLK_LINE_PULSE_PKT_LEN(tmp)=3020 cdns_dsi_bridge_early_enable
[    7.680629] ### DBG: TI after tmp = 3016 BLK_LINE_PULSE_PKT_LEN(tmp)=3016 cdns_dsi_bridge_early_enable

----------------------HFP, BLK_LINE_PULSE_PKT_LEN Reduced by 6 --------------------------------------
[    7.093754] ### DBG: TI dsi_cfg.hfp = 114 cdns_dsi_bridge_early_enable
[    7.093763] ### DBG: TI dsi_cfg.hsa = 128 cdns_dsi_bridge_early_enable
[    7.093766] ### DBG: TI dsi_cfg.hbp = 636 cdns_dsi_bridge_early_enable
[    7.093768] ### DBG: TI dsi_cfg.hact = 2400 cdns_dsi_bridge_early_enable
[    7.093770] ### DBG: TI dsi_cfg.htotal = 2400 cdns_dsi_bridge_early_enable
[    7.093772] ### DBG: TI before dsi_cfg.hfp = 114 HBP_LEN(dsi_cfg.hfp) = 7471104 cdns_dsi_bridge_early_enable
[    7.093774] ### DBG: TI after dsi_cfg.hfp = 108 HBP_LEN(dsi_cfg.hfp) = 7077888 cdns_dsi_bridge_early_enable
[    7.093778] ### DBG: TI before tmp = 3020 BLK_LINE_PULSE_PKT_LEN(tmp)=3020 cdns_dsi_bridge_early_enable
[    7.093781] ### DBG: TI after tmp = 3014 BLK_LINE_PULSE_PKT_LEN(tmp)=3014 cdns_dsi_bridge_early_enable

Just to let you know that, as I mentioned, I am using fixed EDID blob for HDMI connector. With this, I saw BAD MODE DRM errors in the beginning, most likely due to missing crtc properties expected by cdns-dsi phy driver. In order to get rid of such errors, I have to hack DRM EDID reader in below way to detect and make mode state OK. This helped me to at least have a valid mode detected in DRM as you would see in my earlier shared logs for modetest.

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 5ed77e3361fd..8eb5867ec19c 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3362,6 +3362,28 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
                        DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
        }
 
+       mode->crtc_clock = mode->clock;
+       mode->crtc_hdisplay = mode->hdisplay;
+       mode->crtc_hsync_start = mode->hsync_start;
+       mode->crtc_hsync_end = mode->hsync_end;
+       mode->crtc_htotal = mode->htotal;
+
+       mode->crtc_vdisplay = mode->vdisplay;
+       mode->crtc_vsync_start = mode->vsync_start;
+       mode->crtc_vsync_end = mode->vsync_end;
+       mode->crtc_vtotal = mode->vtotal;

Could you please suggest the next steps to debug or check ?

Thank you for your support.

Regards,

Parth P

Hi Parth,

i see you have tried -2, -4 and -6, can you please try some more, like -8, -10, -12 and see if it helps? 

Regards,

Brijesh

Hi Brijesh Jadav,

I have tried to reduce aforementioned parameters to 8,10 and 12, that too did not help.

In addition, I have also tried to test DSI0 with 19.2 REF_CLK by changing external clk oscillator and MCU[2:0] boot config, that did not help either. Observation is just the same, no data on DSI0 data lanes, DSI0 CLK is seen on oscilloscope at ~119 MHz.

Please let me know the further steps to make DSI0 working on AM69.

Thank you for your support.

Regards,

Parth P

Hi Parth,

Let me see if there is any other change required to get this one working. 

Regards,

Brijesh

Hi Parth,

Can you please take a dump of few registers and share them for the review?

0x04AC0054

0x04AC0058

0x048000B0

0x048000B4

0x048000B8

0x048000C0

0x048000C4

0x048000CC

0x048000D0

0x048000F0

Regards,

Brijesh

Hello Brijesh Jadav,

Please find below register dump.

root@aquila-am69-12345678:~# ./dump_dsi_reg.sh 
/dev/mem opened.
Memory mapped at address 0xffff9bf14000.
Read at address  0x04AC0054 (0xffff9bf14054): 0x0570277F
/dev/mem opened.
Memory mapped at address 0xffffbd13a000.
Read at address  0x04AC0058 (0xffffbd13a058): 0x01700103
/dev/mem opened.
Memory mapped at address 0xffffb3dcb000.
Read at address  0x048000B0 (0xffffb3dcb0b0): 0x80A0FE00
/dev/mem opened.
Memory mapped at address 0xffffa7767000.
Read at address  0x048000B4 (0xffffa77670b4): 0x00001585
/dev/mem opened.
Memory mapped at address 0xffffaf7e2000.
Read at address  0x048000B8 (0xffffaf7e20b8): 0x00000258
/dev/mem opened.
Memory mapped at address 0xffffa0a6a000.
Read at address  0x048000C0 (0xffffa0a6a0c0): 0x027C0000
/dev/mem opened.
Memory mapped at address 0xffff975df000.
Read at address  0x048000C4 (0xffff975df0c4): 0x00720960
/dev/mem opened.
Memory mapped at address 0xffff8f8c9000.
Read at address  0x048000CC (0xffff8f8c90cc): 0x00000C56
/dev/mem opened.
Memory mapped at address 0xffffa7bfc000.
Read at address  0x048000D0 (0xffffa7bfc0d0): 0x00000C4C
/dev/mem opened.
Memory mapped at address 0xffff8a44e000.
Read at address  0x048000F0 (0xffff8a44e0f0): 0x00000004

Thank you.

Regards,

Parth P

Hi Parth,

Sorry, can you also share the register at the offset 0x04AC0050?

Regards,

Brijesh

Brijesh Jadav,
Please find the 0x04AC0050 value below,

root@aquila-am69-12345678:~# devmem2 0x04AC0050
/dev/mem opened.
Memory mapped at address 0xffff9b027000.
Read at address  0x04AC0050 (0xffff9b027050): 0x0257031F

Thank you for support.

Regards,

Parth P

Hi Parth,

There are couple of issues i see in the shared registers.

1, VSA is set to 0x5 (0x048000B4 (0xffffa77670b4): 0x00001585), whereas VSW is set to 4 (0x04AC0058 (0xffffbd13a058): 0x01700103). They should be set to same value. Not sure why VSA is different. 

2, VFP is set to 1 in both DSI (0x048000B4 (0xffffa77670b4): 0x00001585) and DSS (0x04AC0058 (0xffffbd13a058): 0x01700103) timing parameters. VFP in DSS should be greater than VFP in DSI

3, HSA in DSI is set to 0x0 (0x048000C0 (0xffffa0a6a0c0): 0x027C0000), it should not be 0, instead it should be set to 370 (128x3 - 14)

Also not sure why these two fields are not set in the register. I see these two fields are set in RTOS driver.

Can you try making these changes and see if it helps? 

Regards,

Brijesh

Hello Brijesh Jadav,
Please see my comments below.

Brijesh Jadav said:

Not sure why VSA is different. 

This is done by https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/blame/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c?h=ti-linux-6.1.y#n790 where VSA and VBP are added and reduced by '1' respectively. I am not sure if this is expected or not. I have tried changing VSA to 4. That did not help.

Brijesh Jadav said:

VFP in DSS should be greater than VFP in DSI

Again, this is something which is done by CDNS DSI PHY driver. For my test resolution, VFP for DSS itself is '1'. I have also tried to make '0' for DSI, this did not help.

Brijesh Jadav said:

HSA in DSI is set to 0x0 (0x048000C0 (0xffffa0a6a0c0): 0x027C0000), it should not be 0, instead it should be set to 370 (128x3 - 14)

Yes, this is something which I missed to enable in a shared register dumps. As I am using LT8912 DSI to HDMI bridge, I should pass 'MIPI_DSI_MODE_VIDEO_SYNC_PULSE' flag in LT8912 driver, with that, I see correct HSA 370 in DSI driver. This did not help either.

I am looking for right DSI (4 data lane, RGB888) and DPI parameters for below mode line at the moment. Could you please help provide ?

index name refresh (Hz) hdisp  hss  hse  htot  vdisp  vss  vse  vtot
  #0 800x600 60.32      800    840  968  1056  600    601  605  628    40000 flags: phsync, pvsync; type: preferred, driver

--------------------------------- DSI Timings --------------------------------
[    7.028478] ### DBG: TI DSI dsi_cfg.hfp = 114 cdns_dsi_bridge_early_enable
[    7.028489] ### DBG: TI DSI dsi_cfg.hsa = 370 cdns_dsi_bridge_early_enable
[    7.028491] ### DBG: TI DSI dsi_cfg.hbp = 252 cdns_dsi_bridge_early_enable
[    7.028493] ### DBG: TI DSI dsi_cfg.hact = 2400 cdns_dsi_bridge_early_enable
[    7.028495] ### DBG: TI DSI dsi_cfg.htotal = 2400 cdns_dsi_bridge_early_enable
[    7.028521] ### DBG: TI DSI vbp = 22 cdns_dsi_bridge_early_enable
[    7.028524] ### DBG: TI DSI vfp = 1 cdns_dsi_bridge_early_enable
[    7.028526] ### DBG: TI DSI vsa = 5 cdns_dsi_bridge_early_enable

--------------------------------- DPI Timings --------------------------------
[    7.030565] ### DBG : TI DPI dispc_vp_enable 1358 hbp = 88
[    7.030568] ### DBG : TI DPI dispc_vp_enable 1359 hfp = 40
[    7.030570] ### DBG : TI DPI dispc_vp_enable 1360 hsw = 128
[    7.030572] ### DBG : TI DPI dispc_vp_enable 1362 vbp = 23
[    7.030574] ### DBG : TI DPI dispc_vp_enable 1363 vfp = 1
[    7.030576] ### DBG : TI DPI dispc_vp_enable 1364 vsw = 4

-------------------------- LT8912 Bridge Timings ------------------------------
[    7.030585] ### DBG: lt8912_video_setup 302 LT8912 hactive = 800
[    7.030588] ### DBG: lt8912_video_setup 303 LT8912 hfp = 40
[    7.030590] ### DBG: lt8912_video_setup 304 LT8912 hpw = 128
[    7.030592] ### DBG: lt8912_video_setup 305 LT8912 hbp = 88
[    7.030594] ### DBG: lt8912_video_setup 306 LT8912 h_total = 1056
[    7.030596] ### DBG: lt8912_video_setup 316 LT8912 vactive = 600
[    7.030598] ### DBG: lt8912_video_setup 317 LT8912 vfp = 1
[    7.030600] ### DBG: lt8912_video_setup 318 LT8912 vpw = 4
[    7.030602] ### DBG: lt8912_video_setup 319 LT8912 vbp = 23
[    7.030604] ### DBG: lt8912_video_setup 320 LT8912 v_total = 628

Regards,

Parth P

Parth Pancholi said:

Yes, this is something which I missed to enable in a shared register dumps. As I am using LT8912 DSI to HDMI bridge, I should pass 'MIPI_DSI_MODE_VIDEO_SYNC_PULSE' flag in LT8912 driver, with that, I see correct HSA 370 in DSI driver. This did not help either.

What is the HDMI bridge here? Does HSA issue resolve with this change? What's the value of 0x048000F0 register? 

Regards,

Brijesh

Hi Brijesh Jadav,

As I mentioned in my original post, I am trying to bring up LT8912B DSI to HDMI bridge connected at AM69 DSI0. For now I am struggling to get data out of AM69 DSI0 as you are aware.

Parth Pancholi said:

We have a custom HW based on AM69 SOC and would like to use SOC DSI0 with LT8912B bridge for HDMI connector.
I am bringing up AM69 DSI0 and LT8912B bridge chip for DSI to HDMI conversion. During my tests, I observed that DSI CLK is at-least available at ~119 MHz for my test resolution 800x600, however on the DSI0 data lanes, I do not see any data. Data lines stays high at ~1.8V.

Brijesh Jadav said:

Does HSA issue resolve with this change? What's the value of 0x048000F0 register? 

Yes, I see correct HSA value in register. However, 0x048000F0 still show the same error of missing HSYNC.

root@aquila-am69-12345678:~# devmem2 0x048000F0
/dev/mem opened.
Memory mapped at address 0xffff9dc88000.
Read at address  0x048000F0 (0xffff9dc880f0): 0x00000004
root@aquila-am69-12345678:~# devmem2 0x048000C0                                                                                                                                            
/dev/mem opened.
Memory mapped at address 0xffffbe999000.
Read at address  0x048000C0 (0xffffbe9990c0): 0x00FC0172

Could you please check and comment on my questions in above response related to DPI to DSI timing parameters for my mode line ?

Also please suggest the further steps to debug.

Regards,

Parth P

Dear Brijesh Jadav,

I came to know that on J784s4 EVM where DSI0 is kind of validated for similar SOCs/AM69 uses the "fixed resolution 800x600" and "DSI0 configured in two lanes". This is hard coded here I believe. https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/?h=ti-linux-6.1.y&id=50b06eec44cdae252de3154517333dca90394b12 

With this exact settings of two lane DSI and fixed mode of 800x600 with NHSYNC and NVSYNC, I see basic DSI0 finally working. Apart from this fixed resolution of 800x600 + two lane DSI config, not a single resolution worked so far. Even the 800x600 does not work at all with 4 lane DSI settings.

However, this is not what we expect.
We would like to see broad range of resolutions working with a 4 lane DSI on AM69.
This is because of the fact that we have 4 lane DSI to HDMI daughter card (with LT8912B bridge chip) which is expected to be working for all the supported mode for all the displays connected to the HDMI port.
In addition, we also support LVDS daughter card with DSI to LVDS bridge with 1280x800 resolution from the same DSI interface.

Could you please help confirm the current limitation of the fixed resolution (800x600) and fixed DSI data lanes (2 lanes) on AM69 ?
Also, kindly let us know that if there's a SW limitation at the moment, when can we expect the proper solution from TI for this ?

Regards,

Parth P

Hi Parth,

Any further update on this issue? 

Regards,

Brijesh

Dear Brijesh,

I was waiting for your response on the below questions. I am waiting for an update from TI on this.

Parth Pancholi said:

Could you please help confirm the current limitation of the fixed resolution (800x600) and fixed DSI data lanes (2 lanes) on AM69 ?
Also, kindly let us know that if there's a SW limitation at the moment, when can we expect the proper solution from TI for this ?

Nevertheless, I have already created the related E2E thread, please see below link.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1391369/am69-am69-limitations-of-mipi-dsi-and-expected-improvements

Above link has a summary of the AM69 DSI0 issues and we are waiting for TI to provide the fixes for them.

Thank you.

Regards,

Parth P

Hi Parth,

Parth Pancholi said:

Could you please help confirm the current limitation of the fixed resolution (800x600) and fixed DSI data lanes (2 lanes) on AM69 ?

Atleast from the DSI module, its not limited to 800x600 resolution and 2 lanes.. I am not sure from Linux driver side, i would suggest you to continue discussion on the other thread, where Takuma is helping you out from Linux driver perspective. 

Regards,

Brijesh