PROCESSOR-SDK-AM62X: Reading a file from UBIFS makes every mtd partitions shifted 2 bytes

$ git diff
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index 510775e9a88f..8100879cdaa1 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -628,8 +628,8 @@ ospi0: spi@fc40000 {
                        cdns,trigger-address = <0x0>;
                        clocks = <&k3_clks 75 7>;
                        assigned-clocks = <&k3_clks 75 7>;
-                       assigned-clock-parents = <&k3_clks 75 8>;
-                       assigned-clock-rates = <166666666>;
+                       assigned-clock-parents = <&k3_clks 75 9>; /* Select PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK */
+                       assigned-clock-rates = <80000000>;
                        power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
                        #address-cells = <1>;
                        #size-cells = <0>;

From e09c3479ca952e59ad362ca0a7d299b4b20ebf2c Mon Sep 17 00:00:00 2001
From: huy <huykv1@fpt.com>
Date: Thu, 1 Aug 2024 18:17:37 +0700
Subject: [PATCH] s28hs02gt DAC read mode

---
 drivers/spi/spi-cadence-quadspi.c | 31 ++++++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index cb9ab1ba67..ce71e56198 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -39,6 +39,7 @@
 
 /* Capabilities */
 #define CQSPI_SUPPORTS_OCTAL		BIT(0)
+#define CQSPI_STIG_DATA_LEN_MAX		 8
 
 struct cqspi_st;
 
@@ -172,6 +173,8 @@ struct cqspi_driver_platdata {
 #define CQSPI_REG_SIZE_ADDRESS_MASK		0xF
 #define CQSPI_REG_SIZE_PAGE_MASK		0xFFF
 #define CQSPI_REG_SIZE_BLOCK_MASK		0x3F
+#define CQSPI_REG_SIZE_MEM_SIZE_ON_C0           (0x2<<21)
+#define CQSPI_REG_SIZE_MEM_SIZE_ON_C0_MASK      (0x3<<21)
 
 #define CQSPI_REG_SRAMPARTITION			0x18
 #define CQSPI_REG_INDIRECTTRIGGER		0x1C
@@ -215,6 +218,7 @@ struct cqspi_driver_platdata {
 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB		16
 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB		19
 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB		20
+#define	CQSPI_REG_CMDCTRL_ADDR_EN		BIT(19)
 #define CQSPI_REG_CMDCTRL_RD_EN_LSB		23
 #define CQSPI_REG_CMDCTRL_OPCODE_LSB		24
 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK		0x7
@@ -1146,6 +1150,19 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
 	/* 0 means 1 byte. */
 	reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 		<< CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
+
+	/* setup ADDR BIT field */
+	if (op->addr.nbytes) {
+		writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
+		/*
+		 * address bytes are zero indexed
+		 */
+		reg |= (((op->addr.nbytes - 1) &
+			  CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
+			  CQSPI_REG_CMDCTRL_ADD_BYTES_LSB);
+		reg |= CQSPI_REG_CMDCTRL_ADDR_EN;
+	}
+
 	status = cqspi_exec_flash_cmd(cqspi, reg);
 	if (status)
 		return status;
@@ -1275,6 +1292,8 @@ static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
 	reg = readl(reg_base + CQSPI_REG_SIZE);
 	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 	reg |= (op->addr.nbytes - 1);
+	reg &= ~CQSPI_REG_SIZE_MEM_SIZE_ON_C0_MASK;
+	reg |= CQSPI_REG_SIZE_MEM_SIZE_ON_C0;
 	writel(reg, reg_base + CQSPI_REG_SIZE);
 	readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */
 	return 0;
@@ -1418,6 +1437,8 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
 	reg = readl(reg_base + CQSPI_REG_SIZE);
 	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 	reg |= (op->addr.nbytes - 1);
+	reg &= ~CQSPI_REG_SIZE_MEM_SIZE_ON_C0_MASK;
+	reg |= CQSPI_REG_SIZE_MEM_SIZE_ON_C0;
 	writel(reg, reg_base + CQSPI_REG_SIZE);
 	readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */
 	return 0;
@@ -1993,7 +2014,14 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
 	cqspi_configure(f_pdata, mem->spi->max_speed_hz);
 
 	if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
-		if (!op->addr.nbytes)
+		// if (!op->addr.nbytes)
+					/*
+	 * Performing reads in DAC mode forces to read minimum 4 bytes
+	 * which is unsupported on some flash devices during register
+	 * reads, prefer STIG mode for such small reads.
+	 */
+		if (!op->addr.nbytes ||
+		    op->data.nbytes < CQSPI_STIG_DATA_LEN_MAX)
 			return cqspi_command_read(f_pdata, op);
 
 		return cqspi_read(f_pdata, op);
@@ -2514,3 +2542,4 @@ MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");
+
-- 
2.25.1

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index ddb53f3c9a6fc8b508eefddfb90200f312a30369..ea4ec953d06aa3e927efed4074203507635c4d29 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -39,7 +39,6 @@
 
 /* Capabilities */
 #define CQSPI_SUPPORTS_OCTAL		BIT(0)
-#define CQSPI_STIG_DATA_LEN_MAX		 8
 
 struct cqspi_st;
 
@@ -861,7 +860,7 @@ static bool cqspi_is_idle(struct cqspi_st *cqspi)
 {
 	u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 
-	return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
+	return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB);
 }
 
 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
@@ -906,6 +905,9 @@ static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr)
 {
 	unsigned int dummy_clk;
 
+	if (!op->dummy.nbytes)
+		return 0;
+
 	dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
 	if (dtr)
 		dummy_clk /= 2;
@@ -1153,14 +1155,12 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
 
 	/* setup ADDR BIT field */
 	if (op->addr.nbytes) {
+		reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
+		reg |= ((op->addr.nbytes - 1) &
+			CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
+			<< CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
+
 		writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
-		/*
-		 * address bytes are zero indexed
-		 */
-		reg |= (((op->addr.nbytes - 1) &
-			  CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
-			  CQSPI_REG_CMDCTRL_ADD_BYTES_LSB);
-		reg |= CQSPI_REG_CMDCTRL_ADDR_EN;
 	}
 
 	status = cqspi_exec_flash_cmd(cqspi, reg);
@@ -1181,6 +1181,9 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
 		memcpy(rxbuf, &reg, read_len);
 	}
 
+	/* Reset CMD_CTRL Reg once command read completes */
+	writel(0, reg_base + CQSPI_REG_CMDCTRL);
+
 	return 0;
 }
 
@@ -1935,7 +1938,7 @@ static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
 	u_char *buf = op->data.buf.in;
 	int ret;
 
-	if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
+	if (!cqspi->rx_chan || !virt_addr_valid(buf) || len <= 16) {
 		cqspi_memcpy_fromio(op, buf, cqspi->ahb_base + from, len);
 		return 0;
 	}
@@ -2014,14 +2017,13 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
 	cqspi_configure(f_pdata, mem->spi->max_speed_hz);
 
 	if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
-		// if (!op->addr.nbytes)
-					/*
+	/*
 	 * Performing reads in DAC mode forces to read minimum 4 bytes
 	 * which is unsupported on some flash devices during register
 	 * reads, prefer STIG mode for such small reads.
 	 */
 		if (!op->addr.nbytes ||
-		    op->data.nbytes < CQSPI_STIG_DATA_LEN_MAX)
+		    op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
 			return cqspi_command_read(f_pdata, op);
 
 		return cqspi_read(f_pdata, op);