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Original question:

AM625: How to present Clock tree configuration that was executed in the target

[AM625] Set OSPI0 Clock setting to 160MHZ

Cong Pham
Prodigy 220 points
Other Parts Discussed in Thread: SYSCONFIG, SK-AM62

Dear TI experts

I want to set the OSPI0 clock to 160MHz

I'm trying to change the clock config here:

Besides, We found the OSPI clocking settings in this area:

But when we add 2 line of code below to the *.syscfg file,

we face the build error like this:

Can you tell me how to switch the  MAIN_OSPI_REF_CLK_SEL into 

160.0MHz

Thanks,

Cong.

  • 0
    TI__Mastermind 37548 points

    Hi,

    Thanks for the query. I have taken your inputs and will revert back soon.

    Regards,

    Tushar

  • 0
    TI__Mastermind 31854 points

    Hi Cong,

    You are trying to set frequency of OSPI0 to 160.0 MHz, you can simply set it in the SysConfig file.

    Once you build, the files generated will surely have the configuration of 160 MHz set for OPSI0.

    Regards,

    Vaibhav

  • 0
    TI__Mastermind 31854 points

    Hi Cong,

    I understood, what you are trying to do. 

    So from Clock Tree Tool, you set 160.0 MHz for MAIN_OSPI_REF_CLK_SEL and got a file generated.

    Currently, we are not supporting addition of generated configurations from clock tree tool straight into .sysconfig file.

    Regards,

    Vaibhav

  • 0
    TI__Mastermind 31854 points

    Hi Cong,

    As mentioned earlier we are not supporting the addition of generated configurations from clock tree tool to example.sysconfig file as of now.

    So, I have got a work around for you by the help of which you can set the OSPI clock frequency to 160 MHz.

    Please look at the diagram below:

    The two clocks are:

    1. MAIN_PLL0_HSDIV1_CLKOUT: Supports clock frequencies of 200, 166 or 133 MHz.
    2. MAIN_PLL1_HSDIV5_CLKOUT: Supports clock frequency of 160 MHz.

    Based on your usecase, we will use the second one which provides 160 MHz.

    Follow the steps below:

    1. Once you have sysconfig files generated, then look up the file named ti_power_clock_config.c and set the clock name and frequency as shown in the code below.


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      SOC_ModuleClockFrequency gSocModulesClockFrequency[] = {
      { TISCI_DEV_FSS0_OSPI_0, TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK, 160000000 },
      { TISCI_DEV_WKUP_UART0, TISCI_DEV_WKUP_UART0_FCLK_CLK, 48000000 },
      { SOC_MODULES_END, SOC_MODULES_END, SOC_MODULES_END },
      };
      XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX



    3. For your clear understanding the clock has been taken from the file named tisci_clocks.h (Located here: mcu_plus_sdk_am62x_08_06_00_18\source\drivers\sciclient\include\tisci\am62x\tisci_clocks.h)


    4. Basically instead of choosing the clock  TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK, we are using TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLKS


    5. Next, copy the generated files and paste them into example directory as shown in the image below.





    6. Set SysConfig to be not included in the build and then build the project.

    Now you should be good to go.

    Regards,

    Vaibhav

  • 0 in reply to Vaibhav Kumar
    Prodigy 220 points

    Hello Vaibhav,

    Thanks for your reply

    Currentlly, we can set the clock of SBl1 to 160 Mhz correctlly, but we face an issue on linux side: the output of OSPI clock is not correct.

    The OSPI output clock is captured on the actual ZKW ECU from SBL1 stage is 160.66MHz

    • w/ syscfg: 160000000, divider:4
    • w/o clocktree params

    Continue to modify on Linux side: Output of OSPI is 153.67MHz

    dts:

    waweform:

    Could you please tell me 

    1.Why is there consistence of OSPI clock between SBL stage and Linux stage?

    2.How can we set the clock of OSPI on linux exactly to 160Mhz?

  • 0 in reply to Cong Pham
    TI__Guru 65077 points

    Hi Cong,

    Just noticed this thread here. Will provide some additional guidance soon.

    Regards, Andreas

  • 0 in reply to Andreas Dannenberg
    TI__Guru 65077 points

    Closing out this thread by adding back into from an offline discucssion.

    Cong Pham said:
    1.Why is there consistence of OSPI clock between SBL stage and Linux stage?

    The clock was initialized with different frequencies, at SBL vs. Linux stage.

    Cong Pham said:
    2.How can we set the clock of OSPI on linux exactly to 160Mhz?

    We need modify the assigned-clock-parents property of the ospi0 node to select the same input (“parent”) as it was suggested earlier.  In the device tree file you can do this like this (note this is on the SK-AM62 board with stock SDK v8.6):

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    $ git diff
    diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
    index 510775e9a88f..8100879cdaa1 100644
    --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
    +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
    @@ -628,8 +628,8 @@ ospi0: spi@fc40000 {
    cdns,trigger-address = <0x0>;
    clocks = <&k3_clks 75 7>;
    assigned-clocks = <&k3_clks 75 7>;
    - assigned-clock-parents = <&k3_clks 75 8>;
    - assigned-clock-rates = <166666666>;
    + assigned-clock-parents = <&k3_clks 75 9>; /* Select PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK */
    + assigned-clock-rates = <160000000>;
    power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
    #address-cells = <1>;
    #size-cells = <0>;
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    If I do this I can see how the input clock to the OSPI module changes in Linux, as follows.

    Before (see how clock parent 8 feeds the RCLK with clock ID 7 with 166.66MHz)

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    root@am62xx-evm:/# k3conf dump clock 75
    |--------------------------------------------------------------------------------|
    | VERSION INFO |
    |--------------------------------------------------------------------------------|
    | K3CONF | (version v0.1-88-g982f5c2 built Fri Feb 24 05:07:09 UTC 2023) |
    | SoC | AM62X SR1.0 |
    | SYSFW | ABI: 3.1 (firmware version 0x0008 '8.6.4--v08.06.04 (Chill Capybar)') |
    |--------------------------------------------------------------------------------|
    |-------------------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name | Status | Clock Frequency |
    |-------------------------------------------------------------------------------------------------------------------------------------|
    | 75 | 0 | DEV_FSS0_OSPI_0_OSPI_DQS_CLK | CLK_STATE_READY | 0 |
    | 75 | 1 | DEV_FSS0_OSPI_0_OSPI_HCLK_CLK | CLK_STATE_READY | 500000000 |
    | 75 | 2 | DEV_FSS0_OSPI_0_OSPI_ICLK_CLK | CLK_STATE_READY | 0 |
    | 75 | 3 | DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT | CLK_STATE_READY | 0 |
    | 75 | 4 | DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT | CLK_STATE_READY | 0 |
    | 75 | 5 | DEV_FSS0_OSPI_0_OSPI_OCLK_CLK | CLK_STATE_READY | 0 |
    | 75 | 6 | DEV_FSS0_OSPI_0_OSPI_PCLK_CLK | CLK_STATE_READY | 500000000 |
    | 75 | 7 | DEV_FSS0_OSPI_0_OSPI_RCLK_CLK | CLK_STATE_READY | 166666666 |<--+
    | 75 | 8 | DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 166666666 |---+
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    After (see how now clock parent 9 feeds the RCLK with clock ID 7 with 160MHz)

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    root@am62xx-evm:~# k3conf dump clock 75
    |--------------------------------------------------------------------------------|
    | VERSION INFO |
    |--------------------------------------------------------------------------------|
    | K3CONF | (version v0.1-88-g982f5c2 built Fri Feb 24 05:07:09 UTC 2023) |
    | SoC | AM62X SR1.0 |
    | SYSFW | ABI: 3.1 (firmware version 0x0008 '8.6.4--v08.06.04 (Chill Capybar)') |
    |--------------------------------------------------------------------------------|
    |-------------------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name | Status | Clock Frequency |
    |-------------------------------------------------------------------------------------------------------------------------------------|
    | 75 | 0 | DEV_FSS0_OSPI_0_OSPI_DQS_CLK | CLK_STATE_READY | 0 |
    | 75 | 1 | DEV_FSS0_OSPI_0_OSPI_HCLK_CLK | CLK_STATE_READY | 500000000 |
    | 75 | 2 | DEV_FSS0_OSPI_0_OSPI_ICLK_CLK | CLK_STATE_READY | 0 |
    | 75 | 3 | DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT | CLK_STATE_READY | 0 |
    | 75 | 4 | DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT | CLK_STATE_READY | 0 |
    | 75 | 5 | DEV_FSS0_OSPI_0_OSPI_OCLK_CLK | CLK_STATE_READY | 0 |
    | 75 | 6 | DEV_FSS0_OSPI_0_OSPI_PCLK_CLK | CLK_STATE_READY | 500000000 |
    | 75 | 7 | DEV_FSS0_OSPI_0_OSPI_RCLK_CLK | CLK_STATE_READY | 160000000 |<--+
    | 75 | 8 | DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | |
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Regards, Andreas