Hi Mani,

Manikandan Murugan said:

In PHY mode without data training (DDR Mode, without loopback) configuration, 6.1596ns of Delay time calculated for CLK to Data. If i consider this delay, its difficult to meet setup & hold timing requirements for 200MHz. In this case, what is the max frequency TDA4 can supports, Since our NOR Flash have 0.4ns as Setup & Hold time? 

We suggest using DDR PHY Data Training mode. The highest frequency supported here is 166MHz.

Best Regards,

Matt

Hi Mani,

First, if you are using DDR PHY Data Training mode, you will only need to focus on this table:

Manikandan Murugan said:

T = OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD]

Where are you seeing this value? This is not a parameter in the switching characteristics that I see.

Manikandan Murugan said:

P = CLK cycle time

This is the clk period based on what speed mode you are using.

Manikandan Murugan said:

• M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
• N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

Please see the TRM section 12.3.2.4.2 Configuring the OSPI Controller for Optimal Use for information on what these registers are and how they should be configured.

Best Regards,

Matt

Hi Mani,

The current version of the datasheet does not yet have this updated timing information. Pasted below is what the new datasheet will have.

6.10.5.19 OSPI

6.10.5.19.1.1 OSPI0/1 With PHY Data Training

Read and write data valid windows will shift due to variation in process, voltage, temperature, and operating frequency. A data training method may be implemented to dynamically configure optimal read and write timing. Implementing data training enables proper operation across temperature with a specific process, voltage, and frequency operating condition, while achieving a higher operating frequency.

Data transmit and receive timing parameters are not defined for the data training use case since they are dynamically adjusted based on the operating condition.

Table 6-82 defines DLL delays required for OSPI0/1 with Data Training. Table 6-83, Figure 6-98, Figure 6-99, Table 6-84, Figure 6-100, and Figure 6-101 present timing requirements and switching characteristics for OSPI0/1 with Data Training.

Table 6-82 OSPI0/1 DLL Delay Mapping for PHY Data Training

MODE	OSPI_PHY_CONFIGURATION_REG BIT FIELD	DELAY VALUE
Transmit
All modes	PHY_CONFIG_TX_DLL_DELAY_FLD	(1)
Receive
All modes	PHY_CONFIG_RX_DLL_DELAY_FLD	(2)

(1) Transmit DLL delay value determined by training software

(2) Receive DLL delay value determined by training software

Table 6-83 OSPI0 Timing Requirements – PHY Data Training see Figure 6-98, and Figure 6-99

NO.			MODE	MIN	MAX	UNIT
O15	tsu(D-LBCLK)	Setup time, OSPI0_D[7:0] valid before active OSPI0_DQS edge	DDR with DQS	(1)		ns
O16	th(LBCLK-D)	Hold time, OSPI0_D[7:0] valid after active OSPI0_DQS edge	DDR with DQS	(1)		ns
O21	tsu(D-LBCLK)	Setup time, OSPI0_D[7:0] valid before active OSPI0_DQS edge	SDR with External Board Loopback	(1)		ns
O22	th(LBCLK-D)	Hold time, OSPI0_D[7:0] valid after active OSPI0_DQS edge	SDR with External Board Loopback	(1)		ns
	tDVW	Data valid window (O15 + O16)	1.8V, DDR with DQS	1.4		ns
		Data valid window (O21 + O22)	1.8V, SDR with External Board Loopback	1.7		ns

(1) Minimum setup and hold time requirements for OSPI0/1_D[7:0] inputs are not defined when Data Training is used to find the optimum data valid window. The t_DVW parameter defines the minimum data invalid window required. This parameter is provided in lieu of minimum setup and minimum hold times, where it must be used to check compatibility with the data valid window provided by an attached device.

Table 6-84 OSPI/1 Switching Characteristics – PHY Data Training See Figure 6-100 and Figure 6-101

NO.	PARAMETER		MODE	MIN	MAX	UNIT
O1	tc(CLK)	Cycle time, OSPI0/1_CLK	1.8V, DDR	6.0	6.0	ns
O7			1.8V, SDR	6.0	6.0	ns
O2	tw(CLKL)	Pulse duration, OSPI0/1_CLK low	DDR	((0.475P(1)) - 0.3)		ns
O8			SDR
O3	tw(CLKH)	Pulse duration, OSPI0/1_CLK high	DDR	((0.475P(1)) - 0.3)		ns
O9			SDR
O4	td(CSn-CLK)	Delay time, OSPI0/1_CSn[3:0] active edge to OSPI0/1_CLK rising edge	DDR	((0.475P(1)) + (0.975M(2)R(4)) + (0.028TD(5)) - 1)	((0.525P(1)) + (1.025M(2)R(4)) + (0.055TD(5)) + 1)	ns
O10			SDR
O5	td(CLK-CSn)	Delay time, OSPI0/1_CLK rising edge to OSPI0/1_CSn[3:0] inactive edge	DDR	((0.475P(1)) + (0.975N(3)R(4)) - (0.028TD(5)) - 1)	((0.525P(1)) + (1.025N(3)R(4)) - (0.055TD(5)) + 1)	ns
O11			SDR
O6	td(CLK-D)	Delay time, OSPI0/1_CLK active edge to OSPI0/1_D[7:0] transition	DDR	(6)	(6)	ns
O12			SDR
	tDIVW	Data invalid window (O6 Max - Min)	DDR		1	ns
		Data invalid window (O12 Max - Min)	SDR

(1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns

(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4) R = reference clock cycle time in ns

(5) TD = PHY_CONFIG_TX_DLL_DELAY_FLD

(6) Minimum and maximum delay times for OSPI0_D[7:0] outputs are not defined when Data Training is used to find the optimum data valid window. The t_DIVW parameter defines the maximum data invalid window. This parameter is provided in lieu of minimum and maximum delay times, where it must be used to check compatibility with the data valid window requirements of an attached device.

Figure 6-100 OSPI0/1 Switching Characteristics – PHY DDR Data Training

Figure 6-101 OSPI0/1 Switching Characteristics – PHY SDR Data Training

Best Regards,

Matt

Hi Mani,

The latest datasheet is not yet available. I don't have a revision to share currently, so I have given you the most up to date information above for the sections you need.

Best,

Matt