TMS320C6657: DDR3 Configuration ROM Boot

Alex Jones

Part Number: TMS320C6657

Tool/software:

Currently we are able to successfully boot from a SPI NOR flash device when nothing is placed in DDR3. When we begin placing sections in DDR3 such as: Program.sectMap[".text"] = "DDR3"; we can no longer boot. Our assumption is this is happening because because the PLL2 for the DDR3 is never getting initialized. To remedy this, we have followed TI's instructions and made the necessary changes to this BOOT_EMIF4_TBL_T . We have also placed this at the proper address in L2SRAM as specified in TI's instructions. We can confirm it is placed correctly through our memory map. Here is our table:

==================================================================================================================================================================

#pragma DATA_SECTION (emif4Cfg, ".emif4Cfg")
const BOOT_EMIF4_TBL_T emif4Cfg = {

/* Config select msw */
BOOT_EMIF4_ENABLE_MSW_pllCtl | \
BOOT_EMIF4_ENABLE_MSW_powerManageCtl | \
BOOT_EMIF4_ENABLE_MSW_sdRamTiming1 | \
BOOT_EMIF4_ENABLE_MSW_sdRamTiming2 | \
BOOT_EMIF4_ENABLE_MSW_sdRamTiming3 | \
BOOT_EMIF4_ENABLE_MSW_ddrPhyCtl1 | \
BOOT_EMIF4_ENABLE_MSW_sdRamRefreshCtl | \
BOOT_EMIF4_ENABLE_MSW_sdRamOutImpdedCalCfg | \
BOOT_EMIF4_ENABLE_MSW_sdRamConfig,

/* Config select lsw */
BOOT_EMIF_ENABLE_LSW_config52 | \
BOOT_EMIF_ENABLE_LSW_config53 | \
BOOT_EMIF_ENABLE_LSW_config54 | \
BOOT_EMIF_ENABLE_LSW_config55 | \
BOOT_EMIF_ENABLE_LSW_config60,

/* The following values are all derived from Brad and Toms work
to get the correct settings for the GEL file. These have been
copied over to the best of my abilties to ensure they are the same */

2, /* pllPrediv */
79, /* pllMult */
2, /* pllPostDiv */ // Cant change since its set to 2 on the c6657

0x63026832, /* sdRamConfig */ // DDR_SDCFG
0, /* sdRamConfig2 */ // No mention in GEL

// First set to 0x00005161 then changed to 0x00001458 after setup
0x00001458, /* sdRamRefreshCtl */ // DDR_SDRFC

/* Set to values based on GEL file */
0x1113783C, /* sdRamTiming1 */ // DDR_SDTIM1
0x30B37FE3, /* sdRamTiming2 */ // DDR_SDTIM2
0x559F8ADF, /* sdRamTiming3 */ // DDR_SDTIM3

0, /* lpDdrNvmTiming */
0, /* powerManageCtl */ // DDR_PMCTL
0, /* iODFTTestLogic */
0, /* performCountCfg */
0, /* performCountMstRegSel */
0, /* readIdleCtl */
0, /* sysVbusmIntEnSet */
//0x70073214, /* sdRamOutImpdedCalCfg */ // Gel File: 0x70073214
0x700742C5, /* sdRamOutImpdedCalCfg */ // Gale: 0x700742C5
0, /* tempAlterCfg */

0x0010010F, /* ddrPhyCtl1 */ // DDR_DDRPHYC

0, /* ddrPhyCtl2 */ // No mention in GEL
0, /* priClassSvceMap */
0, /* mstId2ClsSvce1Map */
0, /* mstId2ClsSvce2Map */
0, /* eccCtl */ // No ECC on ram
0, /* eccRange1 */ // ^
0, /* eccRange2 */ // ^
0, /* rdWrtExcThresh */

/* Register descriptions can be found at the following file:
* www.ti.com/.../sprugv8e.pdf
*/
0x0020000F, /* DDR3_CONFIG_0 */ /* Bit 0-3: CMD_PHY_DLL_LOCK_DIFF
Bit 13-22: CMD_PHY_CTRL_SLAVE_RATIO */
0x01000000, /* DDR3_CONFIG_1 */ /* Bit 18-24: PHY_DQ_OFFSET */
0x5A, /* DDR3_CONFIG_2 */ /* Bit 0-19: DATA0_PHY_WRLVL_INIT_RATIO */
0x5B, /* DDR3_CONFIG_3 */ /* Bit 0-19: DATA1_PHY_WRLVL_INIT_RATIO */
0x44, /* DDR3_CONFIG_4 */ /* Bit 0-19: DATA2_PHY_WRLVL_INIT_RATIO */
0x44, /* DDR3_CONFIG_5 */ /* Bit 0-19: DATA3_PHY_WRLVL_INIT_RATIO */
0, /* DDR3_CONFIG_6 */ /* Bit 0-19: DATA4_PHY_WRLVL_INIT_RATIO */
0, /* DDR3_CONFIG_7 */ /* Bit 0-19: DATA5_PHY_WRLVL_INIT_RATIO */
0, /* DDR3_CONFIG_8 */ /* Bit 0-19: DATA6_PHY_WRLVL_INIT_RATIO */
0, /* DDR3_CONFIG_9 */ /* Bit 0-19: DATA7_PHY_WRLVL_INIT_RATIO */
0, /* DDR3_CONFIG_10 */ /* Bit 0-19: DATA8_PHY_WRLVL_INIT_RATIO */
0, /* DDR3_CONFIG_11 */ /* Not listed */
0x08000000, /* DDR3_CONFIG_12 */ /* Bit 24: USE_RANK0_DELAYS
Bit 27: CMD_PHY_INVERT_CLKOUT */
0, /* DDR3_CONFIG_13 */ /* Not listed */
0x81, /* DDR3_CONFIG_14 */ /* Bit 0-19: DATA0_PHY_GATELVL_INIT_RATIO */
0x80, /* DDR3_CONFIG_15 */ /* Bit 0-19: DATA1_PHY_GATELVL_INIT_RATIO */
0x79, /* DDR3_CONFIG_16 */ /* Bit 0-19: DATA2_PHY_GATELVL_INIT_RATIO */
0x79, /* DDR3_CONFIG_17 */ /* Bit 0-19: DATA3_PHY_GATELVL_INIT_RATIO */
0, /* DDR3_CONFIG_18 */ /* Bit 0-19: DATA4_PHY_GATELVL_INIT_RATIO */
0, /* DDR3_CONFIG_19 */ /* Bit 0-19: DATA5_PHY_GATELVL_INIT_RATIO */
0, /* DDR3_CONFIG_20 */ /* Bit 0-19: DATA6_PHY_GATELVL_INIT_RATIO */
0, /* DDR3_CONFIG_21 */ /* Bit 0-19: DATA7_PHY_GATELVL_INIT_RATIO */
0, /* DDR3_CONFIG_22 */ /* Bit 0-19: DATA8_PHY_GATELVL_INIT_RATIO */
0, /* DDR3_CONFIG_23 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_24 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_25 */ /* Bit 0-21: DATA0_FIFO_WE_SLAVE_RATIO */
0, /* DDR3_CONFIG_26 */ /* Bit 0-21: DATA1_FIFO_WE_SLAVE_RATIO */
0, /* DDR3_CONFIG_27 */ /* Bit 0-21: DATA2_FIFO_WE_SLAVE_RATIO */
0, /* DDR3_CONFIG_28 */ /* Bit 0-21: DATA3_FIFO_WE_SLAVE_RATIO */
0, /* DDR3_CONFIG_29 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_30 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_31 */ /* NA for ti c665x */

0, /* DDR3_CONFIG_32 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_33 */ /* Bit 0-21: DATA_ECC_FIFO_WE_SLAVE_RATIO */
0, /* DDR3_CONFIG_34 */ /* Bit 0-21: DATA0_WR_DATA_SLAVE_RATIO */
0, /* DDR3_CONFIG_35 */ /* Bit 0-21: DATA1_WR_DATA_SLAVE_RATIO */
0, /* DDR3_CONFIG_36 */ /* Bit 0-21: DATA2_WR_DATA_SLAVE_RATIO */
0, /* DDR3_CONFIG_37 */ /* Bit 0-21: DATA3_WR_DATA_SLAVE_RATIO */
0, /* DDR3_CONFIG_38 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_39 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_40 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_41 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_42 */ /* Bit 0-19: DATA_ECC_WR_DATA_SLAVE_RATIO */
0, /* DDR3_CONFIG_43 */ /* Bit 0-19: DATA0_WR_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_44 */ /* Bit 0-19: DATA1_WR_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_45 */ /* Bit 0-19: DATA2_WR_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_46 */ /* Bit 0-19: DATA3_WR_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_47 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_48 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_49 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_50 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_51 */ /* Bit 0-19: DATA_ECC_WR_DQS_SLAVE_RATIO */
0x00000200, /* DDR3_CONFIG_52 */ /* Bit 0-19: DATA0_RD_DQS_SLAVE_RATIO */
0x00000200, /* DDR3_CONFIG_53 */ /* Bit 0-19: DATA1_RD_DQS_SLAVE_RATIO */
0x00000200, /* DDR3_CONFIG_54 */ /* Bit 0-19: DATA2_RD_DQS_SLAVE_RATIO */
0x00000200, /* DDR3_CONFIG_55 */ /* Bit 0-19: DATA3_RD_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_56 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_57 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_58 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_59 */ /* NA for ti c665x */
0x00000200, /* DDR3_CONFIG_60 */ /* Bit 0-19: DATA_ECC_RD_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_61 */ /* Not listed */
0, /* DDR3_CONFIG_62 */ /* Not listed */
0 /* DDR3_CONFIG_63 */ /* Not listed */
};

=================================================================================================================================================================
The following is an example we have looked into:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1171336/faq-tms320c6657-how-to-run-the-direct-spi-boot-example-on-ti-c6657-evm-without-ibl

We would be grateful for any and all information regarding how to initialize DDR3 successful via this "BOOT_EMIF4_TBL_T emif4Cfg" DDR3 boot table

over 1 year ago

0 Alex Jones over 1 year ago

Prodigy 110 points

We have combed through documentation and tried to determine what as many of the DDR3_CONFIG_# represent and the values above come from our GEL file

0 Alex Jones over 1 year ago

Prodigy 110 points

name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
L2SRAM 00800000 000ffd20 00069124 00096bfc RW X
DDR_CFG 008ffd20 00000180 00000178 00000008 RW X
L2MAGIC 008ffffc 00000004 00000000 00000004 RW X
MSMCSRAM 0c000000 00100000 0000c33c 000f3cc4 RW X
DDR3 80000000 20000000 019a2ee0 1e65d120 RW X

MEMORY MAP FOR REFERENCE

0 Shankari G over 1 year ago in reply to Alex Jones

TI__Mastermind 25535 points

Alex,

Sure. I could do that.

Refer to this Excel sheet particularly. (“Keystone I DDR3 Register Calculation Spreadsheet ” from this link : http://www.ti.com/lit/zip/sprabl2 ( This link will directly download, sprabl2.zip file. Please look into your download folder).

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1189685/faq-tms320c6657-how-to-calculate-the-ddr3-interface-registers-for-keystone-i-devices-and-test-debug-on-keystone-i-evm

The definition and significance of each DDR3 registers will be given in the application note of DDR3:- https://www.ti.com/lit/ug/sprugv8e/sprugv8e.pdf

Documents to read at first sight :

====================

1. Design requirements - https://www.ti.com/lit/an/sprabi1d/sprabi1d.pdf

2.Keyston I Interface bring - up - https://www.ti.com/lit/an/spracl8/spracl8.pdf

3. KeyStone I DDR3 Initialization - https://www.ti.com/lit/an/sprabl2e/sprabl2e.pdf

4. Keystone Architecture DDR3 Memory Controller - https://www.ti.com/lit/ug/sprugv8e/sprugv8e.pdf

Regards

Shankari G

0 Alex Jones over 1 year ago in reply to Shankari G

Prodigy 110 points

Thank you for your response, we have used those register calculators and updated our table accordingly, only a few changes were necessary. That said, our DDR3 is still not getting initialized properly. We have put together a DDR3 memory test based on a TI example and we have verified it works properly by debugging in no boot mode with and without running the GEL file and the result were as expected. This same memory test is how we are trying to verify our NOR flash boot ddr3 initialization. We know we are placing our emif table in the correct/reserved section of memory, however we have no way of knowing if this emif table we have spent all day filling out is even doing anything. We have investigated the memory controller registers and they are different in no boot mode vs nor flash boot mode when they should be the same as we have an emif table that reflects our GEL file. We are unsure of what to investigate next.

0 Alex Jones over 1 year ago in reply to Alex Jones

Prodigy 110 points

Here is our updated emif table......
==========================================================

const BOOT_EMIF4_TBL_T emif4Cfg = {

/* Config select slsw */
BOOT_EMIF_ENABLE_SLSW_config0 | \
BOOT_EMIF_ENABLE_SLSW_config1 | \
BOOT_EMIF_ENABLE_SLSW_config2 | \
BOOT_EMIF_ENABLE_SLSW_config3 | \
BOOT_EMIF_ENABLE_SLSW_config4 | \
BOOT_EMIF_ENABLE_SLSW_config5 | \
BOOT_EMIF_ENABLE_SLSW_config6 | \
BOOT_EMIF_ENABLE_SLSW_config7 | \
BOOT_EMIF_ENABLE_SLSW_config8 | \
BOOT_EMIF_ENABLE_SLSW_config9 | \
BOOT_EMIF_ENABLE_SLSW_config12 | \
BOOT_EMIF_ENABLE_SLSW_config14 | \
BOOT_EMIF_ENABLE_SLSW_config15 | \
BOOT_EMIF_ENABLE_SLSW_config16 | \
BOOT_EMIF_ENABLE_SLSW_config17 | \
BOOT_EMIF_ENABLE_SLSW_config18 | \
BOOT_EMIF_ENABLE_SLSW_config19 | \
BOOT_EMIF_ENABLE_SLSW_config20 | \
BOOT_EMIF_ENABLE_SLSW_config21 | \
BOOT_EMIF_ENABLE_SLSW_config25,

/* Config select lsw */
BOOT_EMIF_ENABLE_LSW_config34 | \
BOOT_EMIF_ENABLE_LSW_config43 | \
BOOT_EMIF_ENABLE_LSW_config52 | \
BOOT_EMIF_ENABLE_LSW_config53 | \
BOOT_EMIF_ENABLE_LSW_config54 | \
BOOT_EMIF_ENABLE_LSW_config55 | \
BOOT_EMIF_ENABLE_LSW_config60,

/* The following values are all derived from Brad and Toms work
to get the correct settings for the GEL file. These have been
copied over to the best of my abilties to ensure they are the same */

2, /* pllPrediv */
79, /* pllMult */
2, /* pllPostDiv */ // Cant change since its set to 2 on the c6657

0x63026AB2, /* sdRamConfig */ // DDR_SDCFG

0, /* sdRamConfig2 */ // No mention in GEL

// First set to 0x00005161 then changed to 0x00001458 after setup
00005161, /* sdRamRefreshCtl */ // DDR_SDRFC

/* Set to values based on GEL file */
0x1113783C, /* sdRamTiming1 */ // DDR_SDTIM1
0x30B37FE3, /* sdRamTiming2 */ // DDR_SDTIM2
0x559F8ADF, /* sdRamTiming3 */ // DDR_SDTIM3

0x0010010F, /* ddrPhyCtl1 */ // DDR_DDRPHYC

/* Register descriptions can be found at the following file:
* www.ti.com/.../sprugv8e.pdf
*/
0x0020000F, /* DDR3_CONFIG_0 */ /* Bit 0-3: CMD_PHY_DLL_LOCK_DIFF
Bit 13-22: CMD_PHY_CTRL_SLAVE_RATIO */
0x01000000, /* DDR3_CONFIG_1 */ /* Bit 18-24: PHY_DQ_OFFSET */
0x0000005B, /* DDR3_CONFIG_2 */ /* Bit 0-19: DATA0_PHY_WRLVL_INIT_RATIO */
0x0000005C, /* DDR3_CONFIG_3 */ /* Bit 0-19: DATA1_PHY_WRLVL_INIT_RATIO */
0x00000045, /* DDR3_CONFIG_4 */ /* Bit 0-19: DATA2_PHY_WRLVL_INIT_RATIO */
0x00000045, /* DDR3_CONFIG_5 */ /* Bit 0-19: DATA3_PHY_WRLVL_INIT_RATIO */
0x0000005B, /* DDR3_CONFIG_6 */ /* Bit 0-19: DATA4_PHY_WRLVL_INIT_RATIO */
0x0000005C, /* DDR3_CONFIG_7 */ /* Bit 0-19: DATA5_PHY_WRLVL_INIT_RATIO */
0x00000045, /* DDR3_CONFIG_8 */ /* Bit 0-19: DATA6_PHY_WRLVL_INIT_RATIO */
0x00000045, /* DDR3_CONFIG_9 */ /* Bit 0-19: DATA7_PHY_WRLVL_INIT_RATIO */
0x00000000, /* DDR3_CONFIG_10 */ /* Bit 0-19: DATA8_PHY_WRLVL_INIT_RATIO */
0, /* DDR3_CONFIG_11 */ /* Not listed */
0x08000000, /* DDR3_CONFIG_12 */ /* Bit 24: USE_RANK0_DELAYS
Bit 27: CMD_PHY_INVERT_CLKOUT */
0, /* DDR3_CONFIG_13 */ /* Not listed */
0x00000086, /* DDR3_CONFIG_14 */ /* Bit 0-19: DATA0_PHY_GATELVL_INIT_RATIO */
0x00000085, /* DDR3_CONFIG_15 */ /* Bit 0-19: DATA1_PHY_GATELVL_INIT_RATIO */
0x0000007D, /* DDR3_CONFIG_16 */ /* Bit 0-19: DATA2_PHY_GATELVL_INIT_RATIO */
0x0000007D, /* DDR3_CONFIG_17 */ /* Bit 0-19: DATA3_PHY_GATELVL_INIT_RATIO */
0x00000086, /* DDR3_CONFIG_18 */ /* Bit 0-19: DATA4_PHY_GATELVL_INIT_RATIO */
0x00000085, /* DDR3_CONFIG_19 */ /* Bit 0-19: DATA5_PHY_GATELVL_INIT_RATIO */
0x0000007D, /* DDR3_CONFIG_20 */ /* Bit 0-19: DATA6_PHY_GATELVL_INIT_RATIO */
0x0000007D, /* DDR3_CONFIG_21 */ /* Bit 0-19: DATA7_PHY_GATELVL_INIT_RATIO */
0, /* DDR3_CONFIG_22 */ /* Bit 0-19: DATA8_PHY_GATELVL_INIT_RATIO */
0, /* DDR3_CONFIG_23 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_24 */ /* NA for ti c665x */
0x000000C1, /* DDR3_CONFIG_25 */ /* Bit 0-21: DATA0_FIFO_WE_SLAVE_RATIO */
0, /* DDR3_CONFIG_26 */ /* Bit 0-21: DATA1_FIFO_WE_SLAVE_RATIO */
0, /* DDR3_CONFIG_27 */ /* Bit 0-21: DATA2_FIFO_WE_SLAVE_RATIO */
0, /* DDR3_CONFIG_28 */ /* Bit 0-21: DATA3_FIFO_WE_SLAVE_RATIO */
0, /* DDR3_CONFIG_29 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_30 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_31 */ /* NA for ti c665x */

0, /* DDR3_CONFIG_32 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_33 */ /* Bit 0-21: DATA_ECC_FIFO_WE_SLAVE_RATIO */
0x000000D0, /* DDR3_CONFIG_34 */ /* Bit 0-21: DATA0_WR_DATA_SLAVE_RATIO */
0, /* DDR3_CONFIG_35 */ /* Bit 0-21: DATA1_WR_DATA_SLAVE_RATIO */
0, /* DDR3_CONFIG_36 */ /* Bit 0-21: DATA2_WR_DATA_SLAVE_RATIO */
0, /* DDR3_CONFIG_37 */ /* Bit 0-21: DATA3_WR_DATA_SLAVE_RATIO */
0, /* DDR3_CONFIG_38 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_39 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_40 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_41 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_42 */ /* Bit 0-19: DATA_ECC_WR_DATA_SLAVE_RATIO */
0x00000090, /* DDR3_CONFIG_43 */ /* Bit 0-19: DATA0_WR_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_44 */ /* Bit 0-19: DATA1_WR_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_45 */ /* Bit 0-19: DATA2_WR_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_46 */ /* Bit 0-19: DATA3_WR_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_47 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_48 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_49 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_50 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_51 */ /* Bit 0-19: DATA_ECC_WR_DQS_SLAVE_RATIO */
0x00000034, /* DDR3_CONFIG_52 */ /* Bit 0-19: DATA0_RD_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_53 */ /* Bit 0-19: DATA1_RD_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_54 */ /* Bit 0-19: DATA2_RD_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_55 */ /* Bit 0-19: DATA3_RD_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_56 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_57 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_58 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_59 */ /* NA for ti c665x */
0, /* DDR3_CONFIG_60 */ /* Bit 0-19: DATA_ECC_RD_DQS_SLAVE_RATIO */
0, /* DDR3_CONFIG_61 */ /* Not listed */
0, /* DDR3_CONFIG_62 */ /* Not listed */
0 /* DDR3_CONFIG_63 */ /* Not listed */
};

0 Shankari G over 1 year ago in reply to Alex Jones

TI__Mastermind 25535 points

Alex,

I could see a mismatch here:-

In the FAQ-Code:-

[FAQ] TMS320C6657: How to run the direct SPI-BOOT example on TI-C6657-EVM without IBL ? - Processors forum - Processors - TI E2E support forums

===============

const BOOT_EMIF4_TBL_T emif4Cfg = {

---------------

In your code above:-

=================

const BOOT_EMIF4_TBL_T emif4Cfg = {

----

Please check the differences in the register values with the TI EVM board Vs your custom board.

Like that, check each register values one by one.

For example, do these comparisons and evaluate one by one...

KEEP TWO SETUP IN PARALLEL - ONE is TI EVM and another is your custom board.

===================================================================

case 1: -

Set the register settings same in FAQ ---- > Both TI EVM and your custom board and do a direct SPI boot and make sure it works on both..

Case 2:-

Set the register settings as per your customized one ( as you given above) ----> Both in TI EVM and in Custom board.

Regards

Shankari G