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TDA4VM: "user" & "permissions" of CCS when making changes with Memory Browser

Part Number: TDA4VM

Tool/software:

Hi Support-Team,

I realized that when I'm connected e.g. to C66xdsp_1 having set-up a RAT that this is used by the CCS Memory Browser (View->Memory Browser).

But I also realized (strongly assume) that the CPU is "covered" by a Firewall (no write access) whereas the CCS Memory Browser isn't (memory modifications possible).
(TDA4VM: Write to 00A0 0004h from C66xx_0 not possible - Processors forum - Processors - TI E2E support forums)

Is there a document / explanation how the CCS (in general) handles "access" ?

Thanks in advance, Wolfgang

P.S.: Confused as there's Memory "local" to a core & memory not accessable by one core, how this is done "from outside" DAP port.

  • Hi Wolfgang,

    Can you clarify if you are using a GP, HS-SE, or HS-FS device? I realize that I didn't ask that in our earlier conversation - generally firewalls are only enforced on HS device variants. Regardless, we would still recommend using the Sciclient APIs going forward for the reason I mentioned in that thread. 

    Writing/Reading through CCS Memory Browser will fall under debug permissions (noted as "d" on the same firewall chart here) whereas if you were writing to the memory region from code running on the C66x core, that would fall under write permissions (noted as "w"). 

    Could you clarify based on the last thread where you were having issues with this memory region? From C66x with code were you able to read from the memory region?

    Best,

    Asha

  • Hi Asha,

    The TDA4VM is "as delivered". Hence, I assume it's HS-FS. 
    Thanks for hint that "d" gives the "debugger" Permissions. 
    I was a bit confused as I thought also a debugger could get w/r-permissions. 
    Hence, I thought the debugger must be a "user" rather than a permission itself.

    Thanks, Wolfgang

    P.S.: As stated I got your point regarding Sciclient API.