AM6422: Inquiry Regarding AM6422 GPIO Read Timing

Hello Shivangi,

The clock cycle queries I will send to the hardware team to comment.

I can help answer item 2:

Shivangi Jain said:

Is there an option to read all GPIO lines at once in parallel?

Yes, this is possible through Linux Command Line and directly reading the registers of the GPIOs.

Best,

Anshu

Hi Anshu,

Thank you for confirming that it’s possible to read all GPIO lines at once in parallel.

Do you have any updates on the clock cycle queries? It would be great if we could get responses to the remaining queries as soon as possible.

Thanks,
Shivangi

Hello Shivangi,

Shivangi Jain said:

Do you have any updates on the clock cycle queries? It would be great if we could get responses to the remaining queries as soon as possible.

Expert input:.

I think the general answer is that trying to use one of the processor cores (A53, R5, etc.) will pay a heavy latency penalty, especially for reads, because of the complex interconnect.  They are better off using the PRU which is intended for this type of operation and will be much more deterministic. 

I found a couple of links below which describe the situation

(38) SK-AM62-LP: Reading the IO register takes too much time - Processors forum - Processors - TI E2E support forums

(+) AM3352: GPIO read/write latency - Processors forum - Processors - TI E2E support forums

I don’t think they will be able to read the GPIOs every 50ns from the A53 or R5, but they may be able to do it with the PRU. 

Similar reference for other processors

https://www.ti.com/lit/SPRACE8

Shivangi Jain said:

it’s possible to read all GPIO lines at once in parallel.

You can read 32 GPIOs in one command (from the same GPIO bank), but then you have to make sure that all of the GPIOs used on the board are mapped to the same GPIO bank. This is likely to be a challenge.

Regards,

Sreenivasa

Hi Sreenivasa,

Thank you for your response and for providing the suggested links for further study.

Kallikuppa Sreenivasa said:

(+) AM3352: GPIO read/write latency - Processors forum - Processors - TI E2E support forums

I reviewed the above post and noted that a timing of 5ns was achieved, which may be aligns well with my application's requirements. However, the AM6422 PRU core only has 20 GPI lines, whereas I need to read 28 GPIO lines within 50ns. Could you please provide any suggestions on how to achieve this with the AM6422?

Additionally, if I use the R5 core running at 800MHz, how much time would it take to read the GPIO lines?

Thank you,
Shivangi

Hello Shivangi,

Thank you.

Shivangi Jain said:

Additionally, if I use the R5 core running at 800MHz, how much time would it take to read the GPIO lines?

I don’t think they will be able to read the GPIOs every 50ns from the A53 or R5, but they may be able to do it with the PRU. 

Shivangi Jain said:

Could you please provide any suggestions on how to achieve this with the AM6422?

Help me understand your requirement on toggling 28 IOs and the application.

Regards,

Sreenivasa

Hi Sreenivasa,

Kallikuppa Sreenivasa said:

Help me understand your requirement on toggling 28 IOs and the application.

My requirement involves interfacing with a 2-channel, 14-bit external ADC. Specifically, I need to read 28 GPIOs within a 50 ns window, as the ADC outputs data at this rate. Given this constraint, I’m looking for guidance on how to effectively manage these GPIOs using the AM6422 to meet this timing requirement.

Any suggestions or insights you can provide would be greatly appreciated.

Thanks,
Shivangi

Hello Shivangi,

Thank you.

This should be feasible. 

Are you able to add the requirements into s simple block diagram?

Regards,

Sreenivasa 

Hi Sreenivasa, 

Kallikuppa Sreenivasa said:

Are you able to add the requirements into s simple block diagram?

Sharing here the simple block diagram for your reference. We will be using a 2-channel ADC with a sampling rate of 48 MSPS.

Here are the time requirements for the ADC:
- Sampling rate: 48 MSPS
- Clock frequency: 48 MHz
- Pipeline delay: 7 clock cycles
- Output propagation delay: max 6 ns
- Conversion time: Pipeline delay + Output propagation delay

Let me know if you need any further details.

Additionally, if you have any suggestions for alternative TI processors that might be more suitable, I’d be open to exploring those options as well.

Best Regards,
Shivangi

Hello Shivangi,

Thank you.

Do you have the ADC part number.

This is to check internally if someone has looked at interfacing with the specific ADC.

The Am64x would be the family to consider.

The Device selection could vary.

Regards,

Sreenivasa

Hello Shivangi,

Do you have the setup to do some experiments or is the project in analysis phase.

Regards,

Sreenivasa

Hi Sreenivasa,

Kallikuppa Sreenivasa said:

Do you have the ADC part number

Yes, The ADC part number is AD9248BSTZ-65.

Kallikuppa Sreenivasa said:

Do you have the setup to do some experiments or is the project in analysis phas

Currently, the project is in the analysis phase, so I don’t have the complete setup for the ADC yet. However, I do have the AM6442 EVK available if we can use it for GPIO experiments.

Thanks,
Shivangi

Hello Shivangi,

Thank you.

Let me reach out to the experts and come back with any inputs or thoughts they may have.

Regards,

Sreenivasa

Shivangi

Sitara AM64x has 2x PRU-ICSSGs (Programmable Realtime Unit - Industrial Communication SubSystem). Each PRU-ICSSG has 2x slices, and each slice has 3x PRU cores (processing cores) and 20 GPIO pins. In total, there are 80 GPIO pins. If pin is configured for input, we can directly read the state of pin via PRU register in single PRU cycle. For write also, it is a single instruction operation. PRU can run at 333 MHz maximum frequency, which means one operation/cycle takes 3 ns only. More details are present in AM243x MCU+ SDK: PRU Guide (ti.com)

One concern I see is you need 28+2 pins, and it may not be possible to do it using one slice but can be done using 2 slices with IPC between 2 slices.

Please note that we also have some examples in SDK which interface with certain TI ADCs. Please refer to following page for more details : AM243x MCU+ SDK: PRU ADC (ti.com)

Regards

Dhaval

Hi Dhaval, 
Thank you for the response. 

Dhaval Khandla said:

 AM243x MCU+ SDK: PRU Guide (ti.com)

I checked the PRU guide but I wasn't able to find information on how to measure the GPIO read time practically
I have the AM6442 EVK and would appreciate your guidance on how to measure the actual GPIO read time using the PRU core.

Thanks,
Shivangi