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AM2432: CLKOUT0 and RMII_REF_CLK

Part Number: AM2432
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hi,

  1. When MII is selected, we got answer on e2e that CLKOUT0 is not connected to RMII_REF_CLK. Is there any description of this in datasheet or TRM? My understanding is that MII does not require reference clock input, so it is not described implicitly
  2. When MII is selected, customer would like to use CLKOUT0 for PHY clock instead of dedicated oscillator for PHY . Is it ok ? I don't find any reference design like this. So I need the opinion from expert.

Thank you.

Best Regards,

Kasai

  • CLKOUT0 can be configured to source 25MHz or 50MHz. Software will need to configure the internal path to route the clock signal to the pin and then the pin mux logic would need to be configured to select that specific signal function and turn on the output buffer associated with the CLKOUT0 pin. The attached PHY device will need to be held in reset with another pin configured as a GPIO, such that it asserts reset to the PHY by default. Software will need to configure the GPIO to drive the reset signal to the inactive state after waiting for the minimum reset assertion time required by the PHY.

    You should use the clock tree tool to understand how to configure the internal clock paths.  The clock tree tool is part of the SYSCONFIG tool.  Select clock tree tool in the software select dropdown and select the appropriate device after launching the SYSCONFIG tool. 

    Note: The attached PHY device may see a short clock cycle or glitch on the clock signal when it is first turned on because the output buffer turn on is asynchronous to the clock transitions, so there is no guarantee the signal will be driven at the beginning of a clock cycle. This may cause problems for some attached devices. In most cases, having a short clock cycle doesn't cause a problem as long as reset is asserted when the clock glitch occurs.

    Regards,
    Paul

  • Hi Paul,

    Sorry for my slow response. I was in vacation.

    Thank you for your reply and detail advice. That's very hepful.

    Regarding care of reset and lock for PHY when power on, is it applicable not only for TI PHY but also other supplier's PHY ?

    I've ever hard of this guide line for TI PHY, but I have no idea for other supplier's.

    Best Regards,

    Kasai 

  • Devices with synchronous circuits are designed for a maximum operating frequency. A short cycle clock is very likely to over-clock the synchronous state machine operating the device because the short cycle clock is seen as a much higher frequency clock cycle than expected by the synchronous circuit.

    This higher frequency clock cycle can violate internal timing paths in the synchronous state machine which will cause it to do unexpected things. This concern is not unique to TI Ethernet PHYs. It applies to any Ethernet PHY. However, the state machine should behave as expected as long as software asserts reset for the minimum period required by the Ethernet PHY after all power supplies and clocks are stable.

    Regards,
    Paul 

  • Hi Paul,

    Thank you for your reply.

    We asked customer to create the appropriate timming of CLKOUT0 and reset by software based on PHY datasheet and they accepted it.

    Best Regards,

    Kasai