TMS320C6416T: Request for Max Data Rate of HPI interface and PCI interface

Sujith

I want to be sure you are aware of the following notice in the product folder:

For HPI, please refer to the following application note found in the product folder: TMS320C64x DSP Host Port Interface (HPI) Performance

For PCI, the datasheet specifies the minimum POCLK to be 30ns and figure 49 shows the input/output timing.

--Paul 

Hi PaulM,

Thanks for your inputs.

PaulM said:

I want to be sure you are aware of the following notice in the product folder

Why not design support available from Ti ? We are developing this board with 10 years longevity support. We would like to know how many years this DSP TMS320C6416TBCLZD1 will be available. Moreover we are new in the design and development of this particular DSP chipset. We may required Ti support to bring up and validate the boards.

Regards,
Sujith M

I'll have the correct team comment on this. 

--Paul 

Hi Paul,

I have gone through the application note. The App note Section 7 Measurement table 1 shows the throughput maximum at CPU clock 720MHz.But we are using TMS320C6416TBCLZD1 chip,it supports clock rate 1GHz.

Could you please provide the exact HPI -16bit data rate based on below requirement? So that i can confirm my FPGA to DSP hardware connection is ok or not ?

1. Configurable Bus Width HPI 16 bit selected
2. Read, Write using Level 2 memory/cache (L2)
3.Burst Length 8 /512

Attached below a ppt  i hope this will give you some insight on my board hardware connection, FPGA i have connected DSP HPI 16 bit lanes to FPGA I/O banks.

/cfs-file/__key/communityserver-discussions-components-files/791/DSP.pptx

Thanks,
Sujith M

Hello! HPI is simple to understand and quickly build a solution. However, it is an interface where DSP is considered slave, I would not go this way with FPGA. On the other hand, PCI is just right tool to access FPGA as peripheral. I can't tell you exact numbers, there might be some app note on the topic. Either way, once you're asking about data rate, PCI is the right solution IMHO.

See this manual www.ti.com/.../spru581c.pdf

Hi Victor,

I understand the your point. But our customer requirement is HPI 16 bit  not PCI .The HPI 16 Bit to be connected with FPGA.So i request you to share the HPI speed at 16 bit mode and when CPU core clock is running at 1Ghz.

Regards,
Sujith M

Hello,

Be sure nobody measured the speed in the setup you're asking for. Please understand, peripheral itself and app note were developed in a times, when 600 MHz was standard clock for C64x, not even 720. Next, one may refer to spru578c for timing diagrams to understand access cycle timing, then identify their limits in the datasheet. Finally, this access machine has to be implemented on the host side, FPGA in your case. So matching above timing finding with your FPGA capabilities one can estimate expected performance. Sorry, I'm unaware about other kind of reference material.

Hi Victor,

Ok. We have calculated the DSP throughput at higher CPU clock rate 850Mhz and 1Ghz by referring to spru578c .
Could you please review the calculation sheet and provide your confirmation?

/cfs-file/__key/communityserver-discussions-components-files/791/LATENCY_5F00_CALCULATION_5F00_SHEET_5F00_FPGA.xlsx

Regards,
Sujith M

I’ll look over your spreadsheet and get back to you tomorrow. 

any updates?

he implemented formula matches the app note. 

I did notice small discrepancies on the throughput numbers - I did not see where your numbers were calculated. I add a Excel formula to your table to show the results from that. You can check in the attached updated Excel. 

Note: I did not check the table input data 

--Paul

 LATENCY_CALCULATION_SHEET_FPGA_updated.xlsx

Hi PaulM,

Thanks for your reply.In the spreadsheet we have considered the assumed value of Latency and xfer for CPU clock rate 850Mhz and 1Ghz .
Could you please review the calculation sheet and provide your confirmation?

Regards,
Sujith M

Sujith Mohandas said:

Could you please review the calculation sheet and provide your confirmation?

What specifically? 

Hi PaulM,

Please check below image.

Are these assumptions correct?

Sujith

I don't have the information necessary data to validate your assumptions. 

--Paul