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Frequent questions

  • [FAQ] AM2432: How do I run the FOTA ENET example?

    Part Number: AM2432 FOTA ENET example uses ethernet to transfer a new Application Image from the User/PC side to the AM243x/AM64x device running the old Application Image. Once the new Application Image is received successfully, the FOTA ENET example…

  • [FAQ] TDA4AL-Q1: Ipc echo test failing in SDK 10.1

    Part Number: TDA4AEN-Q1 Sporadic hang in RPMessage_ProcessAnnounce API in ipc echo test while running with safeRTOS on SDK 10.1 , it was observed even with ctrlmsgTask keeping at high priority.

  • [FAQ] TDA4AEN-Q1: How to run Fls app INDAC example with performance numbers ?

    Part Number: TDA4AEN-Q1 FLS APP INDAC example is not showing performance numbers on SDK 11.0. How to get performance numbers similar to other jacinto devices ?

  • [FAQ] TDA4AEN-Q1: How to generate EPWM wave form on MCU2_0 core in J7 Entry ?

    Part Number: TDA4AEN-Q1 Requirement: To Generate EPWM waveform of 30 Hz on EPWM1 instance using register writes and also get an interrupt on each new pulse.

  • [FAQ] AM62L ( AM62L32 , AM62L31 ) - Collaterals for reference during different phases of custom board design, self-review and bring-up

    Part Number: AM62L Hi TI Experts, I am starting a new project and want to use Sitara AM62x processor family in the design. Can you guide me in selecting the processor and list the relevant collaterals that I can refer during different phases on the…

  • [FAQ] TDA4VEN-Q1: TIDL back port from 10.x or 11.x to higher version

    Part Number: TDA4VEN-Q1 Other Parts Discussed in Thread: AM68A , AM69A , AM67A , TDA4VH Get the desired version of tidl firmware: Download according to edgeai-tidl-tools script: https://github.com/TexasInstruments/edgeai-tidl-tools/blob/master…

  • [FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM625SIP - Collaterals for reference during different phases of custom board design, self-review and bring-up

    Part Number: AM625 Other Parts Discussed in Thread: AM623 , , , AM620-Q1 , , SK-AM62B-P1 , SK-AM62-LP , SK-AM62B , SK-AM62-SIP , AM62D-Q1 , AM62X-PET-CALC Hi TI Experts, I am starting a new project and want to use Sitara AM62x processor family in…

  • [FAQ] TDA4VM: How to do IPC echo test example on TDA4VH/VM

    Part Number: TDA4VM Other Parts Discussed in Thread: TDA4VH Hi Team, How can I build and run IPC Echo test example on TDA4VH boards?

  • [FAQ] AM625 / AM623 / AM625-Q1 / AM620-Q1 / AM62L / AM62A / AM62P / AM62D-Q1 / AM64x / AM243x Custom board hardware design - Processor pin mapping and SK board connections (Supply rail, Capacitors and ferrites)

    Part Number: AM625 Other Parts Discussed in Thread: TMDS64EVM , SK-AM64B , TMDS62LEVM , SK-AM62B-P1 , SK-AM62-LP , SK-AM62B , SK-AM62A-LP , AUDIO-AM62D-EVM , SK-AM62P-LP , SK-AM62-SIP Hi TI Experts, Please provide the SOC power pin mapping and connection…

  • [FAQ] J7200XSOMXEVM: Unable to connect to cluster-1 of MCU R5F and Main R5F in No-boot mode from CCS debugger

    Part Number: J7200XSOMXEVM Other Parts Discussed in Thread: DRA821 After loading the Gel script as described in PSDK RTOS in No Boot Mode, I am unable to connect to the MCU_R5F_0_1 and Main_R5F_0_1 cores.

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