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Original question:

[FAQ] AM6442: What PRU_ICSSG functionality is on each AM64x device?

AM6442: Clarification - PRU_ICSSG functionality is on each AM64x device

Andrew McBain
Prodigy 170 points
Part Number: AM6442
Other Parts Discussed in Thread: PROFIBUS

Tool/software:

In this forum post related to the PRU_ICSSG cores in the AM6442, what does the word "support" mean?

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1098260/faq-am6442-what-pru_icssg-functionality-is-on-each-am64x-device/4068272#4068272

For example, it says...

"All PRU_ICSSG features other than Industrial Communication interfaces are supported on all AM64x devices. PRU_ICSSG Industrial Communication interfaces include MII/RGMII, MDIO, three channel peripheral interface (EnDat 2.2 and BiSS), and Sigma-delta (SD) decimation."

And then says...

"C means only PRU_ICSSG, no Industrial Communication support (i.e., no Ethernet or networking)"

Does no support mean that...

A)  The PRU_ICSSG is not physically wired to the RGMII and DMA channels in the silicon, and that even if you wrote your own software, you could never get it to work.

B)  The hardware exists, but some ROM code, SYSFW, or configuration is code missing.  You could get it to work if you wrote your own software for it.

Also, with the right software (and assuming the PRU_ICSSG can access the same memory areas as the R5F cores), I see nothing that would prevent the PRU_ICSSG from just using the CPSW_3G peripheral and associated DMA channels to do Ethernet the same way one of the R5F cores does.  That seems possible no matter what feature set the device supports.  Sure, it's not optimal, but it seems it could be done.

  • 0
    TI__Guru* 85155 points

    Hello Andrew,

    "No industrial communication support" means that CPSW is your only Ethernet networking option on the chip

    I am not sure about the DMA channels. The PRU_ICSSG subsystem itself will be the same in all AM64x devices, with the same INTERNAL inputs and outputs. However, in order for an interface to work, there needs to be a signal path from the actual pins on the processor, to those internal inputs and outputs. My understanding is that the traces that go from the pins to the PRU_ICSSG's internal MII, 3 channel peripheral interface, and sigma-delta decimation interfaces, might not be connected. Regardless of how it is implemented in silicon, you CANNOT do PRU Ethernet on a C device.

    What does "PRU Ethernet" actually mean? 

    The CPSW is a bunch of circuits that are designed to communicate over an Ethernet interface. These circuits are then controlled by Linux or the R5F cores, which also run the network stack. You can have a maximum of 2 external Ethernet ports connected to the CPSW peripheral.

    The PRU_ICSSG is a bunch of custom cores that are ultra-optimized to move signals in and out of processor pins. So they can be programmed to implement Ethernet, just like the CPSW, but they can ALSO be programmed to do a bunch of other things. For example, implement networking protocols that usually require you to buy an external ASIC, like Profinet, Profibus, EtherCAT, Ethernet/IP, etc. Or emulating other communication interfaces, like UART, SPI, or custom bus protocols. For more information, refer to https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1269989/faq-what-is-a-pru-core-why-are-pru-gpio-signals-different-from-regular-gpios

    You don't use the PRU cores to control the CPSW circuit. Instead, the PRU cores act like they ARE a bunch of circuits like the CPSW, and then another core (Either Linux A53s or MCU+ R5F cores) runs the networking stack and controls the PRU subsystem, just like they would do if they were using a CPSW. Each PRU_ICSSG instance can connect to a max of 2 external Ethernet ports, for a max of 4 PRU Ethernet ports.

    Due to pinmuxing limitations, an AM64x can only have a max of 5 Ethernet ports at a time (2 CPSW & 3 PRU Ethernet, or 1 CPSW & 4 PRU Ethernet).

    Regards,

    Nick