Problem with DDR I/O calibration

Hi,

no suggestions?

could it be that issue signaling a layout problem? or are we missing any during the setup? we took that part one-to-one from the GEL file for that DSP EVM...

Thanks

Alex

Here is our GEL DDR2 init code.  Works for us on our custom PCB.

/******************************************************************************/

/* Setup_DDR2() */

/* */

/* DDR2 = 32M x 16 @ 148.8MHz */

/* */

/******************************************************************************/

Setup_DDR2( )

{

int dummy_read;

int pch_nch;

GEL_TextOut( "Setup DDR2 Memory Controller... ");

/*

Step 1 - Setup PPL1 so PPL1_SYSCLK1 is as close to 300MHz as you can get (already done)

*/

/*

Step 2 - Enable DDR2 memory controller clock

*/

psc_change_state1( LPSC_DDR2, LPSC_STATE_ENABLE );

/*

Step 3 - VTP calibration

*/

VTPIO_CTL &= ~0x00000040; // Clear POWERDN

VTPIO_CTL &= ~0x00000080; // Clear LOCK

VTPIO_CTL |= 0x00002000; // Set CLKRZ in case it was cleared before (VTP looks for CLKRZ edge transition)

VTPIO_CTL &= ~0x00002000; // Clear CLKRZ (Use read-modify-write to ensure 1 VTP cycle wait for previous instruction)

VTPIO_CTL |= 0x00002000; // Set CLKRZ (Use read-modify-write to ensure 1 VTP cycle wait for previous instruction)

while( (VTPIO_CTL & 0x00008000) == 0 )

{

/* Wait for ready bit */

}

VTPIO_CTL |= 0x00000080; // Set LOCK bit for static calibration mode

VTPIO_CTL |= 0x00000040; // Set POWERDN bit to power down VTP module

/*

Step 4 - Allow input receivers to save power

*/

VTPIO_CTL |= 0x00004000; // Set IOPWRDN to allow powerdown of input receivers when PWRDNEN is set

/*

Step 5 - Configure DDR PHY control reg

*/

DDR_DDRPHYCR = 0x000000C4; // Enable DQS strobe, enable receivers to power down when idle, RL = 4

/*

Step 6 - Configure DDR Slew

*/

DDR_SLEW = DDR_SLEW & 0xFFFFFFCF; // Clear PDENA and CMOSEN because we are using DDR2 (not mDDR)

/*

Step 7 - Unlock DDR settings so we can change them

Step 8 - Load SDCR, make sure TIMUNLOCK is set

*/

DDR_SDCR |= 0x00800000; // Set BOOTUNLOCK

DDR_SDCR = (0x00174622 | 0x00008000); // Unlock Timer Regs, 16-bit bus, CAS=3, 4 banks, 1024-word page, weak drive

/*

Step 9 - Skip this step, only needed for mDDR

*/

/*

Step 10 - Program the two timing regs

*/

DDR_SDTIMR = 0x1E923209; // DDR Timing ( set for 148.8MHz )

DDR_SDTIMR2 = 0x3C11C722; // DDR Timing ( set for 148.8MHz )

/*

Step 11 - Lock down the timing changes

*/

DDR_SDCR = DDR_SDCR & ~0x00008000; // Lock Timer Regs

/*

Step 12 - Program refresh control reg

*/

DDR_SDRCR = 0xC0000488; // Refresh Control [ 7.8 usec * 148.8MHz ]

/*

Step 13 - Soft Reset ( SYNCRESET) of DDR2 PHY

Step 14 - ENABLE of DDR2 PHY

*/

psc_change_state1( LPSC_DDR2, LPSC_STATE_SYNCRESET );

psc_change_state1( LPSC_DDR2, LPSC_STATE_ENABLE );

/*

Step 15 - Disable self refresh

*/

DDR_SDRCR &= ~0xC0000000; // disable self-refresh

/*

Step 16 - Set PBBPR to a value lower than default to prevent blocking

*/

/* Do this in the real code (BOARDINIT) because the BOOT ROM doesnt do this step. */

GEL_TextOut( "[Done]\n" );

}

Can you look at this thread too , to see if this is source of your issue

http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/t/129998.aspx

Make sure you are clearing the LOCK bit before performing calibration, stated in the user guide.

Jeff

Hi Dean,  Mukul and Jeff

thanks for your answers. Yes, we are clearing the LOCK bit before performing the calibration routine.

So, it seems that it could be a HW layout issue.

In that sense, how should we interpretate that polling the READY bit is blocked?

If we skip the calibration routine, we have a deterministic behavior. One data line (D9) fails to return the correct value (reading). Writting
seems to be fine. 

We will check if the reset is working correctely, as suggested in the other thread posted above.  

Thanks.

Alex

Looking at your 1st post in this thread, I still don't think you have all the calibrations steps.  See the code below, which is from our GEL file that works.  You say you clear LOCK, but do you also clear POWERDN?  How about the step to set CLKRZ before clearing?  Your code only has the clear, then set, then poll.

If you try the exact step below, but still no luck, then you may be right about a HW layout problem.  The DDR2 layout is very picky, and there are a couple of documents that specify exactly how the PCB layout should be between the C6748 and the DDR2.

/* Step 3 - VTP calibration */

VTPIO_CTL &= ~0x00000040; // Clear POWERDN

VTPIO_CTL &= ~0x00000080; // Clear LOCK

VTPIO_CTL |= 0x00002000; // Set CLKRZ in case it was cleared before (VTP looks for CLKRZ edge transition)

VTPIO_CTL &= ~0x00002000; // Clear CLKRZ (Use read-modify-write to ensure 1 VTP cycle wait for previous instruction)

VTPIO_CTL |= 0x00002000; // Set CLKRZ (Use read-modify-write to ensure 1 VTP cycle wait for previous instruction)

while( (VTPIO_CTL & 0x00008000) == 0 )

{

/* Wait for ready bit */

}

- Dean