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Tool/software:
Hello
I have a custom board with a TDA4AL and 2GB of RAM. It's running a modified PSDK Linux 10.
I've successfully modified linux and u-boot to handle 2GB of RAM. I'm trying to modify the vision-apps package with a new memory map that fits in the 2GB. Memory map generation proceeds without issue, and I was able to apply the device tree overlay and deploy the modified vision-apps library. However, at runtime when I try to run TIOVX powered applications, I get the following errors:
APP: Init ... !!! 759.971222 s: MEM: Init ... !!! 759.971322 s: MEM: Initialized DMA HEAP (fd=5) !!! 759.971672 s: MEM: Init ... Done !!! 759.971709 s: IPC: Init ... !!! _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio0.rpmsg_chrdev.-1.13 _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio1.rpmsg_chrdev.-1.13 760.013731 s: IPC: ERROR: Unable to create TX channels for CPU [c7x_1] !!! 760.013753 s: IPC: ERROR: Unable to create TX channels for CPU [c7x_2] !!! 760.013759 s: IPC: Init ... Done !!! APP: ERROR: IPC init failed !!! REMOTE_SERVICE: Init ... !!! _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio3.rpmsg_chrdev.-1.21 _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio4.rpmsg_chrdev.-1.21 _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio0.rpmsg_chrdev.-1.21 _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio1.rpmsg_chrdev.-1.21 REMOTE_SERVICE: Init ... Done !!! 760.021440 s: GTC Frequency = 200 MHz APP: Init ... Done !!! 760.032273 s: VX_ZONE_INIT:Enabled 760.032305 s: VX_ZONE_ERROR:Enabled 760.032320 s: VX_ZONE_WARNING:Enabled 760.050353 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MPU-0 760.050556 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MPU-1 760.050838 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MPU-2 760.051026 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MPU-3 760.051045 s: VX_ZONE_INIT:[tivxInitLocal:136] Initialization Done !!! 760.057180 s: VX_ZONE_INIT:[tivxHostInitLocal:106] Initialization Done for HOST !!! InitDone 760.058222 s: VX_ZONE_ERROR:[ownContextCreateCmdObj:160] context object descriptor [0] allocation failed 760.058245 s: VX_ZONE_ERROR:[ownContextCreateCmdObj:163] context object descriptor [0] allocation failed 760.058261 s: VX_ZONE_ERROR:[ownContextCreateCmdObj:164] Exceeded max object descriptors available. Increase TIVX_PLATFORM_MAX_OBJ_DESC_SHM_INST value 760.058271 s: VX_ZONE_ERROR:[ownContextCreateCmdObj:165] Increase TIVX_PLATFORM_MAX_OBJ_DESC_SHM_INST value in source/platform/psdk_j7/common/soc/tivx_platform_psdk_<soc>.h 760.058311 s: VX_ZONE_ERROR:[vxCreateContext:1062] context objection creation failed 760.058373 s: VX_ZONE_ERROR:[ownIsKernelInContext:667] Failed to lock context 760.058392 s: VX_ZONE_ERROR:[ownGetErrorObject:55] Failed to lock context 760.058405 s: VX_ZONE_ERROR:[vxGetStatus:1025] Reference is NULL 760.058415 s: VX_ZONE_ERROR:[vxLoadKernels:207] Publish function for module openvx-core failed
Output of vx_app_arm_remote_log.out:
[MCU2_0] 4.386927 s: CIO: Init ... Done !!! [MCU2_0] 4.386982 s: ### CPU Frequency = 1000000000 Hz [MCU2_0] 4.387007 s: CPU is running FreeRTOS [MCU2_0] 4.387024 s: APP: Init ... !!! [MCU2_0] 4.387057 s: SCICLIENT: Init ... !!! [MCU2_0] 4.387174 s: SCICLIENT: DMSC FW version [10.0.8--v10.00.08 (Fiery Fox)] [MCU2_0] 4.387203 s: SCICLIENT: DMSC FW revision 0xa [MCU2_0] 4.387222 s: SCICLIENT: DMSC FW ABI revision 4.0 [MCU2_0] 4.387243 s: SCICLIENT: Init ... Done !!! [MCU2_0] 4.387262 s: UDMA: Init ... !!! [MCU2_0] 4.388087 s: UDMA: Init ... Done !!! [MCU2_0] 4.388122 s: UDMA: Init for CSITX/CSIRX ... !!! [MCU2_0] 4.388540 s: UDMA: Init for CSITX/CSIRX ... Done !!! [MCU2_0] 4.388571 s: MEM: Init ... !!! [MCU2_0] 4.388595 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ b9000000 of size 14680064 bytes !!! [MCU2_0] 4.388635 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 60000000 of size 524288 bytes !!! [MCU2_0] 4.388670 s: MEM: Created heap (DDR_CACHE_WT_MEM, id=7, flags=0x00000000) @ b9e00000 of size 2097152 bytes !!! [MCU2_0] 4.388707 s: MEM: Init ... Done !!! [MCU2_0] 4.388724 s: IPC: Init ... !!! [MCU2_0] 4.388754 s: IPC: 5 CPUs participating in IPC !!! [MCU2_0] 4.388789 s: IPC: Waiting for HLOS to be ready ... !!! [MCU2_0] 16.574421 s: IPC: HLOS is ready !!! [MCU2_0] 16.577247 s: IPC: Init ... Done !!! [MCU2_0] 16.577282 s: APP: Syncing with 4 CPUs ... !!! [MCU2_1] 4.499385 s: CIO: Init ... Done !!! [MCU2_1] 4.499443 s: ### CPU Frequency = 1000000000 Hz [MCU2_1] 4.499467 s: CPU is running FreeRTOS [MCU2_1] 4.499484 s: APP: Init ... !!! [MCU2_1] 4.499517 s: SCICLIENT: Init ... !!! [MCU2_1] 4.499636 s: SCICLIENT: DMSC FW version [10.0.8--v10.00.08 (Fiery Fox)] [MCU2_1] 4.499665 s: SCICLIENT: DMSC FW revision 0xa [MCU2_1] 4.499686 s: SCICLIENT: DMSC FW ABI revision 4.0 [MCU2_1] 4.499707 s: SCICLIENT: Init ... Done !!! [MCU2_1] 4.499726 s: UDMA: Init ... !!! [MCU2_1] 4.500560 s: UDMA: Init ... Done !!! [MCU2_1] 4.500590 s: MEM: Init ... !!! [MCU2_1] 4.500614 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ ba000000 of size 16777216 bytes !!! [MCU2_1] 4.500653 s: MEM: Init ... Done !!! [MCU2_1] 4.500669 s: IPC: Init ... !!! [MCU2_1] 4.500706 s: IPC: 5 CPUs participating in IPC !!! [MCU2_1] 4.500733 s: IPC: Waiting for HLOS to be ready ... !!! [MCU2_1] 16.694261 s: IPC: HLOS is ready !!! [MCU2_1] 16.697056 s: IPC: Init ... Done !!! [MCU2_1] 16.697095 s: APP: Syncing with 4 CPUs ... !!! [C7x_1 ] 5.084891 s: CIO: Init ... Done !!! [C7x_1 ] 5.084909 s: ### CPU Frequency = 1000000000 Hz [C7x_1 ] 5.084922 s: CPU is running FreeRTOS [C7x_1 ] 5.084932 s: APP: Init ... !!! [C7x_1 ] 5.084941 s: SCICLIENT: Init ... !!! [C7x_1 ] 5.085044 s: SCICLIENT: DMSC FW version [10.0.8--v10.00.08 (Fiery Fox)] [C7x_1 ] 5.085059 s: SCICLIENT: DMSC FW revision 0xa [C7x_1 ] 5.085070 s: SCICLIENT: DMSC FW ABI revision 4.0 [C7x_1 ] 5.085083 s: SCICLIENT: Init ... Done !!! [C7x_1 ] 5.085093 s: UDMA: Init ... !!! [C7x_1 ] 5.085850 s: UDMA: Init ... Done !!! [C7x_1 ] 5.085866 s: MEM: Init ... !!! [C7x_1 ] 5.085881 s: A0 =0xfffff00 A1 =0x17000000 [C7x_1 ] 5.085895 s: A2 =0x1 A3 =0xaa01c020 [C7x_1 ] 5.085906 s: A4 =0xb10afb18 A5 =0x17000000 [C7x_1 ] 5.085917 s: A6 =0x10000000 A7 =0x0 [C7x_1 ] 5.085928 s: A8 =0xb10afb10 A9 =0xb06e7ba8 [C7x_1 ] 5.085939 s: A10=0xb0decbe4 A11=0xb10aea30 [C7x_1 ] 5.085949 s: A12=0xb10aea34 A13=0x0 [C7x_1 ] 5.085960 s: A14=0xb0b2873c A15=0xb06e7e38 [C7x_1 ] 5.085970 s: D0 =0x26ffff00 D1 =0xb108e980 [C7x_1 ] 5.085981 s: D2 =0xb10b0af0 D3 =0x22d [C7x_1 ] 5.085991 s: D4 =0xb06e7790 D5 =0xb06e7790 [C7x_1 ] 5.086002 s: D6 =0xb06e7790 D7 =0xb06e7790 [C7x_1 ] 5.086013 s: D8 =0xb0e51480 D9 =0xb0e3a840 [C7x_1 ] 5.086024 s: D10=0xb0e3a780 D11=0x8110820 [C7x_1 ] 5.086035 s: D12=0x8d615a0 D13=0xb06e77c6 [C7x_1 ] 5.086045 s: D14=0x30 D15=0xb06e7ad8 [C7x_1 ] 5.086055 s: AM0=0x0 AM1=0x38 [C7x_1 ] 5.086064 s: AM2=0x18 AM3=0x1c90e4c0 [C7x_1 ] 5.086074 s: AM4=0xe4bb1830 AM5=0x32de46b2 [C7x_1 ] 5.086084 s: AM6=0x6ca71bf4 AM7=0x18 [C7x_1 ] 5.086095 s: AL0=0x26ffff00 AL1=0xffffff00 [C7x_1 ] 5.086106 s: AL2=0xb0e4c180 AL3=0x0 [C7x_1 ] 5.086115 s: AL4=0x0 AL5=0x190fe481 [C7x_1 ] 5.086125 s: AL6=0x6b0349c8 AL7=0x38 [C7x_1 ] 5.086135 s: P0=0xffffffff P1=0xffffffff [C7x_1 ] 5.086145 s: P2=0xa40d4bb7 P3=0x854e1b1 [C7x_1 ] 5.086155 s: P4=0x11405097 P5=0x4d760ab0 [C7x_1 ] 5.086166 s: P6=0x5120a604 P7=0x703841f5 [C7x_1 ] 5.086176 s: FPCR=0x10 FSR=0x0 [C7x_1 ] 5.086185 s: GFPGFR=0x700001d GPLY=0x0 [C7x_1 ] 5.086196 s: [C7x_1 ] VBM0=0xb10ffa40 [0] [C7x_1 ] 5.086206 s: [C7x_1 ] =0xb10ffa40 [0] [C7x_1 ] 5.086216 s: 0x0 [1] [C7x_1 ] 5.086224 s: 0x0 [2] [C7x_1 ] 5.086232 s: 0x0 [3] [C7x_1 ] 5.086240 s: 0x0 [4] [C7x_1 ] 5.086247 s: 0x0 [5] [C7x_1 ] 5.086257 s: 0x0 [6] [C7x_1 ] 5.086264 s: 0x0 [7] [C7x_1 ] 5.086272 s: 0x1f6f3708 [1] [C7x_1 ] 5.086281 s: 0xeec502 [2] [C7x_1 ] 5.086290 s: 0x1884121 [3] [C7x_1 ] 5.086298 s: 0x9cd8b481 [4] [C7x_1 ] 5.086307 s: 0x220ccae8 [5] [C7x_1 ] 5.086316 s: 0x18252733 [6] [C7x_1 ] 5.086325 s: 0x242bb539 [7] [C7x_1 ] 5.086334 s: [C7x_1 ] VBM2=0xb10ff9c0 [0] [C7x_1 ] 5.086343 s: [C7x_1 ] =0xb10ff9c0 [0] [C7x_1 ] 5.086352 s: 0x45202a7 [1] [C7x_1 ] 5.086361 s: 0xe0805240 [2] [C7x_1 ] 5.086370 s: 0xd6ab4286 [3] [C7x_1 ] 5.086378 s: 0xab8ae000 [4] [C7x_1 ] 5.086387 s: 0xb3a40490 [5] [C7x_1 ] 5.086396 s: 0x420167f0 [6] [C7x_1 ] 5.086405 s: 0x80180951 [7] [C7x_1 ] 5.086413 s: 0x206c07 [1] [C7x_1 ] 5.086422 s: 0x1c6086 [2] [C7x_1 ] 5.086430 s: 0x48a9d25 [3] [C7x_1 ] 5.086439 s: 0x81244627 [4] [C7x_1 ] 5.086448 s: 0x1420504 [5] [C7x_1 ] 5.086457 s: 0x90a40988 [6] [C7x_1 ] 5.086466 s: 0x8db5c59c [7] [C7x_1 ] 5.086475 s: [C7x_1 ] =0xb10ff940 [0] [C7x_1 ] 5.086484 s: [C7x_1 ] =0xb10ff940 [0] [C7x_1 ] 5.086493 s: 0x4a2c273c [1] [C7x_1 ] 5.086502 s: 0x68ce41f0 [2] [C7x_1 ] 5.086511 s: 0x20baa03 [3] [C7x_1 ] 5.086519 s: 0xccac364c [4] [C7x_1 ] 5.086528 s: 0x3872548 [5] [C7x_1 ] 5.086537 s: 0x3518271c [6] [C7x_1 ] 5.086546 s: 0x1830842 [7] [C7x_1 ] 5.086554 s: 0x218a85b4 [1] [C7x_1 ] 5.086563 s: 0x12116301 [2] [C7x_1 ] 5.086572 s: 0xd26ae8d6 [3] [C7x_1 ] 5.086581 s: 0x9104f103 [4] [C7x_1 ] 5.086589 s: 0x864a0656 [5] [C7x_1 ] 5.086598 s: 0x2022e205 [6] [C7x_1 ] 5.086607 s: 0x91989c5a [7] [C7x_1 ] 5.086616 s: [C7x_1 ] =0xb10ff8c0 [0] [C7x_1 ] 5.086625 s: [C7x_1 ] =0xb10ff8c0 [0] [C7x_1 ] 5.086634 s: 0x61144115 [1] [C7x_1 ] 5.086643 s: 0x561e86 [2] [C7x_1 ] 5.086652 s: 0x29252032 [3] [C7x_1 ] 5.086660 s: 0x29022a0 [4] [C7x_1 ] 5.086669 s: 0xa9697c30 [5] [C7x_1 ] 5.086678 s: 0xa1a0ea04 [6] [C7x_1 ] 5.086687 s: 0x191249d8 [7] [C7x_1 ] 5.086696 s: 0x28415a40 [1] [C7x_1 ] 5.086704 s: 0x41529078 [2] [C7x_1 ] 5.086713 s: 0x5416624c [3] [C7x_1 ] 5.086722 s: 0x80b00019 [4] [C7x_1 ] 5.086730 s: 0x50a30086 [5] [C7x_1 ] 5.086739 s: 0x70061c0c [6] [C7x_1 ] 5.086748 s: 0x4644c149 [7] [C7x_1 ] 5.086757 s: [C7x_1 ] VBL0=0xb10ff840 [0] [C7x_1 ] 5.086766 s: [C7x_1 ] =0xb10ff840 [0] [C7x_1 ] 5.086775 s: 0x0 [1] [C7x_1 ] 5.086784 s: 0x0 [2] [C7x_1 ] 5.086792 s: 0x0 [3] [C7x_1 ] 5.086800 s: 0x0 [4] [C7x_1 ] 5.086808 s: 0x0 [5] [C7x_1 ] 5.086816 s: 0x0 [6] [C7x_1 ] 5.086824 s: 0x0 [7] [C7x_1 ] 5.086832 s: 0x40 [1] [C7x_1 ] 5.086841 s: 0x40 [2] [C7x_1 ] 5.086849 s: 0x40 [3] [C7x_1 ] 5.086857 s: 0x40 [4] [C7x_1 ] 5.086865 s: 0x40 [5] [C7x_1 ] 5.086874 s: 0x40 [6] [C7x_1 ] 5.086882 s: 0x40 [7] [C7x_1 ] 5.086890 s: [C7x_1 ] =0xb10ff7c0 [0] [C7x_1 ] 5.086899 s: [C7x_1 ] =0xb10ff7c0 [0] [C7x_1 ] 5.086908 s: 0xd45b9b69 [1] [C7x_1 ] 5.086917 s: 0x11c3487e [2] [C7x_1 ] 5.086926 s: 0x19180a3c [3] [C7x_1 ] 5.086935 s: 0x90711001 [4] [C7x_1 ] 5.086944 s: 0xa2e0c613 [5] [C7x_1 ] 5.086952 s: 0x6ec88320 [6] [C7x_1 ] 5.086961 s: 0x819817e0 [7] [C7x_1 ] 5.086970 s: 0x212223 [1] [C7x_1 ] 5.086979 s: 0x22790705 [2] [C7x_1 ] 5.086987 s: 0xbe10a25e [3] [C7x_1 ] 5.086996 s: 0x33864010 [4] [C7x_1 ] 5.087005 s: 0xbd402713 [5] [C7x_1 ] 5.087014 s: 0x2110000 [6] [C7x_1 ] 5.087022 s: 0x7cc90600 [7] [C7x_1 ] 5.087032 s: [C7x_1 ] VBL4=0xb10ff740 [0] [C7x_1 ] 5.087041 s: [C7x_1 ] =0xb10ff740 [0] [C7x_1 ] 5.087051 s: 0x3634e313 [1] [C7x_1 ] 5.087059 s: 0xb0d12d29 [2] [C7x_1 ] 5.087068 s: 0x1c98614e [3] [C7x_1 ] 5.087077 s: 0x80e22103 [4] [C7x_1 ] 5.087086 s: 0x4200d005 [5] [C7x_1 ] 5.087094 s: 0x14d24626 [6] [C7x_1 ] 5.087103 s: 0xa688bd12 [7] [C7x_1 ] 5.087112 s: 0x818ca5c2 [1] [C7x_1 ] 5.087121 s: 0x1a36188a [2] [C7x_1 ] 5.087129 s: 0x8082d802 [3] [C7x_1 ] 5.087138 s: 0xcdca897e [4] [C7x_1 ] 5.087147 s: 0x54c11119 [5] [C7x_1 ] 5.087156 s: 0xa4bb4608 [6] [C7x_1 ] 5.087165 s: 0x3d201074 [7] [C7x_1 ] 5.087173 s: [C7x_1 ] =0xb10ff6c0 [0] [C7x_1 ] 5.087182 s: [C7x_1 ] VBL7=0xb10ff6c0 [0] [C7x_1 ] 5.087191 s: 0xed464422 [1] [C7x_1 ] 5.087200 s: 0xe4e2e415 [2] [C7x_1 ] 5.087209 s: 0x12514108 [3] [C7x_1 ] 5.087218 s: 0x61143508 [4] [C7x_1 ] 5.087227 s: 0x6305892 [5] [C7x_1 ] 5.087236 s: 0x829da08c [6] [C7x_1 ] 5.087244 s: 0x63c14675 [7] [C7x_1 ] 5.087253 s: 0x4f88d078 [1] [C7x_1 ] 5.087262 s: 0xab018a4 [2] [C7x_1 ] 5.087271 s: 0x1840021 [3] [C7x_1 ] 5.087279 s: 0x5110b [4] [C7x_1 ] 5.087288 s: 0xa191e04 [5] [C7x_1 ] 5.087297 s: 0x38c2a80a [6] [C7x_1 ] 5.087306 s: 0xc2e81062 [7] [C7x_1 ] 5.087315 s: [C7x_1 ] VB0=0xb10ffe40 [0] [C7x_1 ] 5.087324 s: [C7x_1 ] =0xb10ffe40 [0] [C7x_1 ] 5.087333 s: 0x0 [1] [C7x_1 ] 5.087341 s: 0x0 [2] [C7x_1 ] 5.087349 s: 0x0 [3] [C7x_1 ] 5.087357 s: 0x0 [4] [C7x_1 ] 5.087364 s: 0x0 [5] [C7x_1 ] 5.087372 s: 0x0 [6] [C7x_1 ] 5.087380 s: 0x0 [7] [C7x_1 ] 5.087388 s: 0x40 [1] [C7x_1 ] 5.087397 s: 0x40 [2] [C7x_1 ] 5.087405 s: 0x0 [3] [C7x_1 ] 5.087413 s: 0x0 [4] [C7x_1 ] 5.087421 s: 0x0 [5] [C7x_1 ] 5.087429 s: 0x0 [6] [C7x_1 ] 5.087437 s: 0x40 [7] [C7x_1 ] 5.087445 s: [C7x_1 ] =0xb10ffdc0 [0] [C7x_1 ] 5.087454 s: [C7x_1 ] VB3=0xb10ffdc0 [0] [C7x_1 ] 5.087463 s: 0x8 [1] [C7x_1 ] 5.087471 s: 0xc [2] [C7x_1 ] 5.087479 s: 0x0 [3] [C7x_1 ] 5.087487 s: 0x30009 [4] [C7x_1 ] 5.087496 s: 0x3 [5] [C7x_1 ] 5.087504 s: 0x0 [6] [C7x_1 ] 5.087512 s: 0xb0e4c380 [7] [C7x_1 ] 5.087521 s: 0x4 [1] [C7x_1 ] 5.087529 s: 0x0 [2] [C7x_1 ] 5.087537 s: 0x0 [3] [C7x_1 ] 5.087545 s: 0x0 [4] [C7x_1 ] 5.087553 s: 0x0 [5] [C7x_1 ] 5.087561 s: 0x0 [6] [C7x_1 ] 5.087569 s: 0x20 [7] [C7x_1 ] 5.087577 s: [C7x_1 ] VB4=0xb10ffd40 [0] [C7x_1 ] 5.087586 s: [C7x_1 ] VB5=0xb10ffd40 [0] [C7x_1 ] 5.087596 s: 0x0 [1] [C7x_1 ] 5.087604 s: 0x0 [2] [C7x_1 ] 5.087612 s: 0x2 [3] [C7x_1 ] 5.087619 s: 0x0 [4] [C7x_1 ] 5.087627 s: 0x0 [5] [C7x_1 ] 5.087635 s: 0x4 [6] [C7x_1 ] 5.087644 s: 0x0 [7] [C7x_1 ] 5.087652 s: 0x80002120 [1] [C7x_1 ] 5.087661 s: 0x329d82b2 [2] [C7x_1 ] 5.087670 s: 0x12d99464 [3] [C7x_1 ] 5.087678 s: 0x8007c004 [4] [C7x_1 ] 5.087687 s: 0xc1402ac7 [5] [C7x_1 ] 5.087696 s: 0x2e1628c8 [6] [C7x_1 ] 5.087705 s: 0x92254900 [7] [C7x_1 ] 5.087713 s: [C7x_1 ] VB6=0xb10ffcc0 [0] [C7x_1 ] 5.087723 s: [C7x_1 ] VB7=0xb10ffcc0 [0] [C7x_1 ] 5.087732 s: 0x8686cc00 [1] [C7x_1 ] 5.087741 s: 0xfa1fcc6f [2] [C7x_1 ] 5.087749 s: 0x45083598 [3] [C7x_1 ] 5.087758 s: 0x50553573 [4] [C7x_1 ] 5.087767 s: 0x92d22050 [5] [C7x_1 ] 5.087776 s: 0xb72c4c6a [6] [C7x_1 ] 5.087784 s: 0x18110445 [7] [C7x_1 ] 5.087793 s: 0x125a01f0 [1] [C7x_1 ] 5.087802 s: 0x2a0e4c00 [2] [C7x_1 ] 5.087811 s: 0x220110f0 [3] [C7x_1 ] 5.087820 s: 0xa4dc1713 [4] [C7x_1 ] 5.087828 s: 0xd3b4021 [5] [C7x_1 ] 5.087837 s: 0xee1821d5 [6] [C7x_1 ] 5.087846 s: 0xe8481482 [7] [C7x_1 ] 5.087855 s: [C7x_1 ] =0xb10ffc40 [0] [C7x_1 ] 5.087864 s: [C7x_1 ] =0xb10ffc40 [0] [C7x_1 ] 5.087873 s: 0x21a48a1c [1] [C7x_1 ] 5.087882 s: 0x8d74c084 [2] [C7x_1 ] 5.087891 s: 0x1b3ada85 [3] [C7x_1 ] 5.087899 s: 0x100025d1 [4] [C7x_1 ] 5.087908 s: 0xac101591 [5] [C7x_1 ] 5.087917 s: 0x1b4953a [6] [C7x_1 ] 5.087925 s: 0x474ab94 [7] [C7x_1 ] 5.087934 s: 0xc8028406 [1] [C7x_1 ] 5.087943 s: 0x239ff7aa [2] [C7x_1 ] 5.087952 s: 0x8ce1bbc2 [3] [C7x_1 ] 5.087961 s: 0xc0360043 [4] [C7x_1 ] 5.087969 s: 0x8846490c [5] [C7x_1 ] 5.087978 s: 0x1800ec99 [6] [C7x_1 ] 5.087987 s: 0xc238ae08 [7] [C7x_1 ] 5.087996 s: [C7x_1 ] =0xb10ffbc0 [0] [C7x_1 ] 5.088005 s: [C7x_1 ] =0xb10ffbc0 [0] [C7x_1 ] 5.088014 s: 0x49842405 [1] [C7x_1 ] 5.088022 s: 0xe1d55fae [2] [C7x_1 ] 5.088031 s: 0x52498d6c [3] [C7x_1 ] 5.088040 s: 0x7816ae8 [4] [C7x_1 ] 5.088049 s: 0x51c80261 [5] [C7x_1 ] 5.088058 s: 0x196ea620 [6] [C7x_1 ] 5.088067 s: 0x58481660 [7] [C7x_1 ] 5.088075 s: 0x2d740327 [1] [C7x_1 ] 5.088084 s: 0x907bc010 [2] [C7x_1 ] 5.088093 s: 0x253dd400 [3] [C7x_1 ] 5.088102 s: 0xa10b9210 [4] [C7x_1 ] 5.088110 s: 0x1cb56002 [5] [C7x_1 ] 5.088119 s: 0x86817c70 [6] [C7x_1 ] 5.088128 s: 0x812a5252 [7] [C7x_1 ] 5.088137 s: [C7x_1 ] =0xb10ffb40 [0] [C7x_1 ] 5.088146 s: [C7x_1 ] VB13=0xb10ffb40 [0] [C7x_1 ] 5.088155 s: 0x40d06081 [1] [C7x_1 ] 5.088164 s: 0xe4e43d08 [2] [C7x_1 ] 5.088173 s: 0x1604131d [3] [C7x_1 ] 5.088182 s: 0x3840a [4] [C7x_1 ] 5.088190 s: 0x58200141 [5] [C7x_1 ] 5.088199 s: 0xa000a089 [6] [C7x_1 ] 5.088208 s: 0xa1fa79ac [7] [C7x_1 ] 5.088217 s: 0x300178 [1] [C7x_1 ] 5.088225 s: 0xf1402653 [2] [C7x_1 ] 5.088234 s: 0x21a1210c [3] [C7x_1 ] 5.088243 s: 0x27c0a206 [4] [C7x_1 ] 5.088252 s: 0x46c9a0 [5] [C7x_1 ] 5.088260 s: 0x836a6180 [6] [C7x_1 ] 5.088269 s: 0x46902042 [7] [C7x_1 ] 5.088278 s: [C7x_1 ] =0xb10ffac0 [0] [C7x_1 ] 5.088287 s: [C7x_1 ] VB15=0xb10ffac0 [0] [C7x_1 ] 5.088297 s: 0xb921cd8c [1] [C7x_1 ] 5.088306 s: 0x4fe6406e [2] [C7x_1 ] 5.088315 s: 0x2c442930 [3] [C7x_1 ] 5.088324 s: 0x42082214 [4] [C7x_1 ] 5.088332 s: 0x94806403 [5] [C7x_1 ] 5.088341 s: 0x4844100 [6] [C7x_1 ] 5.088350 s: 0xc2848901 [7] [C7x_1 ] 5.088359 s: 0xa4c22b26 [1] [C7x_1 ] 5.088367 s: 0x602df484 [2] [C7x_1 ] 5.088376 s: 0x103261 [3] [C7x_1 ] 5.088385 s: 0x21404b82 [4] [C7x_1 ] 5.088394 s: 0x1886c01e [5] [C7x_1 ] 5.088402 s: 0x441018b [6] [C7x_1 ] 5.088411 s: 0x75444900 [7] [C7x_1 ] 5.088420 s: [C7x_1 ] CUCR0=0xb10ff640 [0] [C7x_1 ] 5.088429 s: [C7x_1 ] CUCR1=0xb10ff640 [0] [C7x_1 ] 5.088439 s: 0x0 [1] [C7x_1 ] 5.088447 s: 0x0 [2] [C7x_1 ] 5.088455 s: 0x0 [3] [C7x_1 ] 5.088463 s: 0x0 [4] [C7x_1 ] 5.088471 s: 0x0 [5] [C7x_1 ] 5.088479 s: 0x0 [6] [C7x_1 ] 5.088487 s: 0x0 [7] [C7x_1 ] 5.088495 s: 0x0 [1] [C7x_1 ] 5.088503 s: 0x0 [2] [C7x_1 ] 5.088511 s: 0x0 [3] [C7x_1 ] 5.088519 s: 0x0 [4] [C7x_1 ] 5.088527 s: 0x0 [5] [C7x_1 ] 5.088535 s: 0x0 [6] [C7x_1 ] 5.088543 s: 0x0 [7] [C7x_1 ] 5.088551 s: [C7x_1 ] CUCR2=0xb10ff5c0 [0] [C7x_1 ] 5.088561 s: [C7x_1 ] CUCR3=0xb10ff5c0 [0] [C7x_1 ] 5.088570 s: 0x0 [1] [C7x_1 ] 5.088578 s: 0x0 [2] [C7x_1 ] 5.088586 s: 0x0 [3] [C7x_1 ] 5.088594 s: 0x0 [4] [C7x_1 ] 5.088602 s: 0x0 [5] [C7x_1 ] 5.088610 s: 0x0 [6] [C7x_1 ] 5.088618 s: 0x0 [7] [C7x_1 ] 5.088626 s: 0x0 [1] [C7x_1 ] 5.088634 s: 0x0 [2] [C7x_1 ] 5.088642 s: 0x0 [3] [C7x_1 ] 5.088650 s: 0x0 [4] [C7x_1 ] 5.088658 s: 0x0 [5] [C7x_1 ] 5.088666 s: 0x0 [6] [C7x_1 ] 5.088674 s: 0x0 [7] [C7x_1 ] 5.088682 s: [C7x_1 ] SE0_0=0xb10ff180 [0] [C7x_1 ] 5.088692 s: [C7x_1 ] SE0_1=0xb10ff180 [0] [C7x_1 ] 5.088701 s: 0x0 [1] [C7x_1 ] 5.088709 s: 0x0 [2] [C7x_1 ] 5.088717 s: 0x0 [3] [C7x_1 ] 5.088725 s: 0x0 [4] [C7x_1 ] 5.088733 s: 0x0 [5] [C7x_1 ] 5.088741 s: 0x0 [6] [C7x_1 ] 5.088749 s: 0x0 [7] [C7x_1 ] 5.088757 s: 0x0 [1] [C7x_1 ] 5.088765 s: 0x0 [2] [C7x_1 ] 5.088773 s: 0x0 [3] [C7x_1 ] 5.088781 s: 0x0 [4] [C7x_1 ] 5.088789 s: 0x0 [5] [C7x_1 ] 5.088797 s: 0x0 [6] [C7x_1 ] 5.088805 s: 0x0 [7] [C7x_1 ] 5.088813 s: [C7x_1 ] SE0_2=0xb10ff200 [0] [C7x_1 ] 5.088822 s: [C7x_1 ] SE0_3=0xb10ff200 [0] [C7x_1 ] 5.088832 s: 0x0 [1] [C7x_1 ] 5.088840 s: 0x0 [2] [C7x_1 ] 5.088848 s: 0x0 [3] [C7x_1 ] 5.088856 s: 0x0 [4] [C7x_1 ] 5.088864 s: 0x0 [5] [C7x_1 ] 5.088872 s: 0x0 [6] [C7x_1 ] 5.088880 s: 0x0 [7] [C7x_1 ] 5.088888 s: 0x0 [1] [C7x_1 ] 5.088896 s: 0x0 [2] [C7x_1 ] 5.088904 s: 0x0 [3] [C7x_1 ] 5.088912 s: 0x0 [4] [C7x_1 ] 5.088920 s: 0x0 [5] [C7x_1 ] 5.088928 s: 0x0 [6] [C7x_1 ] 5.088936 s: 0x0 [7] [C7x_1 ] 5.088944 s: [C7x_1 ] SE1_0=0xb10ff280 [0] [C7x_1 ] 5.088954 s: [C7x_1 ] SE1_1=0xb10ff280 [0] [C7x_1 ] 5.088963 s: 0x0 [1] [C7x_1 ] 5.088971 s: 0x0 [2] [C7x_1 ] 5.088980 s: 0x0 [3] [C7x_1 ] 5.088987 s: 0x0 [4] [C7x_1 ] 5.088995 s: 0x0 [5] [C7x_1 ] 5.089003 s: 0x0 [6] [C7x_1 ] 5.089011 s: 0x0 [7] [C7x_1 ] 5.089019 s: 0x0 [1] [C7x_1 ] 5.089028 s: 0x0 [2] [C7x_1 ] 5.089036 s: 0x0 [3] [C7x_1 ] 5.089044 s: 0x0 [4] [C7x_1 ] 5.089052 s: 0x0 [5] [C7x_1 ] 5.089059 s: 0x0 [6] [C7x_1 ] 5.089067 s: 0x0 [7] [C7x_1 ] 5.089075 s: [C7x_1 ] SE1_2=0xb10ff300 [0] [C7x_1 ] 5.089085 s: [C7x_1 ] SE1_3=0xb10ff300 [0] [C7x_1 ] 5.089095 s: 0x0 [1] [C7x_1 ] 5.089103 s: 0x0 [2] [C7x_1 ] 5.089111 s: 0x0 [3] [C7x_1 ] 5.089119 s: 0x0 [4] [C7x_1 ] 5.089127 s: 0x0 [5] [C7x_1 ] 5.089135 s: 0x0 [6] [C7x_1 ] 5.089143 s: 0x0 [7] [C7x_1 ] 5.089151 s: 0x0 [1] [C7x_1 ] 5.089159 s: 0x0 [2] [C7x_1 ] 5.089167 s: 0x0 [3] [C7x_1 ] 5.089175 s: 0x0 [4] [C7x_1 ] 5.089183 s: 0x0 [5] [C7x_1 ] 5.089191 s: 0x0 [6] [C7x_1 ] 5.089199 s: 0x0 [7] [C7x_1 ] 5.089207 s: [C7x_1 ] SA0CR=0xb10ff440 [0] [C7x_1 ] 5.089217 s: [C7x_1 ] SA1CR=0xb10ff440 [0] [C7x_1 ] 5.089226 s: 0x0 [1] [C7x_1 ] 5.089234 s: 0x0 [2] [C7x_1 ] 5.089242 s: 0x0 [3] [C7x_1 ] 5.089250 s: 0x0 [4] [C7x_1 ] 5.089258 s: 0x0 [5] [C7x_1 ] 5.089266 s: 0x0 [6] [C7x_1 ] 5.089274 s: 0x0 [7] [C7x_1 ] 5.089282 s: 0x0 [1] [C7x_1 ] 5.089290 s: 0x0 [2] [C7x_1 ] 5.089297 s: 0x0 [3] [C7x_1 ] 5.089306 s: 0x0 [4] [C7x_1 ] 5.089314 s: 0x0 [5] [C7x_1 ] 5.089322 s: 0x0 [6] [C7x_1 ] 5.089330 s: 0x0 [7] [C7x_1 ] 5.089338 s: [C7x_1 ] SA2CR=0xb10ff3c0 [0] [C7x_1 ] 5.089347 s: [C7x_1 ] SA3CR=0xb10ff3c0 [0] [C7x_1 ] 5.089357 s: 0x0 [1] [C7x_1 ] 5.089365 s: 0x0 [2] [C7x_1 ] 5.089373 s: 0x0 [3] [C7x_1 ] 5.089381 s: 0x0 [4] [C7x_1 ] 5.089389 s: 0x0 [5] [C7x_1 ] 5.089396 s: 0x0 [6] [C7x_1 ] 5.089404 s: 0x0 [7] [C7x_1 ] 5.089412 s: 0x0 [1] [C7x_1 ] 5.089421 s: 0x0 [2] [C7x_1 ] 5.089429 s: 0x0 [3] [C7x_1 ] 5.089437 s: 0x0 [4] [C7x_1 ] 5.089445 s: 0x0 [5] [C7x_1 ] 5.089453 s: 0x0 [6] [C7x_1 ] 5.089460 s: 0x0 [7] [C7x_1 ] 5.089468 s: [C7x_1 ] SA0CNTR0=0xb10ff540 [0] [C7x_1 ] 5.089478 s: [C7x_1 ] SA1CNTR0=0xb10ff540 [0] [C7x_1 ] 5.089488 s: 0x0 [1] [C7x_1 ] 5.089496 s: 0x0 [2] [C7x_1 ] 5.089505 s: 0x0 [3] [C7x_1 ] 5.089513 s: 0x0 [4] [C7x_1 ] 5.089520 s: 0x0 [5] [C7x_1 ] 5.089528 s: 0x0 [6] [C7x_1 ] 5.089536 s: 0x0 [7] [C7x_1 ] 5.089544 s: 0x0 [1] [C7x_1 ] 5.089552 s: 0x0 [2] [C7x_1 ] 5.089560 s: 0x0 [3] [C7x_1 ] 5.089568 s: 0x0 [4] [C7x_1 ] 5.089576 s: 0x0 [5] [C7x_1 ] 5.089584 s: 0x0 [6] [C7x_1 ] 5.089592 s: 0x0 [7] [C7x_1 ] 5.089600 s: [C7x_1 ] SA2CNTR0=0xb10ff4c0 [0] [C7x_1 ] 5.089610 s: [C7x_1 ] SA3CNTR0=0xb10ff4c0 [0] [C7x_1 ] 5.089620 s: 0x0 [1] [C7x_1 ] 5.089628 s: 0x0 [2] [C7x_1 ] 5.089635 s: 0x0 [3] [C7x_1 ] 5.089643 s: 0x0 [4] [C7x_1 ] 5.089651 s: 0x0 [5] [C7x_1 ] 5.089659 s: 0x0 [6] [C7x_1 ] 5.089667 s: 0x0 [7] [C7x_1 ] 5.089675 s: 0x0 [1] [C7x_1 ] 5.089684 s: 0x0 [2] [C7x_1 ] 5.089692 s: 0x0 [3] [C7x_1 ] 5.089700 s: 0x0 [4] [C7x_1 ] 5.089707 s: 0x0 [5] [C7x_1 ] 5.089715 s: 0x0 [6] [C7x_1 ] 5.089723 s: 0x0 [7] [C7x_1 ] 5.089737 s: A0 =0x0 A1 =0x0 [C7x_1 ] 5.089748 s: A2 =0x3fe0 A3 =0xaa01c020 [C7x_1 ] 5.089758 s: A4 =0x1 A5 =0xb0e441c8 [C7x_1 ] 5.089768 s: A6 =0xb06e7ad8 A7 =0x1 [C7x_1 ] 5.089778 s: A8 =0x0 A9 =0xb06e7ba8 [C7x_1 ] 5.089788 s: A10=0xb0decbe4 A11=0xb10aea30 [C7x_1 ] 5.089798 s: A12=0xb10aea34 A13=0x0 [C7x_1 ] 5.089808 s: A14=0xb0b2873c A15=0xb06e7e38 [C7x_1 ] 5.089819 s: D0 =0xb06e8000 D1 =0xb108e980 [C7x_1 ] 5.089830 s: D2 =0xb10b0af0 D3 =0x389b [C7x_1 ] 5.089840 s: D4 =0xb06e7790 D5 =0xb06e7790 [C7x_1 ] 5.089850 s: D6 =0xb06e7790 D7 =0xb06e7790 [C7x_1 ] 5.089861 s: D8 =0xb0e51480 D9 =0xb0e3a840 [C7x_1 ] 5.089871 s: D10=0xb0e3a780 D11=0x8110820 [C7x_1 ] 5.089882 s: D12=0x8d615a0 D13=0xb06e77c6 [C7x_1 ] 5.089893 s: D14=0xb06e7698 D15=0xb06e7ad8 [C7x_1 ] 5.089903 s: AM0=0x0 AM1=0x38 [C7x_1 ] 5.089912 s: AM2=0x18 AM3=0x1c90e4c0 [C7x_1 ] 5.089922 s: AM4=0xe4bb1830 AM5=0x32de46b2 [C7x_1 ] 5.089932 s: AM6=0x6ca71bf4 AM7=0x18 [C7x_1 ] 5.089942 s: AL0=0x0 AL1=0x0 [C7x_1 ] 5.089951 s: AL2=0x3fe0 AL3=0x0 [C7x_1 ] 5.089960 s: AL4=0x0 AL5=0x190fe481 [C7x_1 ] 5.089970 s: AL6=0x6b0349c8 AL7=0x38 [C7x_1 ] 5.089980 s: P0=0x1 P1=0xffffffff [C7x_1 ] 5.089990 s: P2=0xa40d4bb7 P3=0x854e1b1 [C7x_1 ] 5.090000 s: P4=0x11405097 P5=0x4d760ab0 [C7x_1 ] 5.090010 s: P6=0x5120a604 P7=0x703841f5 [C7x_1 ] 5.090020 s: FPCR=0x10 FSR=0x0 [C7x_1 ] 5.090029 s: GFPGFR=0x700001d GPLY=0x0 [C7x_1 ] 5.090040 s: [C7x_1 ] =0xb10ffa40 [0] [C7x_1 ] 5.090049 s: [C7x_1 ] =0xb10ffa40 [0] [C7x_1 ] 5.090058 s: 0x0 [1] [C7x_1 ] 5.090066 s: 0x0 [2] [C7x_1 ] 5.090074 s: 0x0 [3] [C7x_1 ] 5.090082 s: 0x0 [4] [C7x_1 ] 5.090090 s: 0x0 [5] [C7x_1 ] 5.090098 s: 0x0 [6] [C7x_1 ] 5.090106 s: 0x0 [7] [C7x_1 ] 5.090114 s: 0x1f6f3708 [1] [C7x_1 ] 5.090124 s: 0xeec502 [2] [C7x_1 ] 5.090132 s: 0x1884121 [3] [C7x_1 ] 5.090141 s: 0x9cd8b481 [4] [C7x_1 ] 5.090150 s: 0x220ccae8 [5] [C7x_1 ] 5.090159 s: 0x18252733 [6] [C7x_1 ] 5.090168 s: 0x242bb539 [7] [C7x_1 ] 5.090176 s: [C7x_1 ] VBM2=0xb10ff9c0 [0] [C7x_1 ] 5.090186 s: [C7x_1 ] =0xb10ff9c0 [0] [C7x_2 ] 5.248454 s: CIO: Init ... Done !!! [C7x_2 ] 5.248473 s: ### CPU Frequency = 1000000000 Hz [C7x_2 ] 5.248488 s: CPU is running FreeRTOS [C7x_2 ] 5.248497 s: APP: Init ... !!! [C7x_2 ] 5.248506 s: SCICLIENT: Init ... !!! [C7x_2 ] 5.248608 s: SCICLIENT: DMSC FW version [10.0.8--v10.00.08 (Fiery Fox)] [C7x_2 ] 5.248625 s: SCICLIENT: DMSC FW revision 0xa [C7x_2 ] 5.248636 s: SCICLIENT: DMSC FW ABI revision 4.0 [C7x_2 ] 5.248648 s: SCICLIENT: Init ... Done !!! [C7x_2 ] 5.248659 s: UDMA: Init ... !!! [C7x_2 ] 5.249420 s: UDMA: Init ... Done !!! [C7x_2 ] 5.249438 s: MEM: Init ... !!! [C7x_2 ] 5.249453 s: A0 =0xffff00 A1 =0x27000000 [C7x_2 ] 5.249469 s: A2 =0x1 A3 =0xaa020020 [C7x_2 ] 5.249479 s: A4 =0xb685ab18 A5 =0x27000000 [C7x_2 ] 5.249491 s: A6 =0x1000000 A7 =0x0 [C7x_2 ] 5.249501 s: A8 =0xb685ab10 A9 =0xb6941ba8 [C7x_2 ] 5.249512 s: A10=0xb6ad38a4 A11=0xb68555b0 [C7x_2 ] 5.249523 s: A12=0xb68555b4 A13=0x0 [C7x_2 ] 5.249534 s: A14=0xb6a5103c A15=0xb6941e38 [C7x_2 ] 5.249544 s: D0 =0x27ffff00 D1 =0xb683ad80 [C7x_2 ] 5.249555 s: D2 =0xb685baf0 D3 =0x22d [C7x_2 ] 5.249566 s: D4 =0xb6941790 D5 =0xb6941790 [C7x_2 ] 5.249576 s: D6 =0xb6941790 D7 =0xb6941790 [C7x_2 ] 5.249587 s: D8 =0xb6b04900 D9 =0xb6af6680 [C7x_2 ] 5.249598 s: D10=0xb6af65c0 D11=0x81361fc3 [C7x_2 ] 5.249609 s: D12=0x341ec37c D13=0xb69417c6 [C7x_2 ] 5.249619 s: D14=0xb6941798 D15=0xb6941ad8 [C7x_2 ] 5.249630 s: AM0=0x0 AM1=0x38 [C7x_2 ] 5.249639 s: AM2=0x18 AM3=0x14df2035 [C7x_2 ] 5.249649 s: AM4=0x2c83a611 AM5=0x51b5cd10 [C7x_2 ] 5.249660 s: AM6=0xb8458a3c AM7=0x18 [C7x_2 ] 5.249670 s: AL0=0x27ffff00 AL1=0xffffff00 [C7x_2 ] 5.249681 s: AL2=0xb6b00700 AL3=0x0 [C7x_2 ] 5.249690 s: AL4=0x0 AL5=0xc9d21a53 [C7x_2 ] 5.249701 s: AL6=0x370c8961 AL7=0x38 [C7x_2 ] 5.249711 s: P0=0xffffffff P1=0xffffffff [C7x_2 ] 5.249721 s: P2=0x47038099 P3=0x1d588608 [C7x_2 ] 5.249732 s: P4=0x808323d1 P5=0xe314c43 [C7x_2 ] 5.249742 s: P6=0x89049cb P7=0x80190665 [C7x_2 ] 5.249753 s: FPCR=0x10 FSR=0x0 [C7x_2 ] 5.249762 s: GFPGFR=0x700001d GPLY=0x0 [C7x_2 ] 5.249773 s: [C7x_2 ] VBM0=0xb6b3fa40 [0] [C7x_2 ] 5.249783 s: [C7x_2 ] =0xb6b3fa40 [0] [C7x_2 ] 5.249793 s: 0x0 [1] [C7x_2 ] 5.249802 s: 0x0 [2] [C7x_2 ] 5.249810 s: 0x0 [3] [C7x_2 ] 5.249819 s: 0x0 [4] [C7x_2 ] 5.249827 s: 0x0 [5] [C7x_2 ] 5.249835 s: 0x0 [6] [C7x_2 ] 5.249844 s: 0x0 [7] [C7x_2 ] 5.249852 s: 0x843c62f5 [1] [C7x_2 ] 5.249862 s: 0xa1222923 [2] [C7x_2 ] 5.249871 s: 0x19100126 [3] [C7x_2 ] 5.249880 s: 0xa48765a0 [4] [C7x_2 ] 5.249889 s: 0xa8485a08 [5] [C7x_2 ] 5.249898 s: 0x22a52f54 [6] [C7x_2 ] 5.249908 s: 0x12208684 [7] [C7x_2 ] 5.249917 s: [C7x_2 ] VBM2=0xb6b3f9c0 [0] [C7x_2 ] 5.249927 s: [C7x_2 ] =0xb6b3f9c0 [0] [C7x_2 ] 5.249937 s: 0xfa5c653a [1] [C7x_2 ] 5.249946 s: 0xa885819f [2] [C7x_2 ] 5.249955 s: 0x4b0d9af2 [3] [C7x_2 ] 5.249964 s: 0x84628004 [4] [C7x_2 ] 5.249973 s: 0xc544200 [5] [C7x_2 ] 5.249982 s: 0xa8814510 [6] [C7x_2 ] 5.249991 s: 0xac44114 [7] [C7x_2 ] 5.250001 s: 0x10410c48 [1] [C7x_2 ] 5.250009 s: 0x81c98d02 [2] [C7x_2 ] 5.250018 s: 0x82241822 [3] [C7x_2 ] 5.250028 s: 0xa8bed7b [4] [C7x_2 ] 5.250036 s: 0x6f90104a [5] [C7x_2 ] 5.250046 s: 0x249ae6a [6] [C7x_2 ] 5.250055 s: 0xa43b4200 [7] [C7x_2 ] 5.250065 s: [C7x_2 ] =0xb6b3f940 [0] [C7x_2 ] 5.250074 s: [C7x_2 ] =0xb6b3f940 [0] [C7x_2 ] 5.250083 s: 0x829a1204 [1] [C7x_2 ] 5.250092 s: 0x12649704 [2] [C7x_2 ] 5.250101 s: 0x3e142748 [3] [C7x_2 ] 5.250110 s: 0xd3e1a6e9 [4] [C7x_2 ] 5.250119 s: 0x840c2fea [5] [C7x_2 ] 5.250128 s: 0x528cb1d [6] [C7x_2 ] 5.250137 s: 0x489e [7] [C7x_2 ] 5.250146 s: 0x56108f68 [1] [C7x_2 ] 5.250155 s: 0x4215c324 [2] [C7x_2 ] 5.250164 s: 0x42a101f1 [3] [C7x_2 ] 5.250174 s: 0x50ec859 [4] [C7x_2 ] 5.250182 s: 0xdc172a9b [5] [C7x_2 ] 5.250192 s: 0xab88e5c3 [6] [C7x_2 ] 5.250201 s: 0xb04294c0 [7] [C7x_2 ] 5.250210 s: [C7x_2 ] =0xb6b3f8c0 [0] [C7x_2 ] 5.250219 s: [C7x_2 ] =0xb6b3f8c0 [0] [C7x_2 ] 5.250229 s: 0x10c222d1 [1] [C7x_2 ] 5.250238 s: 0x85a1ac31 [2] [C7x_2 ] 5.250247 s: 0x16149885 [3] [C7x_2 ] 5.250256 s: 0x18831980 [4] [C7x_2 ] 5.250265 s: 0x21007320 [5] [C7x_2 ] 5.250274 s: 0x1a6614c [6] [C7x_2 ] 5.250283 s: 0x2c352806 [7] [C7x_2 ] 5.250292 s: 0x5211700 [1] [C7x_2 ] 5.250301 s: 0xc911900 [2] [C7x_2 ] 5.250310 s: 0x414a6f02 [3] [C7x_2 ] 5.250320 s: 0x80164ae0 [4] [C7x_2 ] 5.250329 s: 0x40528820 [5] [C7x_2 ] 5.250338 s: 0xc36018 [6] [C7x_2 ] 5.250347 s: 0x2d43524a [7] [C7x_2 ] 5.250356 s: [C7x_2 ] VBL0=0xb6b3f840 [0] [C7x_2 ] 5.250365 s: [C7x_2 ] =0xb6b3f840 [0] [C7x_2 ] 5.250375 s: 0x0 [1] [C7x_2 ] 5.250383 s: 0x0 [2] [C7x_2 ] 5.250392 s: 0x0 [3] [C7x_2 ] 5.250400 s: 0x0 [4] [C7x_2 ] 5.250408 s: 0x0 [5] [C7x_2 ] 5.250416 s: 0x0 [6] [C7x_2 ] 5.250425 s: 0x0 [7] [C7x_2 ] 5.250433 s: 0x40 [1] [C7x_2 ] 5.250441 s: 0x40 [2] [C7x_2 ] 5.250450 s: 0x40 [3] [C7x_2 ] 5.250458 s: 0x40 [4] [C7x_2 ] 5.250467 s: 0x40 [5] [C7x_2 ] 5.250476 s: 0x40 [6] [C7x_2 ] 5.250484 s: 0x40 [7] [C7x_2 ] 5.250493 s: [C7x_2 ] =0xb6b3f7c0 [0] [C7x_2 ] 5.250502 s: [C7x_2 ] =0xb6b3f7c0 [0] [C7x_2 ] 5.250511 s: 0x61e0635a [1] [C7x_2 ] 5.250520 s: 0xa109019 [2] [C7x_2 ] 5.250530 s: 0x9f901398 [3] [C7x_2 ] 5.250539 s: 0x4059a311 [4] [C7x_2 ] 5.250548 s: 0xc0116830 [5] [C7x_2 ] 5.250557 s: 0x7d053288 [6] [C7x_2 ] 5.250566 s: 0x93ed8500 [7] [C7x_2 ] 5.250575 s: 0xd3a2245e [1] [C7x_2 ] 5.250584 s: 0xa8f187bb [2] [C7x_2 ] 5.250593 s: 0x2101048a [3] [C7x_2 ] 5.250602 s: 0x1b22c0c1 [4] [C7x_2 ] 5.250612 s: 0x15b410a4 [5] [C7x_2 ] 5.250621 s: 0x8d30814c [6] [C7x_2 ] 5.250629 s: 0xd500950e [7] [C7x_2 ] 5.250639 s: [C7x_2 ] VBL4=0xb6b3f740 [0] [C7x_2 ] 5.250648 s: [C7x_2 ] =0xb6b3f740 [0] [C7x_2 ] 5.250657 s: 0x2a0464e [1] [C7x_2 ] 5.250666 s: 0x1f61b50b [2] [C7x_2 ] 5.250676 s: 0x3e84541d [3] [C7x_2 ] 5.250685 s: 0xa22a91c [4] [C7x_2 ] 5.250694 s: 0xe2295631 [5] [C7x_2 ] 5.250703 s: 0xefd117d5 [6] [C7x_2 ] 5.250712 s: 0x5d009f8b [7] [C7x_2 ] 5.250721 s: 0x8245d240 [1] [C7x_2 ] 5.250730 s: 0x20022e90 [2] [C7x_2 ] 5.250739 s: 0xa78d06c [3] [C7x_2 ] 5.250748 s: 0x86c5d303 [4] [C7x_2 ] 5.250758 s: 0xd2a2c722 [5] [C7x_2 ] 5.250767 s: 0xa8601210 [6] [C7x_2 ] 5.250775 s: 0x40552240 [7] [C7x_2 ] 5.250785 s: [C7x_2 ] =0xb6b3f6c0 [0] [C7x_2 ] 5.250795 s: [C7x_2 ] VBL7=0xb6b3f6c0 [0] [C7x_2 ] 5.250804 s: 0x42a1e013 [1] [C7x_2 ] 5.250813 s: 0xc9253648 [2] [C7x_2 ] 5.250822 s: 0x100c65d8 [3] [C7x_2 ] 5.250832 s: 0xfa212281 [4] [C7x_2 ] 5.250840 s: 0x65f8925 [5] [C7x_2 ] 5.250849 s: 0xa3418204 [6] [C7x_2 ] 5.250859 s: 0x9e212371 [7] [C7x_2 ] 5.250868 s: 0x8775a184 [1] [C7x_2 ] 5.250877 s: 0x46a0204b [2] [C7x_2 ] 5.250886 s: 0x29378e12 [3] [C7x_2 ] 5.250895 s: 0xc4341942 [4] [C7x_2 ] 5.250904 s: 0xb405d521 [5] [C7x_2 ] 5.250913 s: 0xd0d4040a [6] [C7x_2 ] 5.250922 s: 0xa650069 [7] [C7x_2 ] 5.250931 s: [C7x_2 ] VB0=0xb6b3fe40 [0] [C7x_2 ] 5.250941 s: [C7x_2 ] =0xb6b3fe40 [0] [C7x_2 ] 5.250950 s: 0x0 [1] [C7x_2 ] 5.250958 s: 0x0 [2] [C7x_2 ] 5.250966 s: 0x0 [3] [C7x_2 ] 5.250974 s: 0x0 [4] [C7x_2 ] 5.250983 s: 0x0 [5] [C7x_2 ] 5.250991 s: 0x0 [6] [C7x_2 ] 5.250999 s: 0x0 [7] [C7x_2 ] 5.251008 s: 0x40 [1] [C7x_2 ] 5.251016 s: 0x0 [2] [C7x_2 ] 5.251025 s: 0x0 [3] [C7x_2 ] 5.251033 s: 0x0 [4] [C7x_2 ] 5.251041 s: 0x0 [5] [C7x_2 ] 5.251050 s: 0x0 [6] [C7x_2 ] 5.251058 s: 0x0 [7] [C7x_2 ] 5.251066 s: [C7x_2 ] =0xb6b3fdc0 [0] [C7x_2 ] 5.251075 s: [C7x_2 ] VB3=0xb6b3fdc0 [0] [C7x_2 ] 5.251085 s: 0x8 [1] [C7x_2 ] 5.251093 s: 0xc [2] [C7x_2 ] 5.251102 s: 0x0 [3] [C7x_2 ] 5.251110 s: 0x3000d [4] [C7x_2 ] 5.251120 s: 0x3 [5] [C7x_2 ] 5.251128 s: 0x0 [6] [C7x_2 ] 5.251136 s: 0xb6b00880 [7] [C7x_2 ] 5.251145 s: 0x4 [1] [C7x_2 ] 5.251153 s: 0x0 [2] [C7x_2 ] 5.251162 s: 0x0 [3] [C7x_2 ] 5.251170 s: 0x0 [4] [C7x_2 ] 5.251178 s: 0x0 [5] [C7x_2 ] 5.251186 s: 0x0 [6] [C7x_2 ] 5.251195 s: 0x20 [7] [C7x_2 ] 5.251204 s: [C7x_2 ] VB4=0xb6b3fd40 [0] [C7x_2 ] 5.251214 s: [C7x_2 ] VB5=0xb6b3fd40 [0] [C7x_2 ] 5.251223 s: 0x0 [1] [C7x_2 ] 5.251231 s: 0x0 [2] [C7x_2 ] 5.251239 s: 0x2 [3] [C7x_2 ] 5.251248 s: 0x0 [4] [C7x_2 ] 5.251256 s: 0x0 [5] [C7x_2 ] 5.251265 s: 0x4 [6] [C7x_2 ] 5.251273 s: 0x0 [7] [C7x_2 ] 5.251282 s: 0x18080c8 [1] [C7x_2 ] 5.251291 s: 0xa20ee33a [2] [C7x_2 ] 5.251300 s: 0x20b503b6 [3] [C7x_2 ] 5.251309 s: 0xefb3b802 [4] [C7x_2 ] 5.251318 s: 0xc2502f [5] [C7x_2 ] 5.251327 s: 0x10193851 [6] [C7x_2 ] 5.251336 s: 0x85602683 [7] [C7x_2 ] 5.251346 s: [C7x_2 ] VB6=0xb6b3fcc0 [0] [C7x_2 ] 5.251355 s: [C7x_2 ] VB7=0xb6b3fcc0 [0] [C7x_2 ] 5.251365 s: 0xc2ce0ab0 [1] [C7x_2 ] 5.251374 s: 0x8be05550 [2] [C7x_2 ] 5.251383 s: 0x882224c2 [3] [C7x_2 ] 5.251392 s: 0x59a6c142 [4] [C7x_2 ] 5.251402 s: 0x1c611342 [5] [C7x_2 ] 5.251411 s: 0xf00000b9 [6] [C7x_2 ] 5.251420 s: 0x950019c6 [7] [C7x_2 ] 5.251429 s: 0x7083115a [1] [C7x_2 ] 5.251438 s: 0x587fe903 [2] [C7x_2 ] 5.251447 s: 0x268270c [3] [C7x_2 ] 5.251456 s: 0x2066695a [4] [C7x_2 ] 5.251466 s: 0x25a62222 [5] [C7x_2 ] 5.251475 s: 0x4b124 [6] [C7x_2 ] 5.251484 s: 0xa36016d [7] [C7x_2 ] 5.251493 s: [C7x_2 ] =0xb6b3fc40 [0] [C7x_2 ] 5.251502 s: [C7x_2 ] =0xb6b3fc40 [0] [C7x_2 ] 5.251511 s: 0x4c069788 [1] [C7x_2 ] 5.251521 s: 0xba9fc550 [2] [C7x_2 ] 5.251529 s: 0x8a7c4003 [3] [C7x_2 ] 5.251538 s: 0x611696c8 [4] [C7x_2 ] 5.251548 s: 0x417e1c06 [5] [C7x_2 ] 5.251557 s: 0x1020413a [6] [C7x_2 ] 5.251566 s: 0x6834a942 [7] [C7x_2 ] 5.251575 s: 0x63c2000a [1] [C7x_2 ] 5.251584 s: 0x4d2ffc9b [2] [C7x_2 ] 5.251593 s: 0x2bd1fa9 [3] [C7x_2 ] 5.251602 s: 0x4c438671 [4] [C7x_2 ] 5.251611 s: 0x2316e007 [5] [C7x_2 ] 5.251620 s: 0x50d40a48 [6] [C7x_2 ] 5.251630 s: 0xa41495 [7] [C7x_2 ] 5.251639 s: [C7x_2 ] =0xb6b3fbc0 [0] [C7x_2 ] 5.251648 s: [C7x_2 ] =0xb6b3fbc0 [0] [C7x_2 ] 5.251657 s: 0x4a320969 [1] [C7x_2 ] 5.251667 s: 0x4c6944dc [2] [C7x_2 ] 5.251675 s: 0x10dd5c0e [3] [C7x_2 ] 5.251684 s: 0xa2905 [4] [C7x_2 ] 5.251694 s: 0x884985a9 [5] [C7x_2 ] 5.251703 s: 0x20011e24 [6] [C7x_2 ] 5.251712 s: 0x1a30820 [7] [C7x_2 ] 5.251721 s: 0xa0c01429 [1] [C7x_2 ] 5.251731 s: 0x4f5adc93 [2] [C7x_2 ] 5.251740 s: 0x60478201 [3] [C7x_2 ] 5.251749 s: 0x2184885b [4] [C7x_2 ] 5.251758 s: 0x4933a0a3 [5] [C7x_2 ] 5.251767 s: 0xb1129639 [6] [C7x_2 ] 5.251776 s: 0x23804cc8 [7] [C7x_2 ] 5.251785 s: [C7x_2 ] =0xb6b3fb40 [0] [C7x_2 ] 5.251794 s: [C7x_2 ] VB13=0xb6b3fb40 [0] [C7x_2 ] 5.251804 s: 0x28a912a [1] [C7x_2 ] 5.251813 s: 0x1e21028 [2] [C7x_2 ] 5.251822 s: 0x218225c9 [3] [C7x_2 ] 5.251831 s: 0x3842484d [4] [C7x_2 ] 5.251840 s: 0x8834583 [5] [C7x_2 ] 5.251849 s: 0x98806098 [6] [C7x_2 ] 5.251858 s: 0x4828386e [7] [C7x_2 ] 5.251867 s: 0x11042866 [1] [C7x_2 ] 5.251877 s: 0x1d0d4842 [2] [C7x_2 ] 5.251886 s: 0x4724a049 [3] [C7x_2 ] 5.251894 s: 0xadcd244e [4] [C7x_2 ] 5.251904 s: 0x80002888 [5] [C7x_2 ] 5.251913 s: 0x5102178d [6] [C7x_2 ] 5.251922 s: 0x222caf68 [7] [C7x_2 ] 5.251932 s: [C7x_2 ] =0xb6b3fac0 [0] [C7x_2 ] 5.251941 s: [C7x_2 ] VB15=0xb6b3fac0 [0] [C7x_2 ] 5.251950 s: 0x41015710 [1] [C7x_2 ] 5.251959 s: 0xab22c624 [2] [C7x_2 ] 5.251968 s: 0x443851c0 [3] [C7x_2 ] 5.251978 s: 0xc0125802 [4] [C7x_2 ] 5.251987 s: 0x93a64218 [5] [C7x_2 ] 5.251996 s: 0xc2400c20 [6] [C7x_2 ] 5.252005 s: 0xb12cc80c [7] [C7x_2 ] 5.252014 s: 0x28000896 [1] [C7x_2 ] 5.252023 s: 0x362024a7 [2] [C7x_2 ] 5.252032 s: 0xfa601460 [3] [C7x_2 ] 5.252041 s: 0x48153402 [4] [C7x_2 ] 5.252050 s: 0x80840c8d [5] [C7x_2 ] 5.252060 s: 0x6460184 [6] [C7x_2 ] 5.252068 s: 0x1e008830 [7] [C7x_2 ] 5.252078 s: [C7x_2 ] CUCR0=0xb6b3f640 [0] [C7x_2 ] 5.252087 s: [C7x_2 ] CUCR1=0xb6b3f640 [0] [C7x_2 ] 5.252097 s: 0x0 [1] [C7x_2 ] 5.252106 s: 0x0 [2] [C7x_2 ] 5.252114 s: 0x0 [3] [C7x_2 ] 5.252122 s: 0x0 [4] [C7x_2 ] 5.252130 s: 0x0 [5] [C7x_2 ] 5.252139 s: 0x0 [6] [C7x_2 ] 5.252147 s: 0x0 [7] [C7x_2 ] 5.252155 s: 0x0 [1] [C7x_2 ] 5.252164 s: 0x0 [2] [C7x_2 ] 5.252172 s: 0x0 [3] [C7x_2 ] 5.252180 s: 0x0 [4] [C7x_2 ] 5.252188 s: 0x0 [5] [C7x_2 ] 5.252197 s: 0x0 [6] [C7x_2 ] 5.252205 s: 0x0 [7] [C7x_2 ] 5.252213 s: [C7x_2 ] CUCR2=0xb6b3f5c0 [0] [C7x_2 ] 5.252223 s: [C7x_2 ] CUCR3=0xb6b3f5c0 [0] [C7x_2 ] 5.252233 s: 0x0 [1] [C7x_2 ] 5.252241 s: 0x0 [2] [C7x_2 ] 5.252249 s: 0x0 [3] [C7x_2 ] 5.252258 s: 0x0 [4] [C7x_2 ] 5.252266 s: 0x0 [5] [C7x_2 ] 5.252274 s: 0x0 [6] [C7x_2 ] 5.252282 s: 0x0 [7] [C7x_2 ] 5.252291 s: 0x0 [1] [C7x_2 ] 5.252299 s: 0x0 [2] [C7x_2 ] 5.252307 s: 0x0 [3] [C7x_2 ] 5.252316 s: 0x0 [4] [C7x_2 ] 5.252324 s: 0x0 [5] [C7x_2 ] 5.252332 s: 0x0 [6] [C7x_2 ] 5.252341 s: 0x0 [7] [C7x_2 ] 5.252349 s: [C7x_2 ] SE0_0=0xb6b3f180 [0] [C7x_2 ] 5.252359 s: [C7x_2 ] SE0_1=0xb6b3f180 [0] [C7x_2 ] 5.252369 s: 0x0 [1] [C7x_2 ] 5.252377 s: 0x0 [2] [C7x_2 ] 5.252386 s: 0x0 [3] [C7x_2 ] 5.252394 s: 0x0 [4] [C7x_2 ] 5.252402 s: 0x0 [5] [C7x_2 ] 5.252411 s: 0x0 [6] [C7x_2 ] 5.252419 s: 0x0 [7] [C7x_2 ] 5.252428 s: 0x0 [1] [C7x_2 ] 5.252436 s: 0x0 [2] [C7x_2 ] 5.252444 s: 0x0 [3] [C7x_2 ] 5.252453 s: 0x0 [4] [C7x_2 ] 5.252461 s: 0x0 [5] [C7x_2 ] 5.252469 s: 0x0 [6] [C7x_2 ] 5.252477 s: 0x0 [7] [C7x_2 ] 5.252486 s: [C7x_2 ] SE0_2=0xb6b3f200 [0] [C7x_2 ] 5.252495 s: [C7x_2 ] SE0_3=0xb6b3f200 [0] [C7x_2 ] 5.252506 s: 0x0 [1] [C7x_2 ] 5.252514 s: 0x0 [2] [C7x_2 ] 5.252522 s: 0x0 [3] [C7x_2 ] 5.252530 s: 0x0 [4] [C7x_2 ] 5.252538 s: 0x0 [5] [C7x_2 ] 5.252547 s: 0x0 [6] [C7x_2 ] 5.252556 s: 0x0 [7] [C7x_2 ] 5.252564 s: 0x0 [1] [C7x_2 ] 5.252572 s: 0x0 [2] [C7x_2 ] 5.252580 s: 0x0 [3] [C7x_2 ] 5.252589 s: 0x0 [4] [C7x_2 ] 5.252597 s: 0x0 [5] [C7x_2 ] 5.252605 s: 0x0 [6] [C7x_2 ] 5.252614 s: 0x0 [7] [C7x_2 ] 5.252622 s: [C7x_2 ] SE1_0=0xb6b3f280 [0] [C7x_2 ] 5.252633 s: [C7x_2 ] SE1_1=0xb6b3f280 [0] [C7x_2 ] 5.252642 s: 0x0 [1] [C7x_2 ] 5.252651 s: 0x0 [2] [C7x_2 ] 5.252659 s: 0x0 [3] [C7x_2 ] 5.252667 s: 0x0 [4] [C7x_2 ] 5.252675 s: 0x0 [5] [C7x_2 ] 5.252684 s: 0x0 [6] [C7x_2 ] 5.252692 s: 0x0 [7] [C7x_2 ] 5.252701 s: 0x0 [1] [C7x_2 ] 5.252709 s: 0x0 [2] [C7x_2 ] 5.252717 s: 0x0 [3] [C7x_2 ] 5.252726 s: 0x0 [4] [C7x_2 ] 5.252734 s: 0x0 [5] [C7x_2 ] 5.252742 s: 0x0 [6] [C7x_2 ] 5.252751 s: 0x0 [7] [C7x_2 ] 5.252759 s: [C7x_2 ] SE1_2=0xb6b3f300 [0] [C7x_2 ] 5.252768 s: [C7x_2 ] SE1_3=0xb6b3f300 [0] [C7x_2 ] 5.252778 s: 0x0 [1] [C7x_2 ] 5.252786 s: 0x0 [2] [C7x_2 ] 5.252795 s: 0x0 [3] [C7x_2 ] 5.252803 s: 0x0 [4] [C7x_2 ] 5.252811 s: 0x0 [5] [C7x_2 ] 5.252819 s: 0x0 [6] [C7x_2 ] 5.252828 s: 0x0 [7] [C7x_2 ] 5.252836 s: 0x0 [1] [C7x_2 ] 5.252844 s: 0x0 [2] [C7x_2 ] 5.252852 s: 0x0 [3] [C7x_2 ] 5.252861 s: 0x0 [4] [C7x_2 ] 5.252870 s: 0x0 [5] [C7x_2 ] 5.252878 s: 0x0 [6] [C7x_2 ] 5.252887 s: 0x0 [7] [C7x_2 ] 5.252895 s: [C7x_2 ] SA0CR=0xb6b3f440 [0] [C7x_2 ] 5.252905 s: [C7x_2 ] SA1CR=0xb6b3f440 [0] [C7x_2 ] 5.252914 s: 0x0 [1] [C7x_2 ] 5.252923 s: 0x0 [2] [C7x_2 ] 5.252931 s: 0x0 [3] [C7x_2 ] 5.252940 s: 0x0 [4] [C7x_2 ] 5.252949 s: 0x0 [5] [C7x_2 ] 5.252957 s: 0x0 [6] [C7x_2 ] 5.252965 s: 0x0 [7] [C7x_2 ] 5.252973 s: 0x0 [1] [C7x_2 ] 5.252982 s: 0x0 [2] [C7x_2 ] 5.252990 s: 0x0 [3] [C7x_2 ] 5.252998 s: 0x0 [4] [C7x_2 ] 5.253006 s: 0x0 [5] [C7x_2 ] 5.253015 s: 0x0 [6] [C7x_2 ] 5.253023 s: 0x0 [7] [C7x_2 ] 5.253031 s: [C7x_2 ] SA2CR=0xb6b3f3c0 [0] [C7x_2 ] 5.253041 s: [C7x_2 ] SA3CR=0xb6b3f3c0 [0] [C7x_2 ] 5.253051 s: 0x0 [1] [C7x_2 ] 5.253060 s: 0x0 [2] [C7x_2 ] 5.253068 s: 0x0 [3] [C7x_2 ] 5.253076 s: 0x0 [4] [C7x_2 ] 5.253084 s: 0x0 [5] [C7x_2 ] 5.253093 s: 0x0 [6] [C7x_2 ] 5.253101 s: 0x0 [7] [C7x_2 ] 5.253109 s: 0x0 [1] [C7x_2 ] 5.253117 s: 0x0 [2] [C7x_2 ] 5.253126 s: 0x0 [3] [C7x_2 ] 5.253134 s: 0x0 [4] [C7x_2 ] 5.253142 s: 0x0 [5] [C7x_2 ] 5.253150 s: 0x0 [6] [C7x_2 ] 5.253159 s: 0x0 [7] [C7x_2 ] 5.253167 s: [C7x_2 ] SA0CNTR0=0xb6b3f540 [0] [C7x_2 ] 5.253177 s: [C7x_2 ] SA1CNTR0=0xb6b3f540 [0] [C7x_2 ] 5.253187 s: 0x0 [1] [C7x_2 ] 5.253196 s: 0x0 [2] [C7x_2 ] 5.253204 s: 0x0 [3] [C7x_2 ] 5.253213 s: 0x0 [4] [C7x_2 ] 5.253221 s: 0x0 [5] [C7x_2 ] 5.253229 s: 0x0 [6] [C7x_2 ] 5.253238 s: 0x0 [7] [C7x_2 ] 5.253246 s: 0x0 [1] [C7x_2 ] 5.253254 s: 0x0 [2] [C7x_2 ] 5.253263 s: 0x0 [3] [C7x_2 ] 5.253271 s: 0x0 [4] [C7x_2 ] 5.253280 s: 0x0 [5] [C7x_2 ] 5.253288 s: 0x0 [6] [C7x_2 ] 5.253296 s: 0x0 [7] [C7x_2 ] 5.253304 s: [C7x_2 ] SA2CNTR0=0xb6b3f4c0 [0] [C7x_2 ] 5.253314 s: [C7x_2 ] SA3CNTR0=0xb6b3f4c0 [0] [C7x_2 ] 5.253324 s: 0x0 [1] [C7x_2 ] 5.253332 s: 0x0 [2] [C7x_2 ] 5.253341 s: 0x0 [3] [C7x_2 ] 5.253349 s: 0x0 [4] [C7x_2 ] 5.253358 s: 0x0 [5] [C7x_2 ] 5.253366 s: 0x0 [6] [C7x_2 ] 5.253374 s: 0x0 [7] [C7x_2 ] 5.253382 s: 0x0 [1] [C7x_2 ] 5.253391 s: 0x0 [2] [C7x_2 ] 5.253399 s: 0x0 [3] [C7x_2 ] 5.253407 s: 0x0 [4] [C7x_2 ] 5.253415 s: 0x0 [5] [C7x_2 ] 5.253424 s: 0x0 [6] [C7x_2 ] 5.253432 s: 0x0 [7] [C7x_2 ] 5.253445 s: A0 =0x0 A1 =0x0 [C7x_2 ] 5.253456 s: A2 =0x3fe0 A3 =0xaa020020 [C7x_2 ] 5.253467 s: A4 =0x1 A5 =0xb6afc588 [C7x_2 ] 5.253477 s: A6 =0xb6941ad8 A7 =0x1 [C7x_2 ] 5.253487 s: A8 =0x0 A9 =0xb6941ba8 [C7x_2 ] 5.253497 s: A10=0xb6ad38a4 A11=0xb68555b0 [C7x_2 ] 5.253508 s: A12=0xb68555b4 A13=0x0 [C7x_2 ] 5.253518 s: A14=0xb6a5103c A15=0xb6941e38 [C7x_2 ] 5.253528 s: D0 =0xb6942000 D1 =0xb683ad80 [C7x_2 ] 5.253539 s: D2 =0xb685baf0 D3 =0x389f [C7x_2 ] 5.253549 s: D4 =0xb6941790 D5 =0xb6941790 [C7x_2 ] 5.253560 s: D6 =0xb6941790 D7 =0xb6941790 [C7x_2 ] 5.253571 s: D8 =0xb6b04900 D9 =0xb6af6680 [C7x_2 ] 5.253582 s: D10=0xb6af65c0 D11=0x81361fc3 [C7x_2 ] 5.253592 s: D12=0x341ec37c D13=0xb69417c6 [C7x_2 ] 5.253603 s: D14=0xb6941698 D15=0xb6941ad8 [C7x_2 ] 5.253614 s: AM0=0x0 AM1=0x38 [C7x_2 ] 5.253623 s: AM2=0x18 AM3=0x14df2035 [C7x_2 ] 5.253633 s: AM4=0x2c83a611 AM5=0x51b5cd10 [C7x_2 ] 5.253644 s: AM6=0xb8458a3c AM7=0x18 [C7x_2 ] 5.253654 s: AL0=0x0 AL1=0x0 [C7x_2 ] 5.253663 s: AL2=0x3fe0 AL3=0x0 [C7x_2 ] 5.253673 s: AL4=0x0 AL5=0xc9d21a53 [C7x_2 ] 5.253683 s: AL6=0x370c8961 AL7=0x38 [C7x_2 ] 5.253693 s: P0=0x1 P1=0xffffffff [C7x_2 ] 5.253703 s: P2=0x47038099 P3=0x1d588608 [C7x_2 ] 5.253714 s: P4=0x808323d1 P5=0xe314c43 [C7x_2 ] 5.253724 s: P6=0x89049cb P7=0x80190665 [C7x_2 ] 5.253734 s: FPCR=0x10 FSR=0x0 [C7x_2 ] 5.253744 s: GFPGFR=0x700001d GPLY=0x0 [C7x_2 ] 5.253754 s: [C7x_2 ] =0xb6b3fa40 [0] [C7x_2 ] 5.253763 s: [C7x_2 ] =0xb6b3fa40 [0] [C7x_2 ] 5.253773 s: 0x0 [1] [C7x_2 ] 5.253781 s: 0x0 [2]
output of `dmesg | grep remoteproc`
[ 9.610532] remoteproc remoteproc0: 64800000.dsp is available [ 9.621601] remoteproc remoteproc0: attaching to 64800000.dsp [ 9.647452] remoteproc remoteproc0: unsupported resource 65538 [ 9.721599] remoteproc remoteproc0: remote processor 64800000.dsp is now attached [ 9.765863] remoteproc remoteproc1: 65800000.dsp is available [ 9.772063] remoteproc remoteproc1: attaching to 65800000.dsp [ 9.783829] remoteproc remoteproc1: unsupported resource 65538 [ 9.841450] remoteproc remoteproc1: remote processor 65800000.dsp is now attached [ 10.018024] remoteproc remoteproc2: 41000000.r5f is available [ 10.024179] remoteproc remoteproc2: attaching to 41000000.r5f [ 10.124506] remoteproc remoteproc2: remote processor 41000000.r5f is now attached [ 10.220402] remoteproc remoteproc3: 5c00000.r5f is available [ 10.246007] remoteproc remoteproc3: attaching to 5c00000.r5f [ 10.308062] remoteproc remoteproc3: remote processor 5c00000.r5f is now attached [ 10.345950] remoteproc remoteproc4: 5d00000.r5f is available [ 10.354722] remoteproc remoteproc4: attaching to 5d00000.r5f [ 10.429819] remoteproc remoteproc4: remote processor 5d00000.r5f is now attached [ 10.440568] platform 5e00000.r5f: configured R5F for remoteproc mode [ 10.466077] remoteproc remoteproc5: 5e00000.r5f is available [ 10.478323] remoteproc remoteproc5: loading /lib/firmware/j721s2-main-r5f1_0-fw failed with error -22 [ 10.489112] remoteproc remoteproc5: Direct firmware load for j721s2-main-r5f1_0-fw failed with error -22 [ 10.504836] remoteproc remoteproc5: powering up 5e00000.r5f [ 10.514673] remoteproc remoteproc5: loading /lib/firmware/j721s2-main-r5f1_0-fw failed with error -22 [ 10.524767] remoteproc remoteproc5: Direct firmware load for j721s2-main-r5f1_0-fw failed with error -22 [ 10.539513] remoteproc remoteproc5: request_firmware failed: -22
output of `ls -lah /lib/firmware`
total 620K drwxr-xr-x 6 root root 4.0K Mar 9 2018 . drwxr-xr-x 57 root root 40K Mar 9 2018 .. drwxr-xr-x 2 root root 4.0K Mar 9 2018 cadence drwxr-xr-x 2 root root 4.0K Mar 9 2018 cnm lrwxrwxrwx 1 root root 62 Mar 9 2018 j721s2-c71_0-fw -> /usr/lib/firmware/vision_apps_eaik/vx_app_rtos_linux_c7x_1.out lrwxrwxrwx 1 root root 69 Mar 9 2018 j721s2-c71_0-fw-sec -> /usr/lib/firmware/vision_apps_eaik/vx_app_rtos_linux_c7x_1.out.signed lrwxrwxrwx 1 root root 62 Mar 9 2018 j721s2-c71_1-fw -> /usr/lib/firmware/vision_apps_eaik/vx_app_rtos_linux_c7x_2.out lrwxrwxrwx 1 root root 69 Mar 9 2018 j721s2-c71_1-fw-sec -> /usr/lib/firmware/vision_apps_eaik/vx_app_rtos_linux_c7x_2.out.signed lrwxrwxrwx 1 root root 63 Mar 9 2018 j721s2-main-r5f0_0-fw -> /usr/lib/firmware/vision_apps_eaik/vx_app_rtos_linux_mcu2_0.out lrwxrwxrwx 1 root root 70 Mar 9 2018 j721s2-main-r5f0_0-fw-sec -> /usr/lib/firmware/vision_apps_eaik/vx_app_rtos_linux_mcu2_0.out.signed lrwxrwxrwx 1 root root 63 Mar 9 2018 j721s2-main-r5f0_1-fw -> /usr/lib/firmware/vision_apps_eaik/vx_app_rtos_linux_mcu2_1.out lrwxrwxrwx 1 root root 70 Mar 9 2018 j721s2-main-r5f0_1-fw-sec -> /usr/lib/firmware/vision_apps_eaik/vx_app_rtos_linux_mcu2_1.out.signed lrwxrwxrwx 1 root root 63 Mar 9 2018 j721s2-main-r5f1_0-fw -> /usr/lib/firmware/vision_apps_eaik/vx_app_rtos_linux_mcu3_0.out lrwxrwxrwx 1 root root 70 Mar 9 2018 j721s2-main-r5f1_0-fw-sec -> /usr/lib/firmware/vision_apps_eaik/vx_app_rtos_linux_mcu3_0.out.signed lrwxrwxrwx 1 root root 63 Mar 9 2018 j721s2-main-r5f1_1-fw -> /usr/lib/firmware/vision_apps_eaik/vx_app_rtos_linux_mcu3_1.out lrwxrwxrwx 1 root root 70 Mar 9 2018 j721s2-main-r5f1_1-fw-sec -> /usr/lib/firmware/vision_apps_eaik/vx_app_rtos_linux_mcu3_1.out.signed lrwxrwxrwx 1 root root 63 Mar 9 2018 j721s2-mcu-r5f0_1-fw -> /usr/lib/firmware/vision_apps_eaik/vx_app_rtos_linux_mcu1_1.out lrwxrwxrwx 1 root root 79 Mar 9 2018 j721s2-mcu-r5f0_1-fw-sec -> /usr/lib/firmware/ti-ipc/j721s2/ipc_echo_test_mcu1_1_release_strip.xer5f.signed -rw-r--r-- 1 root root 140K Mar 9 2018 rgx.fw.36.53.104.796 -rw-r--r-- 1 root root 375K Mar 9 2018 rgx.sh.36.53.104.796 drwxr-xr-x 3 root root 4.0K Mar 9 2018 ti-ipc drwxr-xr-x 2 root root 4.0K Mar 9 2018 vision_apps_eaik lrwxrwxrwx 1 root root 46 Mar 9 2018 wave521c_k3_codec_fw.bin -> /usr/lib/firmware/cnm/wave521c_k3_codec_fw.bin
<!DOCTYPE html> <html> <style type="text/css"> .tg {border-collapse:collapse;border-spacing:0;border-color:#999;} .tg td{font-family:Arial, sans-serif;font-size:14px;padding:10px 5px;border-style:solid;border-width:1px;overflow:hidden;word-break:normal;border-color:#999;color:#444;background-color:#F7FDFA;} .tg th{font-family:Arial, sans-serif;font-size:14px;font-weight:normal;padding:10px 5px;border-style:solid;border-width:1px;overflow:hidden;word-break:normal;border-color:#999;color:#fff;background-color:#26ADE4;} .tg .tg-kftd{background-color:#efefef;text-align:left;vertical-align:top} .tg .tg-6sgx{background-color:#ffffff;text-align:left;vertical-align:top} .tg .tg-fjir{background-color:#343434;color:#ffffff;text-align:left;vertical-align:top} </style> <head> <title>System Memory Map for Linux+RTOS mode</title> </head> <body> <h1>System Memory Map for Linux+RTOS mode</h1> <p>Note, this file is auto generated using PyTI_PSDK_RTOS tool</p> <table class="tg"> <tr> <th class="tg-fjir">Name</th> <th class="tg-fjir">Start Addr</th> <th class="tg-fjir">End Addr</th> <th class="tg-fjir">Size </th> <th class="tg-fjir">Attributes</th> <th class="tg-fjir">Description</th> </tr> <tr> <td class="tg-kftd">MAIN_OCRAM_MCU2_0</td> <td class="tg-kftd">0x60000000</td> <td class="tg-kftd">0x6007FFFF</td> <td class="tg-kftd">512.00 KB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">Main OCRAM for MCU2_0</td> </tr> <tr> <td class="tg-6sgx">MAIN_OCRAM_MCU2_1</td> <td class="tg-6sgx">0x60080000</td> <td class="tg-6sgx">0x600FFFFF</td> <td class="tg-6sgx">512.00 KB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">Main OCRAM for MCU2_1</td> </tr> <tr> <td class="tg-kftd">L2RAM_C7x_1</td> <td class="tg-kftd">0x64800000</td> <td class="tg-kftd">0x6486FFFF</td> <td class="tg-kftd">448.00 KB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">L2 for C7x_1</td> </tr> <tr> <td class="tg-6sgx">L1RAM_C7x_1</td> <td class="tg-6sgx">0x64E00000</td> <td class="tg-6sgx">0x64E03FFF</td> <td class="tg-6sgx">16.00 KB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">L1 for C7x_1</td> </tr> <tr> <td class="tg-kftd">L2RAM_C7x_2</td> <td class="tg-kftd">0x65800000</td> <td class="tg-kftd">0x6586FFFF</td> <td class="tg-kftd">448.00 KB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">L2 for C7x_2</td> </tr> <tr> <td class="tg-6sgx">L1RAM_C7x_2</td> <td class="tg-6sgx">0x65E00000</td> <td class="tg-6sgx">0x65E03FFF</td> <td class="tg-6sgx">16.00 KB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">L1 for C7x_2</td> </tr> <tr> <td class="tg-kftd">MSMC_MPU1</td> <td class="tg-kftd">0x70000000</td> <td class="tg-kftd">0x7001FFFF</td> <td class="tg-kftd">128.00 KB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">MSMC reserved for MPU1 for ATF</td> </tr> <tr> <td class="tg-6sgx">MSMC_C7x_1</td> <td class="tg-6sgx">0x70020000</td> <td class="tg-6sgx">0x703E7FFF</td> <td class="tg-6sgx"> 3.78 MB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">MSMC for C7x_1</td> </tr> <tr> <td class="tg-kftd">MSMC_DMSC</td> <td class="tg-kftd">0x703F0000</td> <td class="tg-kftd">0x703FFFFF</td> <td class="tg-kftd">64.00 KB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">MSMC reserved for DMSC IPC</td> </tr> <tr> <td class="tg-6sgx">DDR_MCU1_0_IPC</td> <td class="tg-6sgx">0xA0000000</td> <td class="tg-6sgx">0xA00FFFFF</td> <td class="tg-6sgx">1024.00 KB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for MCU1_0 for Linux IPC</td> </tr> <tr> <td class="tg-kftd">DDR_MCU1_0_RESOURCE_TABLE</td> <td class="tg-kftd">0xA0100000</td> <td class="tg-kftd">0xA01003FF</td> <td class="tg-kftd">1024 B</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for MCU1_0 for Linux resource table</td> </tr> <tr> <td class="tg-6sgx">DDR_MCU1_0</td> <td class="tg-6sgx">0xA0100400</td> <td class="tg-6sgx">0xA0FFFFFF</td> <td class="tg-6sgx">15.00 MB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for MCU1_0 for code/data</td> </tr> <tr> <td class="tg-kftd">DDR_MCU1_1_IPC</td> <td class="tg-kftd">0xA1000000</td> <td class="tg-kftd">0xA10FFFFF</td> <td class="tg-kftd">1024.00 KB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for MCU1_1 for Linux IPC</td> </tr> <tr> <td class="tg-6sgx">DDR_MCU1_1_RESOURCE_TABLE</td> <td class="tg-6sgx">0xA1100000</td> <td class="tg-6sgx">0xA11003FF</td> <td class="tg-6sgx">1024 B</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for MCU1_1 for Linux resource table</td> </tr> <tr> <td class="tg-kftd">DDR_MCU1_1</td> <td class="tg-kftd">0xA1100400</td> <td class="tg-kftd">0xA1FFFFFF</td> <td class="tg-kftd">15.00 MB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for MCU1_1 for code/data</td> </tr> <tr> <td class="tg-6sgx">DDR_MCU2_0_IPC</td> <td class="tg-6sgx">0xA2000000</td> <td class="tg-6sgx">0xA20FFFFF</td> <td class="tg-6sgx">1024.00 KB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for MCU2_0 for Linux IPC</td> </tr> <tr> <td class="tg-kftd">DDR_MCU2_0_RESOURCE_TABLE</td> <td class="tg-kftd">0xA2100000</td> <td class="tg-kftd">0xA21003FF</td> <td class="tg-kftd">1024 B</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for MCU2_0 for Linux resource table</td> </tr> <tr> <td class="tg-6sgx">DDR_MCU2_0</td> <td class="tg-6sgx">0xA2100400</td> <td class="tg-6sgx">0xA3FFFFFF</td> <td class="tg-6sgx">31.00 MB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for MCU2_0 for code/data</td> </tr> <tr> <td class="tg-kftd">DDR_MCU2_1_IPC</td> <td class="tg-kftd">0xA4000000</td> <td class="tg-kftd">0xA40FFFFF</td> <td class="tg-kftd">1024.00 KB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for MCU2_1 for Linux IPC</td> </tr> <tr> <td class="tg-6sgx">DDR_MCU2_1_RESOURCE_TABLE</td> <td class="tg-6sgx">0xA4100000</td> <td class="tg-6sgx">0xA41003FF</td> <td class="tg-6sgx">1024 B</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for MCU2_1 for Linux resource table</td> </tr> <tr> <td class="tg-kftd">DDR_MCU2_1</td> <td class="tg-kftd">0xA4100400</td> <td class="tg-kftd">0xA5FFFFFF</td> <td class="tg-kftd">31.00 MB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for MCU2_1 for code/data</td> </tr> <tr> <td class="tg-6sgx">DDR_MCU3_0_IPC</td> <td class="tg-6sgx">0xA6000000</td> <td class="tg-6sgx">0xA60FFFFF</td> <td class="tg-6sgx">1024.00 KB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for MCU3_0 for Linux IPC</td> </tr> <tr> <td class="tg-kftd">DDR_MCU3_0_RESOURCE_TABLE</td> <td class="tg-kftd">0xA6100000</td> <td class="tg-kftd">0xA61003FF</td> <td class="tg-kftd">1024 B</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for MCU3_0 for Linux resource table</td> </tr> <tr> <td class="tg-6sgx">DDR_MCU3_0</td> <td class="tg-6sgx">0xA6100400</td> <td class="tg-6sgx">0xA6FFFFFF</td> <td class="tg-6sgx">15.00 MB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for MCU3_0 for code/data</td> </tr> <tr> <td class="tg-kftd">DDR_MCU3_1_IPC</td> <td class="tg-kftd">0xA7000000</td> <td class="tg-kftd">0xA70FFFFF</td> <td class="tg-kftd">1024.00 KB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for MCU3_1 for Linux IPC</td> </tr> <tr> <td class="tg-6sgx">DDR_MCU3_1_RESOURCE_TABLE</td> <td class="tg-6sgx">0xA7100000</td> <td class="tg-6sgx">0xA71003FF</td> <td class="tg-6sgx">1024 B</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for MCU3_1 for Linux resource table</td> </tr> <tr> <td class="tg-kftd">DDR_MCU3_1</td> <td class="tg-kftd">0xA7100400</td> <td class="tg-kftd">0xA7FFFFFF</td> <td class="tg-kftd">15.00 MB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for MCU3_1 for code/data</td> </tr> <tr> <td class="tg-6sgx">IPC_VRING_MEM</td> <td class="tg-6sgx">0xA8000000</td> <td class="tg-6sgx">0xA9FFFFFF</td> <td class="tg-6sgx">32.00 MB</td> <td class="tg-6sgx"></td> <td class="tg-6sgx">Memory for IPC Vring's. MUST be non-cached or cache-coherent</td> </tr> <tr> <td class="tg-kftd">APP_LOG_MEM</td> <td class="tg-kftd">0xAA000000</td> <td class="tg-kftd">0xAA03FFFF</td> <td class="tg-kftd">256.00 KB</td> <td class="tg-kftd"></td> <td class="tg-kftd">Memory for remote core logging</td> </tr> <tr> <td class="tg-6sgx">TIOVX_OBJ_DESC_MEM</td> <td class="tg-6sgx">0xAA040000</td> <td class="tg-6sgx">0xADFFFFFF</td> <td class="tg-6sgx">63.75 MB</td> <td class="tg-6sgx"></td> <td class="tg-6sgx">Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent</td> </tr> <tr> <td class="tg-kftd">APP_FILEIO_MEM</td> <td class="tg-kftd">0xAE000000</td> <td class="tg-kftd">0xAE3FFFFF</td> <td class="tg-kftd"> 4.00 MB</td> <td class="tg-kftd"></td> <td class="tg-kftd">Memory for remote core file operations</td> </tr> <tr> <td class="tg-6sgx">TIOVX_LOG_RT_MEM</td> <td class="tg-6sgx">0xAE400000</td> <td class="tg-6sgx">0xAFFFFFFF</td> <td class="tg-6sgx">28.00 MB</td> <td class="tg-6sgx"></td> <td class="tg-6sgx">Memory for TI OpenVX shared memory for Run-time logging. MUST be non-cached or cache-coherent</td> </tr> <tr> <td class="tg-kftd">DDR_C7x_1_IPC</td> <td class="tg-kftd">0xB0000000</td> <td class="tg-kftd">0xB00FFFFF</td> <td class="tg-kftd">1024.00 KB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for C7x_1 for Linux IPC</td> </tr> <tr> <td class="tg-6sgx">DDR_C7x_1_RESOURCE_TABLE</td> <td class="tg-6sgx">0xB0100000</td> <td class="tg-6sgx">0xB01003FF</td> <td class="tg-6sgx">1024 B</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for C7x_1 for Linux resource table</td> </tr> <tr> <td class="tg-kftd">DDR_C7x_1_BOOT</td> <td class="tg-kftd">0xB0200000</td> <td class="tg-kftd">0xB02003FF</td> <td class="tg-kftd">1024 B</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for C7x_1 for boot section</td> </tr> <tr> <td class="tg-6sgx">DDR_C7x_1_VECS</td> <td class="tg-6sgx">0xB0400000</td> <td class="tg-6sgx">0xB0403FFF</td> <td class="tg-6sgx">16.00 KB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for C7x_1 for vecs section</td> </tr> <tr> <td class="tg-kftd">DDR_C7x_1_SECURE_VECS</td> <td class="tg-kftd">0xB0600000</td> <td class="tg-kftd">0xB0603FFF</td> <td class="tg-kftd">16.00 KB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for C7x_1 for secure vecs section</td> </tr> <tr> <td class="tg-6sgx">DDR_C7x_1</td> <td class="tg-6sgx">0xB0604000</td> <td class="tg-6sgx">0xB5FFFFFF</td> <td class="tg-6sgx">89.98 MB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for C7x_1 for code/data</td> </tr> <tr> <td class="tg-kftd">DDR_C7x_2_IPC</td> <td class="tg-kftd">0xB6000000</td> <td class="tg-kftd">0xB60FFFFF</td> <td class="tg-kftd">1024.00 KB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for C7x_2 for Linux IPC</td> </tr> <tr> <td class="tg-6sgx">DDR_C7x_2_RESOURCE_TABLE</td> <td class="tg-6sgx">0xB6100000</td> <td class="tg-6sgx">0xB61003FF</td> <td class="tg-6sgx">1024 B</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for C7x_2 for Linux resource table</td> </tr> <tr> <td class="tg-kftd">DDR_C7x_2_BOOT</td> <td class="tg-kftd">0xB6200000</td> <td class="tg-kftd">0xB62003FF</td> <td class="tg-kftd">1024 B</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for C7x_2 for boot section</td> </tr> <tr> <td class="tg-6sgx">DDR_C7x_2_VECS</td> <td class="tg-6sgx">0xB6400000</td> <td class="tg-6sgx">0xB6403FFF</td> <td class="tg-6sgx">16.00 KB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for C7x_2 for vecs section</td> </tr> <tr> <td class="tg-kftd">DDR_C7x_2_SECURE_VECS</td> <td class="tg-kftd">0xB6600000</td> <td class="tg-kftd">0xB6603FFF</td> <td class="tg-kftd">16.00 KB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for C7x_2 for secure vecs section</td> </tr> <tr> <td class="tg-6sgx">DDR_C7x_2</td> <td class="tg-6sgx">0xB6604000</td> <td class="tg-6sgx">0xB7FFFFFF</td> <td class="tg-6sgx">25.98 MB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for C7x_2 for code/data</td> </tr> <tr> <td class="tg-kftd">DDR_MCU1_0_LOCAL_HEAP</td> <td class="tg-kftd">0xB8000000</td> <td class="tg-kftd">0xB87FFFFF</td> <td class="tg-kftd"> 8.00 MB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for MCU1_0 for local heap</td> </tr> <tr> <td class="tg-6sgx">DDR_MCU1_1_LOCAL_HEAP</td> <td class="tg-6sgx">0xB8800000</td> <td class="tg-6sgx">0xB8FFFFFF</td> <td class="tg-6sgx"> 8.00 MB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for MCU1_1 for local heap</td> </tr> <tr> <td class="tg-kftd">DDR_MCU2_0_LOCAL_HEAP</td> <td class="tg-kftd">0xB9000000</td> <td class="tg-kftd">0xB9DFFFFF</td> <td class="tg-kftd">14.00 MB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for MCU2_0 for local heap</td> </tr> <tr> <td class="tg-6sgx">DDR_MCU2_0_VISS_CONFIG_HEAP</td> <td class="tg-6sgx">0xB9E00000</td> <td class="tg-6sgx">0xB9FFFFFF</td> <td class="tg-6sgx"> 2.00 MB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">VISS configuration memory. MUST be write through cache policy.</td> </tr> <tr> <td class="tg-kftd">DDR_MCU2_1_LOCAL_HEAP</td> <td class="tg-kftd">0xBA000000</td> <td class="tg-kftd">0xBAFFFFFF</td> <td class="tg-kftd">16.00 MB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for MCU2_1 for local heap</td> </tr> <tr> <td class="tg-6sgx">DDR_MCU3_0_LOCAL_HEAP</td> <td class="tg-6sgx">0xBB000000</td> <td class="tg-6sgx">0xBB7FFFFF</td> <td class="tg-6sgx"> 8.00 MB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for MCU3_0 for local heap</td> </tr> <tr> <td class="tg-kftd">DDR_MCU3_1_LOCAL_HEAP</td> <td class="tg-kftd">0xBB800000</td> <td class="tg-kftd">0xBBFFFFFF</td> <td class="tg-kftd"> 8.00 MB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for MCU3_1 for local heap</td> </tr> <tr> <td class="tg-6sgx">DDR_SHARED_MEM</td> <td class="tg-6sgx">0xC0000000</td> <td class="tg-6sgx">0xD7FFFFFF</td> <td class="tg-6sgx">384.00 MB</td> <td class="tg-6sgx"></td> <td class="tg-6sgx">Memory for shared memory buffers in DDR</td> </tr> <tr> <td class="tg-kftd">DDR_C7X_1_SCRATCH</td> <td class="tg-kftd">0xD8000000</td> <td class="tg-kftd">0xEAFFFFFF</td> <td class="tg-kftd">304.00 MB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for c7x_1 for Scratch Memory</td> </tr> <tr> <td class="tg-6sgx">DDR_C7X_1_LOCAL_HEAP</td> <td class="tg-6sgx">0xEB000000</td> <td class="tg-6sgx">0xFAFFFFFF</td> <td class="tg-6sgx">256.00 MB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for c7x_1 for local heap</td> </tr> <tr> <td class="tg-kftd">DDR_C7X_2_LOCAL_HEAP</td> <td class="tg-kftd">0xFB000000</td> <td class="tg-kftd">0xFBFFFFFF</td> <td class="tg-kftd">16.00 MB</td> <td class="tg-kftd">RWIX</td> <td class="tg-kftd">DDR for c7x_2 for local heap</td> </tr> <tr> <td class="tg-6sgx">DDR_C7X_2_SCRATCH</td> <td class="tg-6sgx">0xFC000000</td> <td class="tg-6sgx">0xFFFFFFFF</td> <td class="tg-6sgx">64.00 MB</td> <td class="tg-6sgx">RWIX</td> <td class="tg-6sgx">DDR for c7x_2 for Scratch Memory</td> </tr> </table> </body> </html>
Modified `gen_linker_mem_map.py`
#!/usr/bin/env python3 # # Copyright (c) 2018 Texas Instruments Incorporated # # All rights reserved not granted herein. # # Limited License. # # Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive # license under copyrights and patents it now or hereafter owns or controls to make, # have made, use, import, offer to sell and sell ("Utilize") this software subject to the # terms herein. With respect to the foregoing patent license, such license is granted # solely to the extent that any such patent is necessary to Utilize the software alone. # The patent license shall not apply to any combinations which include this software, # other than combinations with devices manufactured by or for TI ("TI Devices"). # No hardware patent is licensed hereunder. # # Redistributions must preserve existing copyright notices and reproduce this license # (including the above copyright notice and the disclaimer and (if applicable) source # code license limitations below) in the documentation and/or other materials provided # with the distribution # # Redistribution and use in binary form, without modification, are permitted provided # that the following conditions are met: # # No reverse engineering, decompilation, or disassembly of this software is # permitted with respect to any software provided in binary form. # # any redistribution and use are licensed by TI for use only with TI Devices. # # Nothing shall obligate TI to provide you with source code for the software # licensed and provided to you in object code. # # If software source code is provided to you, modification and redistribution of the # source code are permitted provided that the following conditions are met: # # any redistribution and use of the source code, including any resulting derivative # works, are licensed by TI for use only with TI Devices. # # any redistribution and use of any object code compiled from the source code # and any resulting derivative works, are licensed by TI for use only with TI Devices. # # Neither the name of Texas Instruments Incorporated nor the names of its suppliers # # may be used to endorse or promote products derived from this software without # specific prior written permission. # # DISCLAIMER. # # THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. # IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY # OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE # OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # OF THE POSSIBILITY OF SUCH DAMAGE. # # # # This script is used to generate 'MEMORY' section for multiple CPUs # in different CPU specific linker command files. # # This helps to define the memory map in one file vs having to manually # keep the system memory map consistant across multiple CPUs # in different linker commnd files. # # Make sure PyTI_PSDK_RTOS module is installed before running this script. # See vision_apps/tools/PyTI_PSDK_RTOS/README.txt to install PyTI_PSDK_RTOS module. # # Edit this file to change the memory map # # Run this script by doing below, # ./gen_linker_mem_map.py # # This will generate linker command file at below folders # ./<cpu name>/linker_mem_map.cmd # # Here CPU name is mpu1, c7x_1, c7x_2, mcu1_0, mcu2_0, mcu3_0 # # from ti_psdk_rtos_tools import * KB = 1024; MB = KB*KB; GB = KB*MB; # # Notes, # - recommend to keep all memory segment sizes in units of KB at least # # # On J721E/J7ES/TDA4VM, there are 2 DDR chipsets # # lower DDR address starts at 0x0000_8000_0000 # higher DDR address starts at 0x0008_8000_0000 # # As the address is non-contiguous it requires MMU to remap the address # Currently the upper 2GB is accessed by either ARM (user space) # C7x DSP heap/scratch space, as 32-bit cores like R5F cannot access it # # The upper DDR address is mapped contiguously from lower DDR address # but remapped to actual physical address using MMU # # physical lower DDR address range 0x0000_8000_0000 # virtual lower DDR address range 0x0000_8000_0000 # # physical lower DDR address range 0x0008_8000_0000 # virtual lower DDR address range 0x0001_0000_0000 # ddr_mem_addr = 0xa0000000; ddr_mem_size = 1*GB + 448*MB; # Last 64MB is used by Linux #ddr_mem_addr_hi_phy = 0x880000000; #ddr_mem_addr_hi = 0x100000000; #ddr_mem_size_hi = 736*MB; msmc_mem_addr = 0x70000000; main_ocram_mem_addr = 0x60000000; # Note: uses RAT to translate to proper address main_ocram_mem_addr_phys = 0x4F02000000; # # Other constant sizes # linux_ddr_ipc_size = 1*MB; linux_ddr_resource_table_size = 1*KB; # # MSMC memory allocation for various CPUs # dmsc_msmc_size = 64*KB; mpu1_msmc_addr = msmc_mem_addr; mpu1_msmc_size = 128*KB; c7x_1_msmc_addr = mpu1_msmc_addr + mpu1_msmc_size; misc_msmc_stack_size = 32*KB; c7x_1_msmc_size = 4*MB - mpu1_msmc_size - dmsc_msmc_size - misc_msmc_stack_size; dmsc_msmc_addr = c7x_1_msmc_addr + c7x_1_msmc_size + misc_msmc_stack_size; # # C7x L1, L2 memory allocation # L1 - 32KB $, 16KB SRAM # L2 - 64KB $, 448KB SRAM c7x_1_l2_addr = 0x64800000; c7x_1_l2_size = (512 - 64)*KB; c7x_1_l1_addr = 0x64E00000; c7x_1_l1_size = 16*KB; # # C7x L1, L2 memory allocation # L1 - 32KB $, 16KB SRAM # L2 - 64KB $, 448KB SRAM c7x_2_l2_addr = 0x65800000; c7x_2_l2_size = (512 - 64)*KB; c7x_2_l1_addr = 0x65E00000; c7x_2_l1_size = 16*KB; # # Main OCRAM memory allocation # mcu2_0_main_ocram_addr = main_ocram_mem_addr; mcu2_0_main_ocram_addr_phys = main_ocram_mem_addr_phys; mcu2_0_main_ocram_size = 512*KB; mcu2_1_main_ocram_addr = mcu2_0_main_ocram_addr + mcu2_0_main_ocram_size; mcu2_1_main_ocram_addr_phys = mcu2_0_main_ocram_addr_phys + mcu2_0_main_ocram_size; mcu2_1_main_ocram_size = 512*KB; # # DDR memory allocation for various CPUs # mcu1_0_ddr_ipc_addr = ddr_mem_addr; mcu1_0_ddr_resource_table_addr = mcu1_0_ddr_ipc_addr + linux_ddr_ipc_size; mcu1_0_ddr_addr = mcu1_0_ddr_resource_table_addr + linux_ddr_resource_table_size; mcu1_0_ddr_size = 16*MB - (mcu1_0_ddr_addr-mcu1_0_ddr_ipc_addr); mcu1_1_ddr_ipc_addr = mcu1_0_ddr_addr + mcu1_0_ddr_size; mcu1_1_ddr_resource_table_addr = mcu1_1_ddr_ipc_addr + linux_ddr_ipc_size; mcu1_1_ddr_addr = mcu1_1_ddr_resource_table_addr + linux_ddr_resource_table_size; mcu1_1_ddr_size = 16*MB - (mcu1_1_ddr_addr-mcu1_1_ddr_ipc_addr); mcu2_0_ddr_ipc_addr = mcu1_1_ddr_addr + mcu1_1_ddr_size; mcu2_0_ddr_resource_table_addr = mcu2_0_ddr_ipc_addr + linux_ddr_ipc_size; mcu2_0_ddr_addr = mcu2_0_ddr_resource_table_addr + linux_ddr_resource_table_size; mcu2_0_ddr_size = 32*MB - (mcu2_0_ddr_addr-mcu2_0_ddr_ipc_addr); mcu2_1_ddr_ipc_addr = mcu2_0_ddr_addr + mcu2_0_ddr_size; mcu2_1_ddr_resource_table_addr = mcu2_1_ddr_ipc_addr + linux_ddr_ipc_size; mcu2_1_ddr_addr = mcu2_1_ddr_resource_table_addr + linux_ddr_resource_table_size; mcu2_1_ddr_size = 32*MB - (mcu2_1_ddr_addr-mcu2_1_ddr_ipc_addr); mcu3_0_ddr_ipc_addr = mcu2_1_ddr_addr + mcu2_1_ddr_size; mcu3_0_ddr_resource_table_addr = mcu3_0_ddr_ipc_addr + linux_ddr_ipc_size; mcu3_0_ddr_addr = mcu3_0_ddr_resource_table_addr + linux_ddr_resource_table_size; mcu3_0_ddr_size = 16*MB - (mcu3_0_ddr_addr-mcu3_0_ddr_ipc_addr); mcu3_1_ddr_ipc_addr = mcu3_0_ddr_addr + mcu3_0_ddr_size; mcu3_1_ddr_resource_table_addr = mcu3_1_ddr_ipc_addr + linux_ddr_ipc_size; mcu3_1_ddr_addr = mcu3_1_ddr_resource_table_addr + linux_ddr_resource_table_size; mcu3_1_ddr_size = 16*MB - (mcu3_1_ddr_addr-mcu3_1_ddr_ipc_addr); # # DDR memory allocation for various shared memories # # Hardcoding this value, as this cannot be different from IPC echo test value ipc_vring_mem_addr = 0xA8000000; ipc_vring_mem_size = 32*MB; app_log_mem_addr = ipc_vring_mem_addr + ipc_vring_mem_size; app_log_mem_size = 256*KB; tiovx_obj_desc_mem_addr = app_log_mem_addr + app_log_mem_size; tiovx_obj_desc_mem_size = 64*MB - app_log_mem_size; app_fileio_mem_addr = tiovx_obj_desc_mem_addr + tiovx_obj_desc_mem_size; app_fileio_mem_size = 4*MB; tiovx_log_rt_mem_addr = app_fileio_mem_addr + app_fileio_mem_size; tiovx_log_rt_mem_size = 32*MB - app_fileio_mem_size; c7x_1_ddr_ipc_addr =tiovx_log_rt_mem_addr + tiovx_log_rt_mem_size; c7x_1_ddr_resource_table_addr = c7x_1_ddr_ipc_addr + linux_ddr_ipc_size; c7x_1_ddr_boot_addr = c7x_1_ddr_resource_table_addr + 1*MB; c7x_1_ddr_boot_size = 1*KB; c7x_1_ddr_vecs_addr = c7x_1_ddr_resource_table_addr + 3*MB; c7x_1_ddr_vecs_size = 16*KB; c7x_1_ddr_secure_vecs_addr = c7x_1_ddr_resource_table_addr + 5*MB; c7x_1_ddr_secure_vecs_size = 16*KB; c7x_1_ddr_addr = c7x_1_ddr_secure_vecs_addr + c7x_1_ddr_secure_vecs_size; c7x_1_ddr_size = 96*MB - (c7x_1_ddr_addr-c7x_1_ddr_ipc_addr); c7x_2_ddr_ipc_addr = c7x_1_ddr_addr + c7x_1_ddr_size; c7x_2_ddr_resource_table_addr = c7x_2_ddr_ipc_addr + linux_ddr_ipc_size; c7x_2_ddr_boot_addr = c7x_2_ddr_resource_table_addr + 1*MB; c7x_2_ddr_boot_size = 1*KB; c7x_2_ddr_vecs_addr = c7x_2_ddr_resource_table_addr + 3*MB; c7x_2_ddr_vecs_size = 16*KB; c7x_2_ddr_secure_vecs_addr = c7x_2_ddr_resource_table_addr + 5*MB; c7x_2_ddr_secure_vecs_size = 16*KB; c7x_2_ddr_addr = c7x_2_ddr_secure_vecs_addr + c7x_2_ddr_secure_vecs_size; c7x_2_ddr_size = 32*MB - (c7x_2_ddr_addr-c7x_2_ddr_ipc_addr); mcu1_0_ddr_local_heap_addr = c7x_2_ddr_addr + c7x_2_ddr_size; mcu1_0_ddr_local_heap_size = 8*MB; mcu1_1_ddr_local_heap_addr = mcu1_0_ddr_local_heap_addr + mcu1_0_ddr_local_heap_size; mcu1_1_ddr_local_heap_size = 8*MB; mcu2_0_ddr_local_heap_addr = mcu1_1_ddr_local_heap_addr + mcu1_1_ddr_local_heap_size; mcu2_0_ddr_local_heap_size = 14*MB; mcu2_0_ddr_viss_heap_addr = mcu2_0_ddr_local_heap_addr + mcu2_0_ddr_local_heap_size; mcu2_0_ddr_viss_heap_size = 2*MB; mcu2_1_ddr_local_heap_addr = mcu2_0_ddr_viss_heap_addr + mcu2_0_ddr_viss_heap_size; mcu2_1_ddr_local_heap_size = 16*MB; mcu3_0_ddr_local_heap_addr = mcu2_1_ddr_local_heap_addr + mcu2_1_ddr_local_heap_size; mcu3_0_ddr_local_heap_size = 8*MB; mcu3_1_ddr_local_heap_addr = mcu3_0_ddr_local_heap_addr + mcu3_0_ddr_local_heap_size; mcu3_1_ddr_local_heap_size = 8*MB; # Shared memory for DMA Buf FD carveout ddr_shared_mem_addr = 0xC0000000; # This will be the virtual address used for R5F's / C7X's ddr_shared_mem_size = 384*MB; c7x_1_ddr_scratch_addr = 0xD8000000; c7x_1_ddr_scratch_size = 304*MB; c7x_1_ddr_local_heap_addr = c7x_1_ddr_scratch_addr + c7x_1_ddr_scratch_size; c7x_1_ddr_local_heap_size = 256*MB; c7x_2_ddr_local_heap_addr = c7x_1_ddr_local_heap_addr + c7x_1_ddr_local_heap_size; c7x_2_ddr_local_heap_size = 16*MB; c7x_2_ddr_scratch_addr = c7x_2_ddr_local_heap_addr + c7x_2_ddr_local_heap_size; c7x_2_ddr_scratch_size = 64*MB; # Shared memory for DMA Buf FD carveout (located in high mem) ddr_shared_mem_addr_phys = 0xC0000000; # TODO: Clean this up #ddr_shared_mem_size = 512*MB; assert ddr_shared_mem_addr_phys & (ddr_shared_mem_size - 1) == 0 assert ddr_shared_mem_addr & (ddr_shared_mem_size - 1) == 0 # # Create memory section based on addr and size defined above, including # any CPU specific internal memories # # r5f local memory sections mcu_r5f_tcma_vecs = MemSection("R5F_TCMA_VECS" , "X" , 0x00000000, (KB >> 4)); mcu_r5f_tcma = MemSection("R5F_TCMA" , "X" , 0x00000040, (32*KB) - (KB >> 4)); r5f_tcmb0 = MemSection("R5F_TCMB0", "RWIX", 0x41010000, 32*KB); mcu_r5f_tcmb0_vecs = MemSection("R5F_TCMB0_VECS", "RWIX", 0x41010000, (KB >> 4)); mcu_r5f_tcmb0 = MemSection("R5F_TCMB0", "RWIX", 0x41010040, (32*KB) - (KB >> 4)); # MSMC memory sections mpu1_msmc = MemSection("MSMC_MPU1", "RWIX", mpu1_msmc_addr , mpu1_msmc_size , "MSMC reserved for MPU1 for ATF"); c7x_1_msmc = MemSection("MSMC_C7x_1", "RWIX", c7x_1_msmc_addr , c7x_1_msmc_size , "MSMC for C7x_1"); dmsc_msmc = MemSection("MSMC_DMSC", "RWIX", dmsc_msmc_addr , dmsc_msmc_size , "MSMC reserved for DMSC IPC"); # C7x L1/L2 memory sections c7x_1_l2 = MemSection("L2RAM_C7x_1", "RWIX", c7x_1_l2_addr , c7x_1_l2_size , "L2 for C7x_1"); c7x_1_l1 = MemSection("L1RAM_C7x_1", "RWIX", c7x_1_l1_addr , c7x_1_l1_size , "L1 for C7x_1"); c7x_2_l2 = MemSection("L2RAM_C7x_2", "RWIX", c7x_2_l2_addr , c7x_2_l2_size , "L2 for C7x_2"); c7x_2_l1 = MemSection("L1RAM_C7x_2", "RWIX", c7x_2_l1_addr , c7x_2_l1_size , "L1 for C7x_2"); # Main OCRAM memory sections mcu2_0_main_ocram = MemSection("MAIN_OCRAM_MCU2_0", "RWIX", mcu2_0_main_ocram_addr , mcu2_0_main_ocram_size , "Main OCRAM for MCU2_0"); mcu2_1_main_ocram = MemSection("MAIN_OCRAM_MCU2_1", "RWIX", mcu2_1_main_ocram_addr , mcu2_1_main_ocram_size , "Main OCRAM for MCU2_1"); mcu2_0_main_ocram_phys = MemSection("MAIN_OCRAM_MCU2_0_PHYS", "RWIX", mcu2_0_main_ocram_addr_phys , mcu2_0_main_ocram_size , "Main OCRAM Physical Address for MCU2_0"); mcu2_1_main_ocram_phys = MemSection("MAIN_OCRAM_MCU2_1_PHYS", "RWIX", mcu2_1_main_ocram_addr_phys , mcu2_1_main_ocram_size , "Main OCRAM Physical Address for MCU2_1"); # CPU code/data memory sections in DDR mcu1_0_ddr_ipc = MemSection("DDR_MCU1_0_IPC", "RWIX", mcu1_0_ddr_ipc_addr, linux_ddr_ipc_size, "DDR for MCU1_0 for Linux IPC"); mcu1_0_ddr_ipc.setDtsName("vision_apps_mcu_r5fss0_core0_dma_memory_region", "vision-apps-r5f-dma-memory"); mcu1_0_ddr_resource_table = MemSection("DDR_MCU1_0_RESOURCE_TABLE", "RWIX", mcu1_0_ddr_resource_table_addr, linux_ddr_resource_table_size, "DDR for MCU1_0 for Linux resource table"); mcu1_0_ddr = MemSection("DDR_MCU1_0", "RWIX", mcu1_0_ddr_addr, mcu1_0_ddr_size, "DDR for MCU1_0 for code/data"); mcu1_0_ddr_local_heap = MemSection("DDR_MCU1_0_LOCAL_HEAP", "RWIX", mcu1_0_ddr_local_heap_addr, mcu1_0_ddr_local_heap_size, "DDR for MCU1_0 for local heap"); mcu1_0_ddr_total = MemSection("DDR_MCU1_0_DTS", "", 0, 0, "DDR for MCU1_0 for all sections, used for reserving memory in DTS file"); mcu1_0_ddr_total.concat(mcu1_0_ddr_resource_table); mcu1_0_ddr_total.concat(mcu1_0_ddr); mcu1_0_ddr_total.setDtsName("vision_apps_mcu_r5fss0_core0_memory_region", "vision-apps-r5f-memory"); mcu1_1_ddr_ipc = MemSection("DDR_MCU1_1_IPC", "RWIX", mcu1_1_ddr_ipc_addr, linux_ddr_ipc_size, "DDR for MCU1_1 for Linux IPC"); mcu1_1_ddr_ipc.setDtsName("vision_apps_mcu_r5fss0_core1_dma_memory_region", "vision-apps-r5f-dma-memory"); mcu1_1_ddr_resource_table = MemSection("DDR_MCU1_1_RESOURCE_TABLE", "RWIX", mcu1_1_ddr_resource_table_addr, linux_ddr_resource_table_size, "DDR for MCU1_1 for Linux resource table"); mcu1_1_ddr = MemSection("DDR_MCU1_1", "RWIX", mcu1_1_ddr_addr, mcu1_1_ddr_size, "DDR for MCU1_1 for code/data"); mcu1_1_ddr_local_heap = MemSection("DDR_MCU1_1_LOCAL_HEAP", "RWIX", mcu1_1_ddr_local_heap_addr, mcu1_1_ddr_local_heap_size, "DDR for MCU1_1 for local heap"); mcu1_1_ddr_total = MemSection("DDR_MCU1_1_DTS", "", 0, 0, "DDR for MCU1_1 for all sections, used for reserving memory in DTS file"); mcu1_1_ddr_total.concat(mcu1_1_ddr_resource_table); mcu1_1_ddr_total.concat(mcu1_1_ddr); mcu1_1_ddr_total.setDtsName("vision_apps_mcu_r5fss0_core1_memory_region", "vision-apps-r5f-memory"); mcu2_0_ddr_ipc = MemSection("DDR_MCU2_0_IPC", "RWIX", mcu2_0_ddr_ipc_addr, linux_ddr_ipc_size, "DDR for MCU2_0 for Linux IPC"); mcu2_0_ddr_ipc.setDtsName("vision_apps_main_r5fss0_core0_dma_memory_region", "vision-apps-r5f-dma-memory"); mcu2_0_ddr_resource_table = MemSection("DDR_MCU2_0_RESOURCE_TABLE", "RWIX", mcu2_0_ddr_resource_table_addr, linux_ddr_resource_table_size, "DDR for MCU2_0 for Linux resource table"); mcu2_0_ddr = MemSection("DDR_MCU2_0", "RWIX", mcu2_0_ddr_addr, mcu2_0_ddr_size, "DDR for MCU2_0 for code/data"); mcu2_0_ddr_total = MemSection("DDR_MCU2_0_DTS", "", 0, 0, "DDR for MCU2_0 for all sections, used for reserving memory in DTS file"); mcu2_0_ddr_local_heap = MemSection("DDR_MCU2_0_LOCAL_HEAP", "RWIX", mcu2_0_ddr_local_heap_addr, mcu2_0_ddr_local_heap_size, "DDR for MCU2_0 for local heap"); mcu2_0_ddr_viss_config_heap = MemSection("DDR_MCU2_0_VISS_CONFIG_HEAP", "RWIX", mcu2_0_ddr_viss_heap_addr, mcu2_0_ddr_viss_heap_size, "VISS configuration memory. MUST be write through cache policy."); mcu2_0_ddr_total.concat(mcu2_0_ddr_resource_table); mcu2_0_ddr_total.concat(mcu2_0_ddr); mcu2_0_ddr_total.setDtsName("vision_apps_main_r5fss0_core0_memory_region", "vision-apps-r5f-memory"); mcu2_1_ddr_ipc = MemSection("DDR_MCU2_1_IPC", "RWIX", mcu2_1_ddr_ipc_addr, linux_ddr_ipc_size, "DDR for MCU2_1 for Linux IPC"); mcu2_1_ddr_ipc.setDtsName("vision_apps_main_r5fss0_core1_dma_memory_region", "vision-apps-r5f-dma-memory"); mcu2_1_ddr_resource_table = MemSection("DDR_MCU2_1_RESOURCE_TABLE", "RWIX", mcu2_1_ddr_resource_table_addr, linux_ddr_resource_table_size, "DDR for MCU2_1 for Linux resource table"); mcu2_1_ddr = MemSection("DDR_MCU2_1", "RWIX", mcu2_1_ddr_addr, mcu2_1_ddr_size, "DDR for MCU2_1 for code/data"); mcu2_1_ddr_total = MemSection("DDR_MCU2_1_DTS", "", 0, 0, "DDR for MCU2_1 for all sections, used for reserving memory in DTS file"); mcu2_1_ddr_local_heap = MemSection("DDR_MCU2_1_LOCAL_HEAP", "RWIX", mcu2_1_ddr_local_heap_addr, mcu2_1_ddr_local_heap_size, "DDR for MCU2_1 for local heap"); mcu2_1_ddr_total.concat(mcu2_1_ddr_resource_table); mcu2_1_ddr_total.concat(mcu2_1_ddr); mcu2_1_ddr_total.setDtsName("vision_apps_main_r5fss0_core1_memory_region", "vision-apps-r5f-memory"); mcu3_0_ddr_ipc = MemSection("DDR_MCU3_0_IPC", "RWIX", mcu3_0_ddr_ipc_addr, linux_ddr_ipc_size, "DDR for MCU3_0 for Linux IPC"); mcu3_0_ddr_ipc.setDtsName("vision_apps_main_r5fss1_core0_dma_memory_region", "vision-apps-r5f-dma-memory"); mcu3_0_ddr_resource_table = MemSection("DDR_MCU3_0_RESOURCE_TABLE", "RWIX", mcu3_0_ddr_resource_table_addr, linux_ddr_resource_table_size, "DDR for MCU3_0 for Linux resource table"); mcu3_0_ddr = MemSection("DDR_MCU3_0", "RWIX", mcu3_0_ddr_addr, mcu3_0_ddr_size, "DDR for MCU3_0 for code/data"); mcu3_0_ddr_local_heap = MemSection("DDR_MCU3_0_LOCAL_HEAP", "RWIX", mcu3_0_ddr_local_heap_addr, mcu3_0_ddr_local_heap_size, "DDR for MCU3_0 for local heap"); mcu3_0_ddr_total = MemSection("DDR_MCU3_0_DTS", "", 0, 0, "DDR for MCU3_0 for all sections, used for reserving memory in DTS file"); mcu3_0_ddr_total.concat(mcu3_0_ddr_resource_table); mcu3_0_ddr_total.concat(mcu3_0_ddr); mcu3_0_ddr_total.setDtsName("vision_apps_main_r5fss1_core0_memory_region", "vision-apps-r5f-memory"); mcu3_1_ddr_ipc = MemSection("DDR_MCU3_1_IPC", "RWIX", mcu3_1_ddr_ipc_addr, linux_ddr_ipc_size, "DDR for MCU3_1 for Linux IPC"); mcu3_1_ddr_ipc.setDtsName("vision_apps_main_r5fss1_core1_dma_memory_region", "vision-apps-r5f-dma-memory"); mcu3_1_ddr_resource_table = MemSection("DDR_MCU3_1_RESOURCE_TABLE", "RWIX", mcu3_1_ddr_resource_table_addr, linux_ddr_resource_table_size, "DDR for MCU3_1 for Linux resource table"); mcu3_1_ddr = MemSection("DDR_MCU3_1", "RWIX", mcu3_1_ddr_addr, mcu3_1_ddr_size, "DDR for MCU3_1 for code/data"); mcu3_1_ddr_local_heap = MemSection("DDR_MCU3_1_LOCAL_HEAP", "RWIX", mcu3_1_ddr_local_heap_addr, mcu3_1_ddr_local_heap_size, "DDR for MCU3_1 for local heap"); mcu3_1_ddr_total = MemSection("DDR_MCU3_1_DTS", "", 0, 0, "DDR for MCU3_1 for all sections, used for reserving memory in DTS file"); mcu3_1_ddr_total.concat(mcu3_1_ddr_resource_table); mcu3_1_ddr_total.concat(mcu3_1_ddr); mcu3_1_ddr_total.setDtsName("vision_apps_main_r5fss1_core1_memory_region", "vision-apps-r5f-memory"); c7x_2_ddr_ipc = MemSection("DDR_C7x_2_IPC", "RWIX", c7x_2_ddr_ipc_addr, linux_ddr_ipc_size, "DDR for C7x_2 for Linux IPC"); c7x_2_ddr_ipc.setDtsName("vision_apps_c71_1_dma_memory_region", "vision-apps-c71_1-dma-memory"); c7x_2_ddr_resource_table = MemSection("DDR_C7x_2_RESOURCE_TABLE", "RWIX", c7x_2_ddr_resource_table_addr, linux_ddr_resource_table_size, "DDR for C7x_2 for Linux resource table"); c7x_2_ddr_boot = MemSection("DDR_C7x_2_BOOT", "RWIX", c7x_2_ddr_boot_addr, c7x_2_ddr_boot_size, "DDR for C7x_2 for boot section"); c7x_2_ddr_vecs = MemSection("DDR_C7x_2_VECS", "RWIX", c7x_2_ddr_vecs_addr, c7x_2_ddr_vecs_size, "DDR for C7x_2 for vecs section"); c7x_2_ddr_secure_vecs = MemSection("DDR_C7x_2_SECURE_VECS", "RWIX", c7x_2_ddr_secure_vecs_addr, c7x_2_ddr_secure_vecs_size, "DDR for C7x_2 for secure vecs section"); c7x_2_ddr = MemSection("DDR_C7x_2", "RWIX", c7x_2_ddr_addr, c7x_2_ddr_size, "DDR for C7x_2 for code/data"); c7x_2_ddr_local_heap = MemSection("DDR_C7X_2_LOCAL_HEAP", "RWIX", c7x_2_ddr_local_heap_addr, c7x_2_ddr_local_heap_size, "DDR for c7x_2 for local heap"); c7x_2_ddr_scratch = MemSection("DDR_C7X_2_SCRATCH", "RWIX", c7x_2_ddr_scratch_addr, c7x_2_ddr_scratch_size, "DDR for c7x_2 for Scratch Memory"); c7x_2_ddr_total = MemSection("DDR_C7x_2_DTS", "", 0, 0, "DDR for C7x_2 for all sections, used for reserving memory in DTS file"); c7x_2_ddr_total.concat(c7x_2_ddr_resource_table); c7x_2_ddr_total.concat(c7x_2_ddr_boot); c7x_2_ddr_total.concat(c7x_2_ddr_vecs); c7x_2_ddr_total.concat(c7x_2_ddr_secure_vecs); c7x_2_ddr_total.concat(c7x_2_ddr); c7x_2_ddr_total.setDtsName("vision_apps_c71_1_memory_region", "vision-apps-c71_1-memory"); c7x_1_ddr_ipc = MemSection("DDR_C7x_1_IPC", "RWIX", c7x_1_ddr_ipc_addr, linux_ddr_ipc_size, "DDR for C7x_1 for Linux IPC"); c7x_1_ddr_ipc.setDtsName("vision_apps_c71_0_dma_memory_region", "vision-apps-c71-dma-memory"); c7x_1_ddr_resource_table = MemSection("DDR_C7x_1_RESOURCE_TABLE", "RWIX", c7x_1_ddr_resource_table_addr, linux_ddr_resource_table_size, "DDR for C7x_1 for Linux resource table"); c7x_1_ddr_boot = MemSection("DDR_C7x_1_BOOT", "RWIX", c7x_1_ddr_boot_addr, c7x_1_ddr_boot_size, "DDR for C7x_1 for boot section"); c7x_1_ddr_vecs = MemSection("DDR_C7x_1_VECS", "RWIX", c7x_1_ddr_vecs_addr, c7x_1_ddr_vecs_size, "DDR for C7x_1 for vecs section"); c7x_1_ddr_secure_vecs = MemSection("DDR_C7x_1_SECURE_VECS", "RWIX", c7x_1_ddr_secure_vecs_addr, c7x_1_ddr_secure_vecs_size, "DDR for C7x_1 for secure vecs section"); c7x_1_ddr = MemSection("DDR_C7x_1", "RWIX", c7x_1_ddr_addr, c7x_1_ddr_size, "DDR for C7x_1 for code/data"); c7x_1_ddr_local_heap = MemSection("DDR_C7X_1_LOCAL_HEAP", "RWIX", c7x_1_ddr_local_heap_addr, c7x_1_ddr_local_heap_size, "DDR for c7x_1 for local heap"); c7x_1_ddr_scratch = MemSection("DDR_C7X_1_SCRATCH", "RWIX", c7x_1_ddr_scratch_addr, c7x_1_ddr_scratch_size, "DDR for c7x_1 for Scratch Memory"); c7x_1_ddr_total = MemSection("DDR_C7x_1_DTS", "", 0, 0, "DDR for C7x_1 for all sections, used for reserving memory in DTS file"); c7x_1_ddr_total.concat(c7x_1_ddr_resource_table); c7x_1_ddr_total.concat(c7x_1_ddr_boot); c7x_1_ddr_total.concat(c7x_1_ddr_vecs); c7x_1_ddr_total.concat(c7x_1_ddr_secure_vecs); c7x_1_ddr_total.concat(c7x_1_ddr); c7x_1_ddr_total.setDtsName("vision_apps_c71_0_memory_region", "vision-apps-c71_0-memory"); # Shared memory memory sections in DDR app_log_mem = MemSection("APP_LOG_MEM" , "", app_log_mem_addr , app_log_mem_size , "Memory for remote core logging"); tiovx_obj_desc_mem = MemSection("TIOVX_OBJ_DESC_MEM" , "", tiovx_obj_desc_mem_addr, tiovx_obj_desc_mem_size, "Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent"); app_fileio_mem = MemSection("APP_FILEIO_MEM" , "", app_fileio_mem_addr , app_fileio_mem_size , "Memory for remote core file operations"); tiovx_log_rt_mem = MemSection("TIOVX_LOG_RT_MEM" , "", tiovx_log_rt_mem_addr, tiovx_log_rt_mem_size, "Memory for TI OpenVX shared memory for Run-time logging. MUST be non-cached or cache-coherent"); ipc_vring_mem = MemSection("IPC_VRING_MEM" , "", ipc_vring_mem_addr , ipc_vring_mem_size , "Memory for IPC Vring's. MUST be non-cached or cache-coherent"); ipc_vring_mem.setDtsName("vision_apps_rtos_ipc_memory_region", "vision-apps-rtos-ipc-memory-region"); vision_apps_ddr_total = MemSection("DDR_VISION_APPS_DTS", "", 0 , 0 , "DDR for Vision Apps for all sections, used for reserving memory in DTS file"); vision_apps_ddr_total.concat(app_log_mem); vision_apps_ddr_total.concat(tiovx_obj_desc_mem); vision_apps_ddr_total.concat(app_fileio_mem); vision_apps_ddr_total.concat(tiovx_log_rt_mem); vision_apps_ddr_total.setDtsName("vision_apps_memory_region", "vision-apps-dma-memory"); vision_apps_core_heaps_lo = MemSection("DDR_VISION_APPS_CORE_HEAPS_LO_DTS", "", 0, 0, "Vision Apps Core Heaps in 32bit address range of DDR"); vision_apps_core_heaps_lo.concat(mcu1_0_ddr_local_heap); vision_apps_core_heaps_lo.concat(mcu2_0_ddr_local_heap); vision_apps_core_heaps_lo.concat(mcu2_0_ddr_viss_config_heap); vision_apps_core_heaps_lo.concat(mcu2_1_ddr_local_heap); vision_apps_core_heaps_lo.concat(mcu3_0_ddr_local_heap); vision_apps_core_heaps_lo.concat(mcu3_1_ddr_local_heap); vision_apps_core_heaps_lo.setDtsName("vision_apps_core_heaps_lo", "vision-apps-core-heap-memory-lo"); #c7x_1_ddr_local_heap_phy = MemSection("DDR_C7X_1_LOCAL_HEAP", "RWIX", ddr_mem_addr_hi_phy, (c7x_1_ddr_scratch_size + c7x_1_ddr_local_heap_size + c7x_2_ddr_scratch_size + c7x_2_ddr_local_heap_size), "DDR for c7x_1, c7x_2 for scratch memory and local heap"); c7x_1_ddr_scratch_mem = MemSection("C7X_1_DDR_SCRATCH_MEM" , "", c7x_1_ddr_scratch_addr , c7x_1_ddr_scratch_size , "Memory for remote core logging"); c7x_1_ddr_local_heap_mem = MemSection("C7X_1_DDR_LOCAL_HEAP_MEM" , "", c7x_1_ddr_local_heap_addr , c7x_1_ddr_local_heap_size , "Memory for remote core logging"); c7x_2_ddr_local_heap_mem = MemSection("C7X_2_DDR_LOCAL_HEAP_MEM" , "", c7x_2_ddr_local_heap_addr , c7x_2_ddr_local_heap_size , "Memory for remote core logging"); c7x_2_ddr_scratch_mem = MemSection("C7X_2_DDR_SCRATCH_MEM" , "", c7x_2_ddr_scratch_addr , c7x_2_ddr_scratch_size , "Memory for remote core logging"); c7x_ddr_heaps_hi = MemSection("DDR_VISION_APPS_CORE_HEAPS_HI_DTS", "", 0, 0, "Vision Apps Core Heaps in DDR"); c7x_ddr_heaps_hi.concat(c7x_1_ddr_scratch_mem); c7x_ddr_heaps_hi.concat(c7x_1_ddr_local_heap_mem); c7x_ddr_heaps_hi.concat(c7x_2_ddr_local_heap_mem); c7x_ddr_heaps_hi.concat(c7x_2_ddr_scratch_mem); c7x_ddr_heaps_hi.setDtsName("c7x_ddr_heaps_hi", "c7x_ddr_heaps_hi-apps-core-heap-memory-hi"); #c7x_ddr_heaps_hi.splitOrigin(True) # this region should NOT have the "no-map" flag since we want ION to map this memory and do cache ops on it as needed ddr_shared_mem = MemSection("DDR_SHARED_MEM" , "", ddr_shared_mem_addr , ddr_shared_mem_size , "Memory for shared memory buffers in DDR"); ddr_shared_mem_phys = MemSection("DDR_SHARED_MEM_PHYS" , "", ddr_shared_mem_addr_phys , ddr_shared_mem_size , "Physical address of memory for shared memory buffers in DDR"); ddr_shared_mem_phys.setDtsName("vision_apps_shared_region", "vision_apps_shared-memories"); ddr_shared_mem_phys.setCompatibility("dma-heap-carveout"); ddr_shared_mem_phys.setNoMap(False); ddr_shared_mem_phys.setOriginTag(False); #ddr_shared_mem_phys.splitOrigin(True) # # Create CPU specific memory maps using memory sections created above # mcu1_0_mmap = MemoryMap("mcu1_0"); mcu1_0_mmap.addMemSection( mcu_r5f_tcma_vecs ); mcu1_0_mmap.addMemSection( mcu_r5f_tcma ); mcu1_0_mmap.addMemSection( mcu_r5f_tcmb0_vecs ); mcu1_0_mmap.addMemSection( mcu_r5f_tcmb0 ); mcu1_0_mmap.addMemSection( mcu1_0_ddr_ipc ); mcu1_0_mmap.addMemSection( mcu1_0_ddr_resource_table ); mcu1_0_mmap.addMemSection( mcu1_0_ddr ); mcu1_0_mmap.addMemSection( app_log_mem ); mcu1_0_mmap.addMemSection( tiovx_obj_desc_mem ); mcu1_0_mmap.addMemSection( app_fileio_mem ); mcu1_0_mmap.addMemSection( ipc_vring_mem ); mcu1_0_mmap.addMemSection( mcu1_0_ddr_local_heap ); mcu1_0_mmap.addMemSection( ddr_shared_mem ); mcu1_0_mmap.checkOverlap(); mcu1_1_mmap = MemoryMap("mcu1_1"); mcu1_1_mmap.addMemSection( mcu_r5f_tcma_vecs ); mcu1_1_mmap.addMemSection( mcu_r5f_tcma ); mcu1_1_mmap.addMemSection( mcu_r5f_tcmb0_vecs ); mcu1_1_mmap.addMemSection( mcu_r5f_tcmb0 ); mcu1_1_mmap.addMemSection( mcu1_1_ddr_ipc ); mcu1_1_mmap.addMemSection( mcu1_1_ddr_resource_table ); mcu1_1_mmap.addMemSection( mcu1_1_ddr ); mcu1_1_mmap.addMemSection( app_log_mem ); mcu1_1_mmap.addMemSection( tiovx_obj_desc_mem ); mcu1_1_mmap.addMemSection( app_fileio_mem ); mcu1_1_mmap.addMemSection( ipc_vring_mem ); mcu1_1_mmap.addMemSection( mcu1_1_ddr_local_heap ); mcu1_1_mmap.addMemSection( ddr_shared_mem ); mcu1_1_mmap.checkOverlap(); mcu2_0_mmap = MemoryMap("mcu2_0"); mcu2_0_mmap.addMemSection( mcu_r5f_tcma_vecs ); mcu2_0_mmap.addMemSection( mcu_r5f_tcma ); mcu2_0_mmap.addMemSection( r5f_tcmb0 ); mcu2_0_mmap.addMemSection( mcu2_0_ddr_ipc ); mcu2_0_mmap.addMemSection( mcu2_0_ddr_resource_table ); mcu2_0_mmap.addMemSection( mcu2_0_ddr ); mcu2_0_mmap.addMemSection( app_log_mem ); mcu2_0_mmap.addMemSection( tiovx_obj_desc_mem ); mcu2_0_mmap.addMemSection( app_fileio_mem ); mcu2_0_mmap.addMemSection( ipc_vring_mem ); mcu2_0_mmap.addMemSection( mcu2_0_ddr_local_heap ); mcu2_0_mmap.addMemSection( mcu2_0_ddr_viss_config_heap ); mcu2_0_mmap.addMemSection( ddr_shared_mem ); mcu2_0_mmap.addMemSection( mcu2_0_main_ocram ); mcu2_0_mmap.checkOverlap(); mcu2_1_mmap = MemoryMap("mcu2_1"); mcu2_1_mmap.addMemSection( mcu_r5f_tcma_vecs ); mcu2_1_mmap.addMemSection( mcu_r5f_tcma ); mcu2_1_mmap.addMemSection( r5f_tcmb0 ); mcu2_1_mmap.addMemSection( mcu2_1_ddr_ipc ); mcu2_1_mmap.addMemSection( mcu2_1_ddr_resource_table ); mcu2_1_mmap.addMemSection( mcu2_1_ddr ); mcu2_1_mmap.addMemSection( app_log_mem ); mcu2_1_mmap.addMemSection( tiovx_obj_desc_mem ); mcu2_1_mmap.addMemSection( app_fileio_mem ); mcu2_1_mmap.addMemSection( ipc_vring_mem ); mcu2_1_mmap.addMemSection( mcu2_1_ddr_local_heap ); mcu2_1_mmap.addMemSection( ddr_shared_mem ); mcu2_1_mmap.addMemSection( mcu2_1_main_ocram ); mcu2_1_mmap.checkOverlap(); mcu3_0_mmap = MemoryMap("mcu3_0"); mcu3_0_mmap.addMemSection( mcu_r5f_tcma_vecs ); mcu3_0_mmap.addMemSection( mcu_r5f_tcma ); mcu3_0_mmap.addMemSection( r5f_tcmb0 ); mcu3_0_mmap.addMemSection( mcu3_0_ddr_ipc ); mcu3_0_mmap.addMemSection( mcu3_0_ddr_resource_table ); mcu3_0_mmap.addMemSection( mcu3_0_ddr ); mcu3_0_mmap.addMemSection( app_log_mem ); mcu3_0_mmap.addMemSection( tiovx_obj_desc_mem ); mcu3_0_mmap.addMemSection( app_fileio_mem ); mcu3_0_mmap.addMemSection( ipc_vring_mem ); mcu3_0_mmap.addMemSection( mcu3_0_ddr_local_heap ); mcu3_0_mmap.addMemSection( ddr_shared_mem ); mcu3_0_mmap.checkOverlap(); mcu3_1_mmap = MemoryMap("mcu3_1"); mcu3_1_mmap.addMemSection( mcu_r5f_tcma_vecs ); mcu3_1_mmap.addMemSection( mcu_r5f_tcma ); mcu3_1_mmap.addMemSection( r5f_tcmb0 ); mcu3_1_mmap.addMemSection( mcu3_1_ddr_ipc ); mcu3_1_mmap.addMemSection( mcu3_1_ddr_resource_table ); mcu3_1_mmap.addMemSection( mcu3_1_ddr ); mcu3_1_mmap.addMemSection( app_log_mem ); mcu3_1_mmap.addMemSection( tiovx_obj_desc_mem ); mcu3_1_mmap.addMemSection( app_fileio_mem ); mcu3_1_mmap.addMemSection( ipc_vring_mem ); mcu3_1_mmap.addMemSection( mcu3_1_ddr_local_heap ); mcu3_1_mmap.addMemSection( ddr_shared_mem ); mcu3_1_mmap.checkOverlap(); c7x_1_mmap = MemoryMap("c7x_1"); c7x_1_mmap.addMemSection( c7x_1_l2 ); c7x_1_mmap.addMemSection( c7x_1_l1 ); c7x_1_mmap.addMemSection( c7x_1_msmc ); c7x_1_mmap.addMemSection( c7x_1_ddr_ipc ); c7x_1_mmap.addMemSection( c7x_1_ddr_resource_table ); c7x_1_mmap.addMemSection( c7x_1_ddr_boot ); c7x_1_mmap.addMemSection( c7x_1_ddr_vecs ); c7x_1_mmap.addMemSection( c7x_1_ddr_secure_vecs ); c7x_1_mmap.addMemSection( c7x_1_ddr ); c7x_1_mmap.addMemSection( app_log_mem ); c7x_1_mmap.addMemSection( tiovx_obj_desc_mem ); c7x_1_mmap.addMemSection( app_fileio_mem ); c7x_1_mmap.addMemSection( ipc_vring_mem ); c7x_1_mmap.addMemSection( c7x_1_ddr_local_heap ); c7x_1_mmap.addMemSection( c7x_1_ddr_scratch ); c7x_1_mmap.addMemSection( ddr_shared_mem ); c7x_1_mmap.checkOverlap(); c7x_2_mmap = MemoryMap("c7x_2"); c7x_2_mmap.addMemSection( c7x_2_l2 ); c7x_2_mmap.addMemSection( c7x_2_l1 ); c7x_2_mmap.addMemSection( c7x_2_ddr_ipc ); c7x_2_mmap.addMemSection( c7x_2_ddr_resource_table ); c7x_2_mmap.addMemSection( c7x_2_ddr_boot ); c7x_2_mmap.addMemSection( c7x_2_ddr_vecs ); c7x_2_mmap.addMemSection( c7x_2_ddr_secure_vecs ); c7x_2_mmap.addMemSection( c7x_2_ddr ); c7x_2_mmap.addMemSection( app_log_mem ); c7x_2_mmap.addMemSection( tiovx_obj_desc_mem ); c7x_2_mmap.addMemSection( app_fileio_mem ); c7x_2_mmap.addMemSection( ipc_vring_mem ); c7x_2_mmap.addMemSection( c7x_2_ddr_local_heap ); c7x_2_mmap.addMemSection( c7x_2_ddr_scratch ); c7x_2_mmap.addMemSection( ddr_shared_mem ); c7x_2_mmap.checkOverlap(); html_mmap = MemoryMap("System Memory Map for Linux+RTOS mode"); html_mmap.addMemSection( c7x_1_l2 ); html_mmap.addMemSection( c7x_1_l1 ); html_mmap.addMemSection( c7x_2_l2 ); html_mmap.addMemSection( c7x_2_l1 ); html_mmap.addMemSection( mpu1_msmc ); html_mmap.addMemSection( c7x_1_msmc ); html_mmap.addMemSection( dmsc_msmc ); html_mmap.addMemSection( mcu1_0_ddr_ipc ); html_mmap.addMemSection( mcu1_0_ddr_resource_table ); html_mmap.addMemSection( mcu1_0_ddr ); html_mmap.addMemSection( mcu1_0_ddr_local_heap ); html_mmap.addMemSection( mcu1_1_ddr_ipc ); html_mmap.addMemSection( mcu1_1_ddr_resource_table ); html_mmap.addMemSection( mcu1_1_ddr ); html_mmap.addMemSection( mcu1_1_ddr_local_heap ); html_mmap.addMemSection( mcu2_0_ddr_ipc ); html_mmap.addMemSection( mcu2_0_ddr_resource_table ); html_mmap.addMemSection( mcu2_0_ddr ); html_mmap.addMemSection( mcu2_0_ddr_local_heap ); html_mmap.addMemSection( mcu2_0_ddr_viss_config_heap ); html_mmap.addMemSection( mcu2_1_ddr_ipc ); html_mmap.addMemSection( mcu2_1_ddr_resource_table ); html_mmap.addMemSection( mcu2_1_ddr ); html_mmap.addMemSection( mcu2_1_ddr_local_heap ); html_mmap.addMemSection( mcu3_0_ddr_ipc ); html_mmap.addMemSection( mcu3_0_ddr_resource_table ); html_mmap.addMemSection( mcu3_0_ddr ); html_mmap.addMemSection( mcu3_0_ddr_local_heap ); html_mmap.addMemSection( mcu3_1_ddr_ipc ); html_mmap.addMemSection( mcu3_1_ddr_resource_table ); html_mmap.addMemSection( mcu3_1_ddr ); html_mmap.addMemSection( mcu3_1_ddr_local_heap ); html_mmap.addMemSection( c7x_1_ddr_ipc ); html_mmap.addMemSection( c7x_1_ddr_resource_table ); html_mmap.addMemSection( c7x_1_ddr_boot ); html_mmap.addMemSection( c7x_1_ddr_vecs ); html_mmap.addMemSection( c7x_1_ddr_secure_vecs ); html_mmap.addMemSection( c7x_1_ddr_local_heap ); html_mmap.addMemSection( c7x_1_ddr_scratch ); html_mmap.addMemSection( c7x_1_ddr ); html_mmap.addMemSection( c7x_2_ddr_ipc ); html_mmap.addMemSection( c7x_2_ddr_resource_table ); html_mmap.addMemSection( c7x_2_ddr_boot ); html_mmap.addMemSection( c7x_2_ddr_vecs ); html_mmap.addMemSection( c7x_2_ddr_secure_vecs ); html_mmap.addMemSection( c7x_2_ddr_local_heap ); html_mmap.addMemSection( c7x_2_ddr_scratch ); html_mmap.addMemSection( c7x_2_ddr ); html_mmap.addMemSection( app_log_mem ); html_mmap.addMemSection( tiovx_obj_desc_mem ); html_mmap.addMemSection( app_fileio_mem ); html_mmap.addMemSection( ipc_vring_mem ); html_mmap.addMemSection( ddr_shared_mem ); html_mmap.addMemSection( tiovx_log_rt_mem ); html_mmap.addMemSection( mcu2_0_main_ocram ); html_mmap.addMemSection( mcu2_1_main_ocram ); html_mmap.checkOverlap(); c_header_mmap = MemoryMap("Memory Map for C header file"); c_header_mmap.addMemSection( c7x_1_l2 ); c_header_mmap.addMemSection( c7x_1_l1 ); c_header_mmap.addMemSection( c7x_1_msmc ); c_header_mmap.addMemSection( c7x_2_l2 ); c_header_mmap.addMemSection( c7x_2_l1 ); c_header_mmap.addMemSection( mcu1_0_ddr_ipc ); c_header_mmap.addMemSection( mcu1_1_ddr_ipc ); c_header_mmap.addMemSection( mcu2_0_ddr_ipc ); c_header_mmap.addMemSection( mcu2_1_ddr_ipc ); c_header_mmap.addMemSection( mcu3_0_ddr_ipc ); c_header_mmap.addMemSection( mcu3_1_ddr_ipc ); c_header_mmap.addMemSection( c7x_1_ddr_ipc ); c_header_mmap.addMemSection( c7x_2_ddr_ipc ); c_header_mmap.addMemSection( mcu1_0_ddr_total ); c_header_mmap.addMemSection( mcu1_1_ddr_total ); c_header_mmap.addMemSection( mcu2_0_ddr_total ); c_header_mmap.addMemSection( mcu2_1_ddr_total ); c_header_mmap.addMemSection( mcu3_0_ddr_total ); c_header_mmap.addMemSection( mcu3_1_ddr_total ); c_header_mmap.addMemSection( c7x_1_ddr_total ); c_header_mmap.addMemSection( c7x_2_ddr_total ); c_header_mmap.addMemSection( mcu1_0_ddr_local_heap); c_header_mmap.addMemSection( mcu1_1_ddr_local_heap); c_header_mmap.addMemSection( mcu2_0_ddr_local_heap); c_header_mmap.addMemSection( mcu2_0_ddr_viss_config_heap); c_header_mmap.addMemSection( mcu2_1_ddr_local_heap); c_header_mmap.addMemSection( mcu3_0_ddr_local_heap); c_header_mmap.addMemSection( mcu3_1_ddr_local_heap); c_header_mmap.addMemSection( c7x_1_ddr_local_heap); c_header_mmap.addMemSection( c7x_1_ddr_scratch); c_header_mmap.addMemSection( c7x_2_ddr_local_heap); c_header_mmap.addMemSection( c7x_2_ddr_scratch); c_header_mmap.addMemSection( tiovx_log_rt_mem ); c_header_mmap.addMemSection( app_log_mem ); c_header_mmap.addMemSection( tiovx_obj_desc_mem ); c_header_mmap.addMemSection( app_fileio_mem ); c_header_mmap.addMemSection( ipc_vring_mem ); c_header_mmap.addMemSection( ddr_shared_mem ); c_header_mmap.addMemSection( ddr_shared_mem_phys ); c_header_mmap.addMemSection( c7x_1_msmc ); c_header_mmap.addMemSection( mcu2_0_main_ocram ); c_header_mmap.addMemSection( mcu2_1_main_ocram ); c_header_mmap.addMemSection( mcu2_0_main_ocram_phys ); c_header_mmap.addMemSection( mcu2_1_main_ocram_phys ); c_header_mmap.checkOverlap(); dts_mmap = MemoryMap("Memory Map for Linux kernel dts/dtsi file"); dts_mmap.addMemSection( mcu1_0_ddr_ipc ); dts_mmap.addMemSection( mcu1_0_ddr_total ); dts_mmap.addMemSection( mcu1_1_ddr_ipc ); dts_mmap.addMemSection( mcu1_1_ddr_total ); dts_mmap.addMemSection( mcu2_0_ddr_ipc ); dts_mmap.addMemSection( mcu2_0_ddr_total ); dts_mmap.addMemSection( mcu2_1_ddr_ipc ); dts_mmap.addMemSection( mcu2_1_ddr_total ); dts_mmap.addMemSection( mcu3_0_ddr_ipc ); dts_mmap.addMemSection( mcu3_0_ddr_total ); dts_mmap.addMemSection( mcu3_1_ddr_ipc ); dts_mmap.addMemSection( mcu3_1_ddr_total ); dts_mmap.addMemSection( c7x_1_ddr_ipc ); dts_mmap.addMemSection( c7x_1_ddr_total ); dts_mmap.addMemSection( c7x_2_ddr_ipc ); dts_mmap.addMemSection( c7x_2_ddr_total ); dts_mmap.addMemSection( vision_apps_ddr_total ); dts_mmap.addMemSection( ipc_vring_mem ); dts_mmap.addMemSection( vision_apps_core_heaps_lo ); dts_mmap.addMemSection( c7x_ddr_heaps_hi ); dts_mmap.addMemSection( ddr_shared_mem_phys ); dts_mmap.checkOverlap(); # # Generate linker command files containing "MEMORY" definitions # LinkerCmdFile(c7x_1_mmap , "./c7x_1/linker_mem_map.cmd" ).export(); LinkerCmdFile(c7x_2_mmap , "./c7x_2/linker_mem_map.cmd" ).export(); LinkerCmdFile(mcu1_0_mmap, "./mcu1_0/linker_mem_map.cmd").export(); LinkerCmdFile(mcu1_1_mmap, "./mcu1_1/linker_mem_map.cmd").export(); LinkerCmdFile(mcu2_0_mmap, "./mcu2_0/linker_mem_map.cmd").export(); LinkerCmdFile(mcu2_1_mmap, "./mcu2_1/linker_mem_map.cmd").export(); LinkerCmdFile(mcu3_0_mmap, "./mcu3_0/linker_mem_map.cmd").export(); LinkerCmdFile(mcu3_1_mmap, "./mcu3_1/linker_mem_map.cmd").export(); HtmlMmapTable(html_mmap, "./system_memory_map.html").export(); CHeaderFile(c_header_mmap, 0x880000000, 0x100000000, "./app_mem_map.h").export(); DtsFile(dts_mmap, "./k3-j721s2-rtos-memory-map.dtsi").export();
Hello,
The engineer assigned is out of the office until 9/26.
Please expect a delay in response.
-Josue
Hi,
There seems to be a crash in the C7x_1 and C7x_2 cores from your remote logs in memory initialization
[C7x_2 ] 5.249438 s: MEM: Init ... !!!
[C7x_2 ] 5.249453 s: A0 =0xffff00 A1 =0x27000000
[C7x_2 ] 5.249469 s: A2 =0x1 A3 =0xaa020020
[C7x_2 ] 5.249479 s: A4 =0xb685ab18 A5 =0x27000000
[C7x_2 ] 5.249491 s: A6 =0x1000000 A7 =0x0
Please check why this error occurs. Please check if you have updated the mmu mapping of C7x cores accordingly.
Regards,
Nikhil
Yeah I was wondering about that. It does sort of look like a stack dump. I'll start looking into what's going on.
Please check if you have updated the mmu mapping of C7x cores accordingly
Could you be more specific please? I was under the impression that the python script generates a header used by all of the cores to setup their mmu mapping. Is there an additional step?
Alright I've solved my problem. There were a few issues.
I had missed one step here which was to reduce the number of DDR instances in `app_utils`.
The bigger issue is that yocto does not rebuild the firmware. So changes to `ti-vision-apps` and the repos pointed to by `psdk_repo_manifests` don't get applied to the edgeai firmware which is prebuilt. I followed instructions here to rebuild the firmware.
Nikhil thanks for pointing me in the right direction.