TDA4VH-Q1: PCIE probe err

Hi,

It means that you are not able to the serdes PLLs.

Have you changed the clocking for serdes? Or made any changes in the serdes nodes?

Regards,

Tanmay

we use default clk config, how can we modify de clocking for serdes , thanks

Hi,

What are the changes you made overall on top of default device-tree?

Is this issue seen on EVM or custom board?

Regards,
Tanmay

Hi, 

this is custom board, we use：

• SERDES0 lane0 lane1 for PCIE1,
• SERDES0 lane2 lane3 for PCIE3,
• SERDES1 lane2 lane3 for PCIE2;

we use default config "k3-j784s4-main.dtsi";

we use internal refclk;

when probe  pcie3 and pcie2 report err;

we noted issue "">e2e.ti.com/.../faq-tda4vm-tda4vm-dra829v-routing-pcie-reference-clock-externally"

but this is modifed on k3-j721e .

what we need to modify ? thanks 

&serdes1 {
    status = "okay";
    serdes1_pcie_link:phy@2 {
        reg = <2>;
        cdns,num-lanes = <2>;
        #phy-cells= <0>;
        cdns,phy-type = <PHY_TYPE_PCIE>;
        resets = <&serdes_wiz1 3>, <&serdes_wiz1 4>;
    };
};

&pcie0_rc {
    status = "disabled";
    num-lanes = <2>;
    reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
    phy-names = "pcie-phy";
}

&serdes1 {
    status = "okay";
    serdes1_pcie_link:phy@0 {
        reg = <0>;
        cdns,num-lanes = <2>;
        #phy-cells= <0>;
        cdns,phy-type = <PHY_TYPE_PCIE>;
        resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
    };
};

&pcie0_rc {
    status = "disabled";
    num-lanes = <2>;
    reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
    phy-names = "pcie-phy";
}

chen chen said:

we can create pcie root bus,thanks.

Hello Chen Chen

    so this issue already fixed?

Regards

   Semon