AM625: Need to disable to clock_out pin of eth0 and eth1

Hello Abhishek,

Just to clarify

1. You are using the Linux SDK on AM625? If so, which SDK version are you using?

2. Is this a custom board or the SK-AM62B-P1 EVM you are using?

From my understanding, devmem2 will only modify the AM625 registers. If you are trying to modify a register on the PHY chip itself, you would most likely have to use phytool.

Since this appears to be more of a question about the PHY chip itself, I will be redirecting your inquiry to the TI Ethernet PHY team. 

-Daolin

Hi Daolin Qiu,

I am using Yocto SDK 9.1.

We have a custom board based on AM6254ATCGGAALW SOC.

Regards,

Abhishek

Hi Abhishek!

I'm from the Ethernet team and will assist you in disabling the CLKOUT signal. Firstly I would like to confirm how you are accessing the PHY's registers. I would also like to point out that Reg 0x170 is an extended register and cannot be written to directly, please see the following FAQ for more information.

faq-extended-register-space-access-for-ethernet-phys

Regards,

Alvaro

Hi Alvaro (Al-vuh-roe) Reyes,

Thanks for the information.

I am accessing the phy register using the devmem2 tool.

I have one query: We have two ethernet ports, and ethernet's base address is 0x08000000. So how can I read/write both ethernet ports to register at the 0x0170 address?

Regards,

Abhishek

Hi Abhishek,

Thank you for confirming! Are you currently able to access the registers for both ports? Could you read Register 0x2 & 0x3 for both PHYs to confirm the devmem2 tool is working? The expected read is Reg 0x2 = 0x2000 & Reg 0x3 = 0xA231.

Each Ethernet PHY, one at each port, needs to have it's own unique PHY address. For example, ETH0 can be Address 0 and ETH1 can be address 10.

You would need to read/write to each PHY independently. The PHY Address is set by the hardware strap pins RX_D0 and RX_D2.

The MDC/MDIO pins are needed for register access, do both PHYs have this connection bused together to the SoC (i.e. ETH0 and ETH1 share a common MDC/MDIO trace to the SoC), or do they have their own independent traces to the SoC?

Regards,

Alvaro

Hi Alvaro,

As we have the base address of the ethernet is 0x08000000. So I am reading Register 0x2 & 0x3 as below. Is it the correct way?

if it is incorrect, can you provide how we can read registers for both phy independently?

root@ACM1000:~# devmem2 0x0800002 h
/dev/mem opened.
Memory mapped at address 0xffffb3a2d000.
Read at address  0x00800002 (0xffffb3a2d002): 0x0000
root@ACM1000:~# devmem2 0x0800003 h
/dev/mem opened.
Memory mapped at address 0xffff9ac93000.
Read at address  0x00800003 (0xffff9ac93002): 0x0000

Also, we have separate phy addresses, the phy1 address is 0, and the phy2 address is 1. Please check below snapshot.

also, Both ETH0 and ETH1 share a common MDC/MDIO trace to the SOC.

Alvaro (Al-vuh-roe) Reyes said:

The MDC/MDIO pins are needed for register access, do both PHYs have this connection bused together to the SoC (i.e. ETH0 and ETH1 share a common MDC/MDIO trace to the SoC), or do they have their own independent traces to the SoC?

Regards,

Abhishek