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TDA4VH-Q1: SerDes4 PLL Locking Issue with CPSW9G Native Linux Driver

Alex Fang
Prodigy 20 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH, AM69A

Tool/software:

Hi:

       I use TDA4VH SERDES4 to ptovide 4 lans SGMII signal for 4 Realtek RTL8211FS ethernet SGMII PHY chips. 

Now I can communicate with RTL8211FS PHY by MDIO. But the Link between main_cpsw0 and PHY

is not up. SEDES PLL sometimes can be locked, but not always. I use TI SDK "ti-processor-sdk-linux-am69-sk-10_00_07_06"

kernel. Could you help me to review my DTS file setting?

Thank you very much~

My dts setting:

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// SPDX-License-Identifier: GPL-2.0
/*
* DT Overlay for CPSW9G in SGMII mode using ROVY-M2-M-SGMII with ROVY-EVM board
*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
* Copyright 2024 Technexion Ltd.
*
* Author: Alex Fang <alex.fang@technexion.com>
*
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-cadence.h>
#include "k3-pinctrl.h"
&{/} {
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

SEDES PLL  Lock success:

SEDES PLL  Lock fail:

Best Regards

   Alex Fang

  • 0
    TI__Guru 52310 points

    Hi,

    Device tree configuration looks fine.

    One info, no need to mention "serdes4_sgmii_link" for all CPSW Ports, Once mention for Port-5 is sufficient.

    Can you please share the whole A72 Log in case of successful PLL lock and unsuccessful PLL lock scenario for review of flow.
    Also, make sure that no overlays added with same SerDes4 configuration.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 20 points

    Hi Sudheer:

        SEDES PLL isn't locked LOG:

         

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    ### BEGIN LOG - DATE: 241007, TIME: 180509 ###
    U-Boot SPL 2023.04-g84a5582c53-dirty (Aug 30 2024 - 01:07:55 -0700)
    EEPROM not available at 0x50, trying to read at 0x51
    Reading on-board EEPROM at 0x51 failed -1
    SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
    SPL initial stack usage: 13456 bytes
    Trying to boot from MMC2
    Loading Environment from nowhere... OK
    Starting ATF on ARM64 core...
    U-Boot SPL 2023.04-g84a5582c53-dirty (Aug 30 2024 - 01:07:39 -0700)
    SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
    Trying to boot from MMC2
    U-Boot 2023.04-g84a5582c53-dirty (Aug 30 2024 - 01:07:39 -0700)
    SoC: J784S4 SR1.0 GP
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

        SEDES PLL is locked LOG:

         

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    ### BEGIN LOG - DATE: 241007, TIME: 180945 ###
    U-Boot SPL 2023.04-g84a5582c53-dirty (Aug 30 2024 - 01:07:55 -0700)
    EEPROM not available at 0x50, trying to read at 0x51
    Reading on-board EEPROM at 0x51 failed -1
    SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
    SPL initial stack usage: 13456 bytes
    Trying to boot from MMC2
    Loading Environment from nowhere... OK
    Starting ATF on ARM64 core...
    U-Boot SPL 2023.04-g84a5582c53-dirty (Aug 30 2024 - 01:07:39 -0700)
    SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
    Trying to boot from MMC2
    U-Boot 2023.04-g84a5582c53-dirty (Aug 30 2024 - 01:07:39 -0700)
    SoC: J784S4 SR1.0 GP
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Thank you!

    Best Regards

        Alex Fang

  • 0 in reply to Alex Fang
    TI__Guru 52310 points

    Hi,

    From logs it seems like In non PLL locking case, Port Auto-negotiation is not enabled.

    Can you please check PHY configuration under MDIO node.

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    &main_cpsw0_mdio {
    status = "okay";
    bus_freq = <1000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    main_cpsw0_phy0: ethernet-phy@4 {
    reg = <4>;
    reset-gpios = <&pca9554_sgmii 0 GPIO_ACTIVE_LOW>;
    reset-assert-us = <35000>;
    reset-deassert-us = <75000>;
    rtl821x,aldps-disable;
    rtl821x,clkout-disable;
    realtek,phy-mode-eee-disable;
    };
    main_cpsw0_phy1: ethernet-phy@5 {
    reg = <5>;
    reset-gpios = <&pca9554_sgmii 1 GPIO_ACTIVE_LOW>;
    reset-assert-us = <35000>;
    reset-deassert-us = <75000>;
    rtl821x,aldps-disable;
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX


    Doredla Sudheer Kumar said:
    One info, no need to mention "serdes4_sgmii_link" for all CPSW Ports, Once mention for Port-5 is sufficient.

    Also, can you please check by removing the "serdes4_sgmii_link" from all ports and have it from Port-5 alone.

    Along with above, can you please dump Port-5, Port-6, Port-8 register information as well.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 20 points

    Hi Sudheer:

            I tried to remove ""serdes4_sgmii_link" " from "main_cpsw0_port6~8". It still can't LINK UP.

    Port-5 register:

    Port-6 register:

    Port-7 register:

    Port-8 register:

  • 0 in reply to Alex Fang
    Prodigy 20 points

    Sometimes Port7 PLL successfully Locked

    Port 5:

    Port 6:

    Port 7:

    Port 8:

  • 0 in reply to Alex Fang
    TI__Guru 52310 points

    Hi,

    Can you add print in Driver (in "am65_cpsw_nuss_mac_config" API from "am65-cpsw-nuss.c" file) and check whether SGMII registers are updating or not? 

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 20 points

    Hi Sudheer:

           I tried to dump the registers(

    AM65_CPSW_SGMII_MR_ADV_ABILITY_REG/
    AM65_CPSW_SGMII_CONTROL_REG) in  
    am65_cpsw_nuss_mac_config API. The value is the same with the "j7_devmem2_cpsw9g_check_status.sh" script.

    Do I need to check the SEDES PLL to  figure out why it can't be locked? 

    Best Regards

      Alex Fang

  • 0 in reply to Alex Fang
    TI__Guru 52310 points

    Hi,

    How you are printing the values?

    Have you used readl after write to confirm, write is success or not? It should be set for Advertise (MR_ADV should set with bit 1) and SGMII_CONTROL also bit0 should set.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 20 points

    Hi Doredla:

           Yes, I use readl to read the value of register before writing MR_ADV and SGMII_CONTROL and read it again after  writing MR_ADV and SGMII_CONTROL.

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    static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode,
    const struct phylink_link_state *state)
    {
    u32 reg_tmp,reg_tmp1;
    struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
    phylink_config);
    struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
    struct am65_cpsw_common *common = port->common;
    printk("Alex:am65_cpsw_nuss_mac_config extra_modes=%llu interface=%u\n",common->pdata.extra_modes,state->interface);
    if (common->pdata.extra_modes & BIT(state->interface)) {
    if (state->interface == PHY_INTERFACE_MODE_SGMII) {
    reg_tmp=readl(port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG);
    printk("Alex:PHY_INTERFACE_MODE_SGMII[Origin]:AM65_CPSW_SGMII_MR_ADV_ABILITY_REG address=0x%x value=%lu\n",port->sgmii_base+AM65_CPSW_SGMII_MR_ADV_ABILITY_REG,reg_tmp);
    writel(ADVERTISE_SGMII,
    port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG);
    reg_tmp=readl(port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG);
    printk("Alex:PHY_INTERFACE_MODE_SGMII[Current]:AM65_CPSW_SGMII_MR_ADV_ABILITY_REG address=0x%x value=%lu\n",port->sgmii_base+AM65_CPSW_SGMII_MR_ADV_ABILITY_REG,reg_tmp);
    cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN);
    } else {
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    I notice  eth3 sometimes can  successfully enable  MR_ADV and SGMII_CONTROL and others(eth1/2/4) are failed.

    When eth3 successfully enables  MR_ADV and SGMII_CONTROL, the LINK  is still not up but SERDES PLL is locked and

    AUTO negotiation is completed.

    Best Regards

      Alex Fang

  • 0 in reply to Alex Fang
    TI__Guru 52310 points

    Hi Alex,

    Alex Fang said:
    I notice  eth3 sometimes can  successfully enable  MR_ADV and SGMII_CONTROL and others(eth1/2/4) are failed.

    It should be success for all other configured ports.

    Also, Make sure that PHY is configured in SGMII Master Mode, default MAC is configured in Slave Mode.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 20 points

    Hi Sudheer:

        Do I have any way to check the mode status of  my MAC? Thank you~

    Best Regards

      Alex Fang

  • 0 in reply to Alex Fang
    TI__Guru 52310 points

    Hi,

    Alex Fang said:
    Do I have any way to check the mode status of  my MAC? Thank you~

    SGMII control register has bit filed for Master Mode, If that is "0" then MAC is configured in slave mode, and if it was set then MAC is in Master Mode.


    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 20 points

    Hi Sudheer:

        Where I can find the completed information? I can't find it in TI SDK package.

    Thank you~

    Best Regards

       Alex Fang

  • 0 in reply to Alex Fang
    TI__Guru 52310 points

    Hi Alex,

    Alex Fang said:
    Where I can find the completed information? I can't find it in TI SDK package.

    Register Spec is available in TRM not in SDK Documentation page.
    https://www.ti.com/lit/zip/spruj52

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 20 points

    Hi Sudheer:

         I check "SPRUJ52 - J84S4 AM69A TRM.pdf", but the Table 12-2174 you posted is not in the document?

    Best Regards

       Alex Fang

  • 0 in reply to Alex Fang
    TI__Guru 52310 points

    Hi,

    Alex Fang said:
         I check "SPRUJ52 - J84S4 AM69A TRM.pdf", but the Table 12-2174 you posted is not in the document?

    Register spec is from Excel file not PDF. From Excel file please go to cpsw9g sheet and check for SGMII Control and status registers.

    What I have posted is from different SoC's, bit fields and address was same as TDA4VH.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 20 points

    Hi Sudheer:

         Could you provide the document for me? Thank you~

    Best Regards

        Alex Fang

  • 0 in reply to Alex Fang
    TI__Guru 52310 points

    Hi Alex,

    Alex Fang said:
    Could you provide the document for me? Thank you~

    What ever the document capture I have shared in NDA document. Can't be shared.
    You can refer to Excel file present in TRM Link downloaded Zip fille. Excel file has the register information.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 20 points

    Hi Sudheer:

           I tried to check the SGMII signal from SERDES4. There is no signal on the pin.

    Have you ever enabled SGMII on SERDES4 of TDA4VH?

    Best Regards

       Alex Fang

  • 0 in reply to Alex Fang
    TI__Guru 52310 points

    Hi,

    Alex Fang said:

         I tried to check the SGMII signal from SERDES4. There is no signal on the pin.

    Have you ever enabled SGMII on SERDES4 of TDA4VH?

    We don't have Hardware with the provision of using SerDes4.
    TI EVM has only provision for SerDes2. so, default TI SDK also supports SerDes2 connected Ports configuration (Port-1/Port-7 or Port-2/Port-8).

    But, many customers are enabled SerDes4 and verified on custom boards.

    Best Regards,
    Sudheer