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Original question:

AM6442: IBIS setting for eMMC simulation

AM6442: MMC0- eMMC interface timing in HS200

Thierry HAUSER
Intellectual 400 points
Part Number: AM6442

Tool/software:

Hello,

I would like to simulate HS200 mode in write phase.

Table 6-68 of the TRM show OTAPDLYSEL is settled to 0x7 that : 

What is the corresponding delay value between CLK and others signals?

Thanks for you help.

  • 0
    TI__Guru 69061 points

    The query has been assigned to the expert. Please expect a response within a day or two.

    Thanks!

  • 0 in reply to Prashant Shivhare
    TI__Guru 62855 points

    They are defined in the data sheet table titled "MMC0 Switching Characteristics – HS200 Mode". The conditions for which these values are valid are defined in the datasheet table titled "MMC0 Timing Conditions".

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 400 points

    Hello Peaves,

    Thanks for your reply.
    I've understood, that HS2008 & HS2009 swithching characteristics may vary from 0.99ns to 3.28ns according to OTAPDLYSEL[15..12] values.
    The value of 0x7 correspond to which timing value?

    Thanks

  • 0 in reply to Thierry HAUSER
    TI__Guru 62855 points

    The OTAPDLYSEL value of 0x7 has a delay variation that can range from 0.99ns to 3.28ns, where this delay range represents what can be expected across process, voltage, and temperature variations of the device. We do not define delay range for any other value of OTAPDLYSEL since this configuration should provide appropriate setup and hold time to the attached device as long as you meet the PCB trace length requirements defined in the Timing Conditions table.

    Regards,
    Paul