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TDA4VM-Q1: TDA4VM Rtos 0806: How to config SGMII and eth port?

Part Number: TDA4VM-Q1
Other Parts Discussed in Thread: TDA4VM

Tool/software:

Hi,
TDA4VM RTOS 0806
now, my design is 

 I used prebuild sd card. 
 
How do I modify the code on the RTOS and Linux side
so that I can generate the corresponding ethn on the Linux side?

thanks.
dongzhang

  • Hi,

    By default SerDes0 is enabled for Multi-link in PCIe + QSGMII from U-boot.

    If you want to use SGMII2 in SGMII mode, need to configure the SerDes from u-boot.
    Default SGMII not supported from SerDes driver, need patches to SerDes Driver and device tree to be updated as SGMII.

    Please refer to patches for SerDes Driver + Device tree changes from below E2E.
    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1424970/tda4vm-q1-serdes0-4-configured-as-sgmii-interface-in-linux-native-driver-mode

    If you are not using PCIe, then you can enable SerDes0 from ETHFW and configure in SGMII Mode.

    As mentioned above ETHFW defaults configures Port-2 as QSGMII from TI SDK, you need to update as SGMII and invoke SerDes configuration of SGMII(Board_serdesCfgSgmii) instead of QSGMII (Board_serdesCfgQsgmii).
    Aslo, you need to take care of Board specific changes from Application (ethfw server main.c) for enabling of ports required, and need to update board evm file ("ethfw\utils\board\src\j721e\board_j721e_evm.c") for port configuration.

    Also, refer to below ETHFW porting guide for porting to custom board.
    https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/ethfw/docs/user_guide/ethfw_c_porting_top.html

    Best Regards,
    Sudheer

  • thanks,
    We use tda4vm serdes0 Lane 1 and serdes1 Lane1 as sgmii interface communicate other device.
    I used the patch provided at the address above. but failed, can't ping succ...

    Device tree modified below, please help me check if there is any problem with my modification?

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    &serdes_ln_ctrl {
    idle-states=<J721E_SERDES0_LANE0_PCIE0_LANE0>,<J721E_SERDES0_LANE1_QSGMII_LANE2>, //use serdes0 Lan1
    <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_SGMII_LANE1>, //use serdes1 Lan1
    <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
    <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
    <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
    <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
    };
    &serdes0 {
    serdes0_sgmii_link: phy@1 {
    reg = <1>;
    cdns,num-lanes = <1>;
    #phy-cells = <0>;
    cdns,phy-type = <PHY_TYPE_SGMII>;
    resets = <&serdes_wiz0 2>;
    };
    };
    &serdes1 {
    serdes1_sgmii_link: phy@1 {
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • Hi,

    Can you please share Linux terminal Log?

    Also, can you please confirm that patches in below are taken or not?
    SGMII-Patches.zip

    Also, can you please confirm SerDes configuration is disabled from u-boot.
    Please ensure that the following configs are disabled, and SerDes node is disabled form device tree.

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    CONFIG_PHY_CADENCE_SIERRA=n
    CONFIG_PHY_J721E_WIZ=n
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Above is to ensure that U-Boot is not configuring the SerDes.


    Best Regards,
    Sudheer

  • 1. I had taken the patch SGMII-Patches.zip and 3542.0001-phy-cadence-Sierra-Add-Single-link-SGMII-PHY-configu.patch
     SGMII-Patches (1).zip
    2. uboot not configuring the SerDes.
    CONFIG_PHY_CADENCE_SIERRA=n
    CONFIG_PHY_J721E_WIZ=n

    3.  Linux terminal Log below
    log:74382.log.txt

  • Hi,

    Let us check the logs and update you soon.

    Best Regards,
    Sudheer

  • hi,
    Another question, is it true that in this version 0806 network, only in Linux mode, modifying SGMII does not require modifying the RTOS code?
    thanks

  • root@j7-evm:~# devmem2 0x500e000
    /dev/mem opened.
    Memory mapped at address 0xffffa9660000.
    Read at address 0x0500E000 (0xffffa9660000): 0x00003010
    root@j7-evm:~# devmem2 0x5000408
    /dev/mem opened.
    Memory mapped at address 0xffff97ff3000.
    Read at address 0x05000408 (0xffff97ff3408): 0x9A000000
    root@j7-evm:~# devmem2 0x500040C
    /dev/mem opened.
    Memory mapped at address 0xffff89105000.
    Read at address 0x0500040C (0xffff8910540c): 0x92000000
    root@j7-evm:~# devmem2 0x50004C0
    /dev/mem opened.
    Memory mapped at address 0xffffa8000000.
    Read at address 0x050004C0 (0xffffa80004c0): 0x70800000
    root@j7-evm:~# devmem2 0x50004C4
    /dev/mem opened.
    Memory mapped at address 0xffff8ef35000.
    Read at address 0x050004C4 (0xffff8ef354c4): 0x00010002
    root@j7-evm:~# devmem2 0x50004C8
    /dev/mem opened.
    Memory mapped at address 0xffffb46a8000.
    Read at address 0x050004C8 (0xffffb46a84c8): 0x00000000
    root@j7-evm:~# devmem2 0x50004CC
    /dev/mem opened.
    Memory mapped at address 0xffff97f22000.
    Read at address 0x050004CC (0xffff97f224cc): 0x00000002
    root@j7-evm:~# devmem2 0xc000204
    /dev/mem opened.
    Memory mapped at address 0xffff92c70000.
    Read at address 0x0C000204 (0xffff92c70204): 0x00000000
    root@j7-evm:~# devmem2 0xc000210
    /dev/mem opened.
    Memory mapped at address 0xffffb76fb000.
    Read at address 0x0C000210 (0xffffb76fb210): 0x00000021
    root@j7-evm:~# devmem2 0xc000210
    /dev/mem opened.
    Memory mapped at address 0xffff9ccb8000.
    Read at address 0x0C000210 (0xffff9ccb8210): 0x00000021
    root@j7-evm:~# devmem2 0xc000214
    /dev/mem opened.
    Memory mapped at address 0xffffad0c9000.
    Read at address 0x0C000214 (0xffffad0c9214): 0x00000038
    root@j7-evm:~# devmem2 0xc000218
    /dev/mem opened.
    Memory mapped at address 0xffffa674d000.
    Read at address 0x0C000218 (0xffffa674d218): 0x00009801

  • HI, 

    Another question, is it true that in this version 0806 network, only in Linux mode, modifying SGMII does not require modifying the RTOS code?

    When you are using Native Linux driver make sure that RTOS ETHFW should not be loaded on MCU2_0.

    Both RTOS & Linux driver can't access CPSW at the same time. 

    Best Regards, 

    Sudheer

  • Hi,
    Got it thanks
    We had mv  vx_app_rtos_linux_mcu2_0.out vx_app_rtos_linux_mcu2_0.out.bak
    and the log and register  is right or not?
    thanks

    dongzhang

  • HI, 

    Memory mapped at address 0xffffad0c9000.
    Read at address 0x0C000214 (0xffffad0c9214): 0x00000038

    It seems link is not up. 

    The serdes register address was wrong above you are reading. But, from sgmii status register pll is locked it seems. 

    mv  vx_app_rtos_linux_mcu2_0.out vx_app_rtos_linux_mcu2_0.out.bak

    You need to soft link ipc echo test binary to main_r5f0_0.

    Vx_app may have ethfw enabled while creating the vision image. 

    You can run below command and check remote core logs. 

    #cat sys/kernel/debug/remoteproc/remoteproc*/trace0

    Best Regards, 

    Sudheer

  • Hi, 

    It seems like, from logs no prints are available in mcu2_0.

    Can you check softlink of mcu2_0 binay as well. 

    #ls -l /lib/fimware

    Best Regards 

    Sudheer