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TDA4VM-Q1: serdes0/4 configured as SGMII interface in linux native driver mode

Part Number: TDA4VM-Q1

Tool/software:

Hi, ti exports

we are configured serdes0/4 as SGMII interface, and use cpsw9g in linux native driver mode, the Connection diagram as follows.

I modified DTS and RGMII4 is working now, but SGMII doesn't seem to be working,I have read many ticks on ti e2e,but still don't know how to solve the problem.

sdk version: ti-processor-sdk-linux-j7-evm-08_06_01_02

questions:

1、how to configuration SGMII in dts?

2、i saw some ticks mentioned that serdes0 is 2-Lane does not support single sgmii mode,so does we have a patch on sdk 8.6 about it(modify phy-cadence-sierra.c ?),and serdes4 also need to be modify?

3、we are used internal clock for serdes 0/4, does the clock configuration correct?

        Can you help me check the DTS content,and tell me what modifications should be do can make SGMII1/2/8 work, thanks.

some content in k3-j721e-main.dtsi

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cpsw0: ethernet@c000000 {
compatible = "ti,j721e-cpswxg-nuss";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x00 0xc000000 0x00 0x200000>;
reg-names = "cpsw_nuss";
ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
clocks = <&k3_clks 19 89>;
clock-names = "fck";
power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
dmas = <&main_udmap 0xca00>,
<&main_udmap 0xca01>,
<&main_udmap 0xca02>,
<&main_udmap 0xca03>,
<&main_udmap 0xca04>,
<&main_udmap 0xca05>,
<&main_udmap 0xca06>,
<&main_udmap 0xca07>,
<&main_udmap 0x4a00>;
dma-names = "tx0", "tx1", "tx2", "tx3",
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

some content in k3-j721e-common-proc-board.dts

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&serdes_ln_ctrl {
idle-states = <J721E_SERDES0_LANE0_QSGMII_LANE1>, <J721E_SERDES0_LANE1_QSGMII_LANE2>, /* port1, port2 */
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
<J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
<J721E_SERDES3_LANE0_IP1_UNUSED>, <J721E_SERDES3_LANE1_IP1_UNUSED>,
<J721E_SERDES4_LANE0_QSGMII_LANE5>, <J721E_SERDES4_LANE1_QSGMII_LANE6>,
<J721E_SERDES4_LANE2_QSGMII_LANE7>, <J721E_SERDES4_LANE3_QSGMII_LANE8>; /* port 8 */
};
&cpsw0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cpsw0_mdio_pins_default &cpsw0_rgmii_pins_default &cpsw0_phy_reset_pins_default>;
};
&cpsw9g_mdio {
cpsw9g_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id002b.0980", "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
reset-gpios = <&main_gpio0 96 GPIO_ACTIVE_LOW>;
reset-assert-us = <5000>;
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

ifconfig content:

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root@j7-evm:~# ifconfig
docker0: flags=4099<UP,BROADCAST,MULTICAST> mtu 1500 metric 1
inet 172.17.0.1 netmask 255.255.0.0 broadcast 172.17.255.255
ether 02:42:d8:c0:a6:ac txqueuelen 0 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 0 (0.0 B)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 metric 1
inet6 fe80::3608:e1ff:fe58:fb10 prefixlen 64 scopeid 0x20<link>
ether 34:08:e1:58:fb:10 txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 166 bytes 48364 (47.2 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
eth1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 metric 1
inet 192.168.2.21 netmask 255.255.255.0 broadcast 192.168.2.255
inet6 fe80::3068:69ff:feff:93f4 prefixlen 64 scopeid 0x20<link>
ether 32:68:69:ff:93:f4 txqueuelen 1000 (Ethernet)
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

ethtool eth1

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root@j7-evm:~# ethtool eth1
Settings for eth1:
Supported ports: [ ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
1000baseKX/Full
Supported pause frame use: Symmetric
Supports auto-negotiation: No
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
1000baseKX/Full
Advertised pause frame use: Symmetric
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: 1000Mb/s
Duplex: Full
Auto-negotiation: off
Port: Twisted Pair
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • Hi,
    SDK 8.6 needs changes to SerDes Driver for supporting SGMII along with am65-cpsw-nuss driver, and "phy-gmii-sel.c".

    We have tested SGMII link on Sierra 2L SerDes0.

    Please refer to below info for enabling SGMII on Sierra 2L SerDes.

    1. Update the SGMII support from Sierra SerDes & CPSW Driver and other.

    SGMII-Patches.zip

    2. U-Boot is configuring the SerDes in PCIe + QSGMII configuration.
    Due to this, since the SerDes has already been configured in U-Boot, the Linux SerDes driver will not configure the SerDes for the desired SGMII mode.

    When building U-Boot (u-boot.img), please ensure that the following configs are disabled:

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    CONFIG_PHY_CADENCE_SIERRA=n
    CONFIG_PHY_J721E_WIZ=n
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Above is to ensure that U-Boot is not configuring the SerDes.

    3. Additionally, with the SDK, the Sierra driver which configures the SerDes supports "PCIe + SGMII" multilink configuration only. Therefore, with the default SDK, please modify the existing SerDes node to below.

    a) for SGMII + PCIe:

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    &serdes0 {
    serdes0_sgmii_link: phy@0 {
    reg = <0>;
    cdns,num-lanes = <1>;
    #phy-cells = <0>;
    cdns,phy-type = <PHY_TYPE_SGMII>;
    resets = <&serdes_wiz0 1>; /* , <&serdes_wiz0 2>; */
    };
    serdes0_pcie_link: phy@1 {
    reg = <1>;
    cdns,num-lanes = <1>;
    #phy-cells = <0>;
    cdns,phy-type = <PHY_TYPE_PCIE>;
    resets = <&serdes_wiz0 2>;
    };
    };
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX


    NOTE: While the above device-tree node change requests Serdes to be configured in PCIe + SGMII configuration, it is not necessary to enable the PCIe instance for the SerDes to be configured.

    b) for 2 SGMII Ports:

    The serdes0 device-tree node has to be modified to:

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    &serdes0 {
    serdes0_sgmii_link: phy@0 {
    reg = <0>;
    cdns,num-lanes = <2>;
    #phy-cells = <0>;
    cdns,phy-type = <PHY_TYPE_SGMII>;
    resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
    };
    };
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Also, the serdes_ln_ctrl device-tree node has to be modified to:

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    &serdes_ln_ctrl {
    idle-states = <J721E_SERDES0_LANE0_QSGMII_LANE1>, <J721E_SERDES0_LANE1_QSGMII_LANE2>, /*<J721E_SERDES0_LANE1_QSGMII_LANE2>, */
    <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
    <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
    <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
    <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
    <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
    };
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    And finally, the cpsw device-tree nodes have to be modified to:

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    &cpsw0_port1 {
    phy-handle = <&debug_phy>;
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 1>, <&serdes0_sgmii_link>;
    phy-names = "portmode", "serdes-phy";
    };
    &cpsw0_port2 {
    phy-handle = <&anc_phy>;
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 2>;
    phy-names = "portmode";
    };
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    In above only CPSW Port 1's device-tree node points to the SerDes and requests both lanes of the SerDes to be configured in SGMII mode, on behalf of CPSW Port 2 as well.


    For SerDes4, take care of below as well. SerDes4 bu default support SGMII configuration.

    You need to change the compatible name and parent-clock for SerDes4 as below from "k3-j721e-main.dtsi" file.

    1. Make the compatible string forserdes_wiz4 node as : "ti,j721e-wiz-10g"
    2. Make the compatible string for serdes as : "ti,j721e-serdes-10g"
    3. Change assigned clock parent as "assigned-clock-parents = <&k3_clks 297 13>;"
    4. Comment out "assigned-clock-rates = <19200000>;" from "serdes_wiz4" node.

    Please refer to above and update the device tree and Driver files for SGMII enable.

    Best Regards,
    Sudheer

  • Hi,Sudheer

    "3. Additionally, with the SDK, the Sierra driver which configures the SerDes supports "PCIe + SGMII" multilink configuration only."

    what's the meaning, serdes0 cannot configure as "sgmii+sgmii" mode?

    I have modified the drivers according to the patch you gave, use "b) for 2 SGMII Ports:" configuration.

    and there are some different, the tx_good_frames are increated(Before this it was always 0)

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    root@j7-evm:~# ethtool -S eth1 | grep good
    p0_rx_good_frames: 348
    p0_tx_good_frames: 0
    rx_good_frames: 0
    tx_good_frames: 296
    root@j7-evm:~# ethtool -S eth1 | grep good
    p0_rx_good_frames: 349
    p0_tx_good_frames: 0
    rx_good_frames: 0
    tx_good_frames: 297
    root@j7-evm:~# ethtool -S eth1 | grep good
    p0_rx_good_frames: 350
    p0_tx_good_frames: 0
    rx_good_frames: 0
    tx_good_frames: 298
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    some regs values:

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    CPSW_SS_STATUS_SGMII_LINK_REG (0x0c000078) = 0x00000000
    CPSW_SGMII_CONTROL_REG_1 (0x0c000110) = 0x00000001
    CPSW_SGMII_STATUS_REG_1 (0x0c000114) = 0x0000003C
    SERDES0_CTRL (0x05000404) = 0x00000000
    SERDES0_TOP_CTRL (0x05000408) = 0x9A000000
    SERDES0_RST (0x0500040C) = 0xB1000000
    SERDES0_LANECTL0 (0x05000480) = 0x70800000
    SERDES0_LANEDIV0 (0x05000484) = 0x00010002
    SERDES0_LANEALIGN0 (0x05000488) = 0x00000000
    SERDES0_LANESTS0 (0x0500048C) = 0x00000003
    SERDES0_LANECTL1 (0x050004C0) = 0x70800000
    SERDES0_LANEDIV1 (0x050004C4) = 0x00010002
    SERDES0_LANEALIGN1 (0x050004C8) = 0x00000000
    SERDES0_LANESTS1 (0x050004CC) = 0x00000003
    SERDES0_PHY_PMA_CMN_CTRL (0x0500E000) = 0x00002435
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • Hi,add further progress

    sgmii1/sgmii2 on serdes0 are not available, sgmii8 on serdes4 is ok, it can ping outside, but some packets are lost,the ping information is as follows:

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    root@j7-evm:~# ping 192.168.2.80
    PING 192.168.2.80 (192.168.2.80): 56 data bytes
    64 bytes from 192.168.2.80: seq=1 ttl=128 time=0.447 ms
    64 bytes from 192.168.2.80: seq=2 ttl=128 time=0.514 ms
    64 bytes from 192.168.2.80: seq=3 ttl=128 time=0.405 ms
    64 bytes from 192.168.2.80: seq=4 ttl=128 time=0.369 ms
    64 bytes from 192.168.2.80: seq=5 ttl=128 time=0.386 ms
    64 bytes from 192.168.2.80: seq=6 ttl=128 time=0.469 ms
    64 bytes from 192.168.2.80: seq=7 ttl=128 time=0.445 ms
    64 bytes from 192.168.2.80: seq=8 ttl=128 time=0.379 ms
    64 bytes from 192.168.2.80: seq=9 ttl=128 time=0.446 ms
    64 bytes from 192.168.2.80: seq=10 ttl=128 time=0.332 ms
    64 bytes from 192.168.2.80: seq=11 ttl=128 time=0.389 ms
    64 bytes from 192.168.2.80: seq=12 ttl=128 time=0.399 ms
    64 bytes from 192.168.2.80: seq=13 ttl=128 time=0.470 ms
    64 bytes from 192.168.2.80: seq=14 ttl=128 time=0.370 ms
    ^C
    --- 192.168.2.80 ping statistics ---
    15 packets transmitted, 14 packets received, 6% packet loss
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

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    ping -n 30 192.168.2.23
    Ping 192.168.2.23 32 :
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    192.168.2.23 : =32 <1ms TTL=64
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    so is there anything else that needs to be modified here?

    for sgmii1/sgmii2 on serdes0, also anything else that needs to be modified?

  • Additionally,when i configured serdes0 as "SGMII + PCIe" mode(sgmii1- s0l0,pcie-s0l1),the sgmii1 working fine.

  • at the same time, sgmii8(serdes4) can not use iperf3 for test,sgmii1(serdes0) can when configured as "SGMII + PCIe" mode.

  • Hi,

    Can you please check is SerDes0 enabled at u-boot in your side, If so Linux will not configure the SerDes.

    Please disable SerDes from u-boot and check once.

    Best Regards,
    Sudheer

  • yes,i have already disable it

  • Hi,

    When you configured both lanes for SGMII, have you observing any error from Linux?

    Also, can you please confirm, changes in below patch are added to phy-cadence-sierra.c file.
    3542.0001-phy-cadence-Sierra-Add-Single-link-SGMII-PHY-configu.patch


    Best Regards,
    Sudheer

  • i don't find any error info. in boot log

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    U-Boot SPL 2021.01 (Oct 16 2024 - 17:25:48 +0800)
    Model: Texas Instruments K3 J721E SoC
    SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.3--v08.06.03 (Chill Capybar')
    Trying to boot from MMC2
    Starting ATF on ARM64 core...
    NOTICE: BL31: v2.8(release):v2.8-226-g2fcd408bb3-dirty
    NOTICE: BL31: Built : 15:40:55, May 2 2023
    I/TC:
    I/TC: OP-TEE version: 3.20.0 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Tue May 2 15:41:00 U
    TC 2023 aarch64
    I/TC: WARNING: This OP-TEE configuration might be insecure!
    I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
    I/TC: Primary CPU initializing
    I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.3--v08.06.03 (Chill Capybar')
    I/TC: HUK Initialized
    I/TC: Activated SA2UL device
    I/TC: Fixing SA2UL firewall owner for GP device
    I/TC: Enabled firewalls for SA2UL TRNG device
    I/TC: SA2UL TRNG initialized
    I/TC: SA2UL Drivers initialized
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • This is new patch?Should I  make changes based on the original or the modified version? does this patch suitable for 1000M network? we don't use 100M.

  • Hi,

    This is new patch?Should I  make changes based on the original or the modified version? does this patch suitable for 1000M network? we don't use 100M.

    I hope, it was part of above Zip files shared.

    Can you please check changes present in phy-cadence-sierra.c file or not?

    oes this patch suitable for 1000M network? we don't use 100M.

    It is not for Link speed, SerDes clock frequency of 100MHz.

    Best Regards,
    Sudheer

  • Hi,Sudheer,

    Thanks very much, the serdes0 sgmii1/sgmii2 both ok, the patch you gave me twice are different,the second one is ok.

    So another issue still needs your help, the sgmii8 on serdes4 can ping each other with external computer,but i can't use iperf3 to test the network,also i can't transmit files use scp command.

    test case:

    server(computer): iperf3 -s

    client(tda4): iperf3 -c 192.168.2.80

    There is no output on client side.

    i use wireshark to capture packages on server side,there are some prompts as follows:

  • Hi, 

    Thanks very much, the serdes0 sgmii1/sgmii2 both ok, the patch you gave me twice are different,the second one is ok

    Thanks for the update. 

    server(computer): iperf3 -s

    client(tda4): iperf3 -c 192.168.2.80

    There is no output on client side

    There is nothing related to this in driver. 

    Can you please use iperf and check once. Also make sure that port used will be open or not in client machine. 

    You can specify port number like 9000 using -p 9000.

    Best Regards, 

    Sudheer

  • Hi,

    I specified the test port to "-p 9000" and the result was the same.

    I think may be some different with the driver(like phy-cadence-sierra.c and phy-cadence-torrent.c ?), because i do the same test on sgmii1/sgmii2(serdes0), the test result are all passed,only sgmii8(serdes4) not ok.

  • Hi,Sudheer,

    I use this patch solved this issue, but i don't know why. Could you please check if this patch is safe?

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    From 0badc8f20da335c699895cb92353e10f9f6dc109 Mon Sep 17 00:00:00 2001
    From: Tanmay Patil <t-patil@ti.com>
    Date: Mon, 24 Apr 2023 14:28:24 +0530
    Subject: [PATCH] net: ethernet: ti: cpsw_ale: Fix ale field set and get
    CPSW ALE has 75 bit ALE entries which is are stored in 3
    32 bit words. With Read/Write using cpsw_ale_get_field()/
    cpsw_ale_set_field(), the function assumes that the field
    will be strictly contained within one word. This is not
    the case and ALE field entries can span upto two words.
    This commit adds the support for reading/writing ALE
    fields which span two words.
    Signed-off-by: Tanmay Patil <t-patil@ti.com>
    ---
    drivers/net/ethernet/ti/cpsw_ale.c | 22 +++++++++++++++++-----
    1 file changed, 17 insertions(+), 5 deletions(-)
    diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c
    index 6d60373d15e0..dc8d6f8e7dda 100644
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • Hi,

    I use this patch solved this issue, but i don't know why. Could you please check if this patch is safe?

    This is valid change needed in drivers while enabling 8th port.

    If above patch is not there Port-8 may not be part of VLAN mask, by default VLAN-0 enabled in Linux Ethernet Driver.
    May be you can observe packets Drop at Port-8 statistics due to ALE.

    Best Regards,
    Sudheer