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Tool/software:
Dear Sir/ Madam,
I am using DRA821U as a gateway controller in my design, and I have below questions need your confirmation.
1. For SerDes0 and CPSW5G, can below configurations be run at the same time? I have this question because there is notes on DRA821 TRM Page 37 saying that A maximum of two of the three IP can be used concurrently. But, by using TI PinMux tool SysConfig, there is no warning or error messages shown when below configurations were made.
SerDes0 Lane0 - PCIe Lane0 (PCIe x1 Lane Mode)
SerDes0 Lane1 - SGMII Lane4 (CPSW5 Port 4, SGMII Interface)
SerDes0 Lane2 - SGMII Lane1 (CPSW5 Port 1, SGMII Interface)
SerDes0 Lane3 - USB3 (USB3.0)
RGMII2 (CPSW5 Port 2, RGMII Interface)
RGMII3 (CPSW5 Port 3, RGMII Interface)
2. For SerDes0 USB Application, TRM Page 958, 5.1.3.4.27, Table 5-749, SERDES_SEL Register bit says USB3.0 interface can be 2 different SERDES0 lanes, options are Ln1 and Ln3, but in SysConfig, Ln0 and Ln2 can also be selected without any warning or error messages. Please make clarifications.
3. For SerDes0 Lane0 used as PCIe, can it support PCIe 1.1?
Hi,
SerDes0 Lane0 - PCIe Lane0 (PCIe x1 Lane Mode)
SerDes0 Lane1 - SGMII Lane4 (CPSW5 Port 4, SGMII Interface)
SerDes0 Lane2 - SGMII Lane1 (CPSW5 Port 1, SGMII Interface)
SerDes0 Lane3 - USB3 (USB3.0)
This configuration cannot be used. This is a limitation imposed by serdes IP and does not come from the pinmux clashes. The pins are configurable according to what you mentioned, but we cannot configure the individual serdes lanes in the same way.
Basically, you can configure a serdes instance for only two protocols and bit-rates. If you go with devices which have more than 1 serdes instance, then you can do this using multiple serdes.
For SerDes0 USB Application, TRM Page 958, 5.1.3.4.27, Table 5-749, SERDES_SEL Register bit says USB3.0 interface can be 2 different SERDES0 lanes, options are Ln1 and Ln3, but in SysConfig, Ln0 and Ln2 can also be selected without any warning or error messages. Please make clarifications.
Lane 1 and lane 3 are used for normal USB operations where-as lane 0 and lane 2 can be used for USB type-C application. See section "12.2.5.3.1.1 Interface Selection" in the TRM
For SerDes0 Lane0 used as PCIe, can it support PCIe 1.1?
In general, PCIe 3.0 is backwords compatible with PCIe 1.1. So you should not have an issue with PCIe 1.1 device.
Regards,
Tanmay
Dear,
thanks for your response.
would you please check if below configruations are achievable? We would like to use four ports Ethernet (2 SGMII + 2 RGMII) and USB (Type C Application).
SerDes0 Lane0 - SGMII Lane3 (CPSW5 Port 3, SGMII Interface)
SerDes0 Lane1 - SGMII Lane4 (CPSW5 Port 4, SGMII Interface)
SerDes0 Lane2 - USB Type C TX/RX 1
SerDes0 Lane3 - USB Type C TX/RX 2
RGMII1 (CPSW5 Port 1, RGMII Interface)
RGMII2 (CPSW5 Port 2, RGMII Interface)
thanks.
Hi,
From ethernet perspective, these are okay.
I think this is not possible to have 2 USB-C connections like that. Let me forward the thread to USB expert to comment on this.
Regards,
Tanmay
Hi
SerDes0 Lane2 - USB Type C TX/RX 1
SerDes0 Lane3 - USB Type C TX/RX 2
The SERDES can only support one USB interface. Lane 2 is intended to be used in combination with Lane 3 for a USB Type-C lane-swap function.
Regards
Diwakar
Dear,
Yes, I would like to use two SerDes lane for Type C lane swap feature.
thanks for your explanation.
Hi
Do let us know if you have any further question or else we can close this thread.
Regards
Diwakar