J784S4XEVM: stuck while starting debug

Hi,

Burak Burak said:

Additionally, we were also unable to boot from SD card as well, but we could work in no boot mode and we' re able to connect to C7x cores. After some time, we also started having problems in no boot mode.

Could you please tell me if you are using a custom board or TI EVM? 

Regards,

Karthik

Hi Karthik,

It is TI EVM.

Hi Burak,

Burak Burak said:

Console writes below:

Would you kindly provide the entire console log?

Burak Burak said:

I think we are stuck at that line in launch.js

Could you please share the launch.js file with me?

Regards,

Karthik

Hi,

Sorry for the late response. I use the original launch.js file, there is no modification except the PDK path as indicated in the comments of the script. SDK version is 09.01.00.06. You may reach it from sdkpath.pdk_j784s4_09_01_00_22.packages.ti.drv.sciclient.tools.ccsLoadDmsc.j784s4.launch.js.

The full console logs are below.

CORTEX_M4F_0: GEL Output: Configuring ATCM for the R5Fs
CORTEX_M4F_0: GEL Output: ATCM Configured.
CORTEX_M4F_0: GEL Output: This GEL is currently only supported for use from the Cortex-M4 inside the TIFS.
CORTEX_M4F_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
CORTEX_M4F_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
CORTEX_M4F_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000].
CORTEX_M4F_0: GEL Output: This is consistent with the SoC DV assumptions.
CORTEX_M4F_0: GEL Output: R5F Halt bits set.
CORTEX_M4F_0: GEL Output: C71X_x DSPs configured for Wait In Reset Mode
CORTEX_M4F_0: GEL Output: Debugging disabled.
CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Checking LPSC_WKUPMCU2MAIN
CORTEX_M4F_0: GEL Output: Power Domain: On
CORTEX_M4F_0: GEL Output: Module State: Enable
CORTEX_M4F_0: GEL Output: Programming all PLLs.
CORTEX_M4F_0: GEL Output: Programming Main PLL 0 (Main PLL)
CORTEX_M4F_0: GEL Output: Main PLL 0 (Main PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 3 (CPSW5X PLL)
CORTEX_M4F_0: GEL Output: Main PLL 3 (CPSW5X PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 4 (Audio 0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 4 (Audio 0 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 5 (Video PLL)
CORTEX_M4F_0: GEL Output: Main PLL 5 (Video PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 6 (GPU PLL)
CORTEX_M4F_0: GEL Output: Main PLL 6 (GPU PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 7 (MSMC PLL)
CORTEX_M4F_0: GEL Output: Main PLL 7 (MSMC PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 9 (ARM1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 9 (ARM1 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL)
CORTEX_M4F_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 16 (DSS0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 16 (DSS0 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 17 (DSS1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 17 (DSS1 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 19 (DSS3 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 19 (DSS3 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 25 (Vision PLL)
CORTEX_M4F_0: GEL Output: Main PLL 25 (Vision PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 27 (DDR2 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 27 (DDR2 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming Main PLL 28 (DDR3 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 28 (DDR3 PLL) Set.
CORTEX_M4F_0: GEL Output: Programming MCU PLL 0 (MCU PLL)
CORTEX_M4F_0: GEL Output: MCU PLL 0 (MCU PLL) Set.
CORTEX_M4F_0: GEL Output: Programming MCU PLL 1 (MCU Peripheral PLL)
CORTEX_M4F_0: GEL Output: MCU PLL 1 (MCU PLL) Set.
CORTEX_M4F_0: GEL Output: Programming MCU PLL 2 (MCU CPSW PLL)
CORTEX_M4F_0: GEL Output: MCU PLL 2 (MCU PLL) Set.
CORTEX_M4F_0: GEL Output: All PLLs programmed.
CORTEX_M4F_0: GEL Output: Powering up all PSC power domains in progress...
CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUP_ALWAYSON
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DMSC
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DEBUG2DMSC
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUP_GPIO
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN2WKUPMCU
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_TEST
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_DEBUG
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_MCAN_0
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_MCAN_1
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_OSPI_0
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_OSPI_1
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_HYPERBUS
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_I3C_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_ADC_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_ADC_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUP_SPARE_0 (HSM)
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_R5_0
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_R5_1
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_PULSAR_PBIST_0
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_ALWAYSON
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_TEST
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_PBIST
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_AUDIO
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_ATL
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_MLB
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_MOTOR
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_MISCIO
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_GPMC
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_VPFE
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_VPE
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_SPARE_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_SPARE_1
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_DEBUG
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_CFG_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_DATA_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_CFG_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_DATA_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_CFG_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_DATA_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_SPARE_2
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CC_TOP_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MMC4B_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MMC4B_1
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MMC8B_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_SAUL
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_I3C
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_CFG_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_DATA_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MSMC_L1_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DRU_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_ANA_PBIST_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MSMC_L1_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DRU_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_ANA_PBIST_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MSMC_L1_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DRU_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_ANA_PBIST_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MSMC_L1_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DRU_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_ANA_PBIST_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_SERDES_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_SERDES_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_SERDES_4
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_SERDES_5
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_4
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_5
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_6
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_7
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_8
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_9
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_10
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_11
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_12
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_13
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DSS_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DSS
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_TX_DPHY_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DSI
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_EDP_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSITX_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_PHY_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_PHY_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_PHY_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_CSITX_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_TX_DPHY_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_9GSS
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PCIe_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PCIe_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PCIe_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PCIe_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_0
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_1
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_2
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_3
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powered up all Main Timers.
CORTEX_M4F_0: GEL Output: Powering up LPSC_USB_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_USB_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_USB_2
CORTEX_M4F_0: GEL Output: No change needed.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_0_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_1_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_2_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_3_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER_0_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER_1_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER0_CORE2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER0_CORE3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER1_CORE2
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER1_CORE3
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_GPUCOM
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_GPUPBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_GPUCORE
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_0_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_1_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_2_R5_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_2_R5_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_2_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_ENCODE_0
CORTEX_M4F_0: GEL Output: ERROR: module state NOT changed!
CORTEX_M4F_0: GEL Output: Powering up LPSC_ENCODE_PBIST
CORTEX_M4F_0: GEL Output: ERROR: module state NOT changed!
CORTEX_M4F_0: GEL Output: Powering up LPSC_ENCODE_1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_ENCODE_1_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DECODE_0
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DECODE_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DMPAC
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_SDE
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_DMPAC_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_VPAC
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_VPAC_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_VPAC1
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up LPSC_VPAC1_PBIST
CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully.
CORTEX_M4F_0: GEL Output: Powering up PD_SPARE4
CORTEX_M4F_0: GEL Output: ERROR: module state NOT changed!
CORTEX_M4F_0: GEL Output: Powering up PD_SPARE5
CORTEX_M4F_0: GEL Output: ERROR: module state NOT changed!
CORTEX_M4F_0: GEL Output: Powering up PD_SPARE6
CORTEX_M4F_0: GEL Output: ERROR: module state NOT changed!
CORTEX_M4F_0: GEL Output: Powering up all PSC power domains done!
CORTEX_M4F_0: GEL Output: MCU R5F Cluster set to split mode.
CORTEX_M4F_0: GEL Output: Main R5F Cluster 0 set to split mode.
CORTEX_M4F_0: GEL Output: Main R5F Cluster 1 set to split mode.
CORTEX_M4F_0: GEL Output: Main R5F Cluster 2 set to split mode.
CORTEX_M4F_0: GEL Output: --->>> ================================================== <<<---
CORTEX_M4F_0: GEL Output: --->>> Set DDR Interelave Configuration: <<<---
CORTEX_M4F_0: GEL Output: --->>> multi DDR config 0 : 0x0x000C0003 <<<---
CORTEX_M4F_0: GEL Output: --->>> multi DDR config 1 : 0x0x0000180F <<<---
CORTEX_M4F_0: GEL Output: --->>> Quad DDR enabled <<<---
CORTEX_M4F_0: GEL Output: --->>> 128B Granule Size <<<---
CORTEX_M4F_0: GEL Output: --->>> ================================================== <<<---
CORTEX_M4F_0: GEL Output: --->>> LPDDR4 Initialization is in progress ... <<<---
CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to 20MHz/19.2MHz on silicon (bypass)
CORTEX_M4F_0: GEL Output: Set DDR0 PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
CORTEX_M4F_0: GEL Output: --->>> DDR0 controller programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 controller programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 PI programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 PI programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 0 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 0 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 1 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 1 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 2 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 2 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 3 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 3 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Address slice 0 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Address Slice 0 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR PI initialization started... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR Controller initialization started... <<<---
CORTEX_M4F_0: GEL Output: --->>> Waiting for frequency change requests ... <<<---
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 0 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to 20MHz/19.2MHz on silicon (bypass)
CORTEX_M4F_0: GEL Output: Set DDR0 PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 0 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to 20MHz/19.2MHz on silicon (bypass)
CORTEX_M4F_0: GEL Output: Set DDR0 PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set.
CORTEX_M4F_0: GEL Output: --->>> All frequency change requests have completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> LPDDR4 Initialization is DONE! <<<---
CORTEX_M4F_0: GEL Output: --->>> LPDDR4 Initialization is in progress ... <<<---
CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to 20MHz/19.2MHz on silicon (bypass)
CORTEX_M4F_0: GEL Output: Set DDR1 PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
CORTEX_M4F_0: GEL Output: --->>> DDR1 controller programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 controller programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 PI programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 PI programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 0 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 0 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 1 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 1 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 2 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 2 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 3 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 3 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Address slice 0 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Address Slice 0 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR PI initialization started... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR Controller initialization started... <<<---
CORTEX_M4F_0: GEL Output: --->>> Waiting for frequency change requests ... <<<---
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 0 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to 20MHz/19.2MHz on silicon (bypass)
CORTEX_M4F_0: GEL Output: Set DDR1 PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 0 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to 20MHz/19.2MHz on silicon (bypass)
CORTEX_M4F_0: GEL Output: Set DDR1 PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set.
CORTEX_M4F_0: GEL Output: --->>> All frequency change requests have completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> LPDDR4 Initialization is DONE! <<<---
CORTEX_M4F_0: GEL Output: --->>> LPDDR4 Initialization is in progress ... <<<---
CORTEX_M4F_0: GEL Output: Setting DDR2 PLL to 20MHz/19.2MHz on silicon (bypass)
CORTEX_M4F_0: GEL Output: Set DDR2 PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
CORTEX_M4F_0: GEL Output: --->>> DDR2 controller programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 controller programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 PI programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 PI programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 PHY Data Slice 0 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 PHY Data Slice 0 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 PHY Data Slice 1 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 PHY Data Slice 1 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 PHY Data Slice 2 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 PHY Data Slice 2 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 PHY Data Slice 3 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 PHY Data Slice 3 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 PHY Address slice 0 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 PHY Address Slice 0 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 PHY programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR2 PHY programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR PI initialization started... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR Controller initialization started... <<<---
CORTEX_M4F_0: GEL Output: --->>> Waiting for frequency change requests ... <<<---
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR2 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 27 (DDR2 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 27 (DDR2 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 0 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR2 PLL to 20MHz/19.2MHz on silicon (bypass)
CORTEX_M4F_0: GEL Output: Set DDR2 PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR2 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 27 (DDR2 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 27 (DDR2 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 0 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR2 PLL to 20MHz/19.2MHz on silicon (bypass)
CORTEX_M4F_0: GEL Output: Set DDR2 PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR2 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 27 (DDR2 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 27 (DDR2 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR2 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 27 (DDR2 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 27 (DDR2 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR2 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 27 (DDR2 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 27 (DDR2 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR2 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 27 (DDR2 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 27 (DDR2 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR2 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 27 (DDR2 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 27 (DDR2 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR2 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 27 (DDR2 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 27 (DDR2 PLL) Set.
CORTEX_M4F_0: GEL Output: --->>> All frequency change requests have completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> LPDDR4 Initialization is DONE! <<<---
CORTEX_M4F_0: GEL Output: --->>> LPDDR4 Initialization is in progress ... <<<---
CORTEX_M4F_0: GEL Output: Setting DDR3 PLL to 20MHz/19.2MHz on silicon (bypass)
CORTEX_M4F_0: GEL Output: Set DDR3 PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
CORTEX_M4F_0: GEL Output: --->>> DDR3 controller programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 controller programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 PI programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 PI programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 PHY Data Slice 0 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 PHY Data Slice 0 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 PHY Data Slice 1 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 PHY Data Slice 1 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 PHY Data Slice 2 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 PHY Data Slice 2 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 PHY Data Slice 3 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 PHY Data Slice 3 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 PHY Address slice 0 programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 PHY Address Slice 0 programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 PHY programming in progress.. <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR3 PHY programming completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR PI initialization started... <<<---
CORTEX_M4F_0: GEL Output: --->>> DDR Controller initialization started... <<<---
CORTEX_M4F_0: GEL Output: --->>> Waiting for frequency change requests ... <<<---
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR3 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 28 (DDR3 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 28 (DDR3 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 0 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR3 PLL to 20MHz/19.2MHz on silicon (bypass)
CORTEX_M4F_0: GEL Output: Set DDR3 PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR3 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 28 (DDR3 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 28 (DDR3 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 0 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR3 PLL to 20MHz/19.2MHz on silicon (bypass)
CORTEX_M4F_0: GEL Output: Set DDR3 PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR3 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 28 (DDR3 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 28 (DDR3 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR3 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 28 (DDR3 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 28 (DDR3 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR3 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 28 (DDR3 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 28 (DDR3 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR3 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 28 (DDR3 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 28 (DDR3 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR3 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 28 (DDR3 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 28 (DDR3 PLL) Set.
CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller
CORTEX_M4F_0: GEL Output: Setting DDR3 PLL to produce a clock at 1066MHz.
CORTEX_M4F_0: GEL Output: Programming Main PLL 28 (DDR3 PLL)
CORTEX_M4F_0: GEL Output: Main PLL 28 (DDR3 PLL) Set.
CORTEX_M4F_0: GEL Output: --->>> All frequency change requests have completed... <<<---
CORTEX_M4F_0: GEL Output: --->>> LPDDR4 Initialization is DONE! <<<---

Scripts hangs here.

Thanks in advance.

Hi,

Burak Burak said:

we were also unable to boot from SD card as well

 Did you get any error while boot from SD card? and if possible could you share your launch.js  file?

Regards,

Karthik

Hi,

Serial console does not log anything while trying to boot from SD card. I guess, even, U-boot does not run.

Here is the launch.js.

/*
 * Copyright (c) 2022, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

//
//File Name: launch_j784s4.js
//Description:
//   Launch the DMSC firmware and board configuration from R5F.
//
//Usage:
//
//From CCS Scripting console
//  1. loadJSFile "C:\\ti\\launch_j784s4.js"
//
//Note:
//  1. Search for "edit this" to look at changes that need to be edited
//     for your usage.
//


//<!!!!!! EDIT THIS !!!!!>
// Set this to 1, if using 'FreeRTOS'
isFreertos = 1;
// Set this to 1, if using 'SafeRTOS'
isSafertos = 0;

//PDK path. Edit this
//pdkPath = "/ti/j7presi/workarea/pdk";

pdkPath = "/home/mycomputer/ti/ti-processor-sdk-rtos-j784s4-evm-09_01_00_06/pdk_j784s4_09_01_00_22/";

//path to board config elf
pathSciclient = pdkPath+"/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j784s4/"
ccs_init_elf_file = pathSciclient+"sciclient_ccs_init_mcu1_0_release.xer5f";

// Set this to 1, to clear 'Secure Claim' Bit in CLEC register
clearCLECSecureClaimFlag = 1;

loadSciserverFlag = 1; //1

if(isFreertos == 1)
{
    //Path to FreeRTOS sciserver
    sciserver_elf_file = pathSciclient+"sciserver_testapp_freertos_mcu1_0_release.xer5f";
}
else if(isSafertos == 1)
{
    //Path to SafeRTOS sciserver
    sciserver_elf_file = pathSciclient+"sciserver_testapp_safertos_mcu1_0_release.xer5f";
}
//path to sysfw bin
sysfw_bin = pdkPath+"/packages/ti/drv/sciclient/soc/sysfw/binaries/ti-fs-firmware-j784s4-gp.bin"

//<!!!!!! EDIT THIS !!!!!>

// Import the DSS packages into our namespace to save on typing
importPackage(Packages.com.ti.debug.engine.scripting)
importPackage(Packages.com.ti.ccstudio.scripting.environment)
importPackage(Packages.java.lang);
importPackage(Packages.java.io);

function updateScriptVars()
{
    //Open a debug session
    dsMCU1_0 = debugServer.openSession( ".*MCU_Cortex_R5_0" );
    dsMCU1_1 = debugServer.openSession( ".*MCU_Cortex_R5_1" );
    dsDMSC_0 = debugServer.openSession( ".*CORTEX_M4F_0" );
}

function printVars()
{
    updateScriptVars();
}

function connectTargets()
{
    /* Set timeout of 200 seconds */
    script.setScriptTimeout(2000000);
    updateScriptVars();
    sysResetVar=dsDMSC_0.target.getResetType(1);
    sysResetVar.issueReset();
    print("Connecting to Cortex_M4F_0!");
    // Connect targets
    dsDMSC_0.target.connect();
    print("Fill R5F ATCM memory...");
    dsDMSC_0.memory.fill(0x61000000, 0, 0x8000, 0);
    print("Writing While(1) for R5F")
    dsDMSC_0.memory.writeWord(0, 0x61000000, 0xE59FF004); /* ldr        pc, [pc, #4] */
    dsDMSC_0.memory.writeWord(0, 0x61000004, 0x38);       /* Address 0x38 */
    dsDMSC_0.memory.writeWord(0, 0x61000038, 0xEAFFFFFE) /* b          #0x38 */
    print("Loading DMSC Firmware ... " + sysfw_bin);
    // Load the DMSC firmware
    dsDMSC_0.memory.loadRaw(0, 0x40000, sysfw_bin, 32, false);
    print("DMSC Firmware Load Done...");
    // Set Stack pointer and Program Counter
    stackPointer = dsDMSC_0.memory.readWord(0, 0x40000);
    progCounter = dsDMSC_0.memory.readWord(0, 0x40004);
    dsDMSC_0.memory.writeRegister("SP", stackPointer);
    dsDMSC_0.memory.writeRegister("PC", progCounter);
    print( "DMSC Firmware run starting now...");
    // Run the DMSC firmware
    dsDMSC_0.target.runAsynch();
    /* Run the DDR Configuration */
    print("J784S4 Running the DDR configuration... Wait till it completes!");
    dsDMSC_0.target.halt();
    dsDMSC_0.expression.evaluate("J7_LPDDR4_Config_Late()");
    dsDMSC_0.target.runAsynch();
    print("Connecting to MCU Cortex_R5_0!");

    // Connect the MCU R5F
    dsMCU1_0.target.connect();

    // This is done to support other boot modes. OSPI is the most stable.
    // MMC is not always stable.
    bootMode = dsMCU1_0.memory.readWord(0, 0x43000030) & 0xF8;
    print (" WKUP Boot Mode is " + bootMode);
    mainBootMode = dsMCU1_0.memory.readWord(0, 0x100030) & 0xFF;
    print (" Main Boot Mode is " + mainBootMode);
    if ((bootMode != 0x38) || (mainBootMode != 0x11))
    {
        print("Disable MCU Timer for ROM clean up");
        dsMCU1_0.memory.writeWord(0, 0x40400010, 0x1); /* Write reset to MCU Timer 0. Left running by ROM */
        dsMCU1_0.memory.writeWord(0, 0x40F80430, 0xFFFFFFFF); /* Clear Pending Interrupts */
        dsMCU1_0.memory.writeWord(0, 0x40F80018, 0x0); /* Clear Pending Interrupts */
        // Reset the R5F to be in clean state.
        dsMCU1_0.target.reset();
        // Load the board configuration init file.
        dsMCU1_0.expression.evaluate('GEL_Load("'+ ccs_init_elf_file +'")');
        // Run Asynchronously
        dsMCU1_0.target.runAsynch();
        print ("Running Async");
        // Halt the R5F and re-run.
        dsMCU1_0.target.halt();
    }
    // Reset the MCU R5F Core 1, to ensure the ATCM/BTCM config takes effect
    print("Connecting to MCU R5 1 0");
    dsMCU1_1.target.connect();
    print("Reset MCU R5 10, to ensure TCMs configurations take effect");
    dsMCU1_1.target.reset();

    // Reset the R5F to be in clean state.
    dsMCU1_0.target.reset();
    print("Running the board configuration initialization from R5!");
    // Load the board configuration init file.
    dsMCU1_0.memory.loadProgram(ccs_init_elf_file);
    // Halt the R5F and re-run.
    dsMCU1_0.target.halt();
    // Run Synchronously for the executable to finish
    dsMCU1_0.target.run();
    dsMCU1_0.target.halt();
    dsMCU1_0.target.reset();


    dsMCU1_0.target.restart();

}

function disconnectTargets()
{
    updateScriptVars();
    // Reset the R5F to be in clean state.
    dsMCU1_0.target.reset();
    dsMCU1_1.target.disconnect();

    // Disconnect targets
    dsDMSC_0.target.disconnect();
}

function sampleDDRCheck ()
{
    print("Running DDR Memory Checks....");
    dsMCU1_0.memory.fill (0x80000000, 0, 1024, 0xA5A5A5A5);
    ar = dsMCU1_0.memory.readWord(0, 0x80000000, 1024);
    fail = 0
    for (i = 0; i < ar.length; i++) {
            x = ar[i];
            if (x != 0xA5A5A5A5)
            {
                fail = 1;
            }
        }
    if (fail == 1)
    {
        print ("0x80000000: DDR memory sample check failed !!");
    }
    dsMCU1_0.memory.fill (0x81000000, 0, 1024, 0x5A5A5A5A);
    ar = dsMCU1_0.memory.readWord(0, 0x81000000, 1024);
    fail = 0
    for (i = 0; i < ar.length; i++) {
            x = ar[i];
            if (x != 0x5a5a5a5a)
            {
                fail = 1;
            }
        }
    if (fail == 1)
    {
        print ("0x81000000: DDR memory sample check failed !!");
    }

}

function loadSciserver()
{
    updateScriptVars();
    print("######################################################################################");
    print("Loading Sciserver Application on MCU1_0. This will service RM/PM messages");
    print("If you do not want this to be loaded update the launch script to make loadSciserverFlag = 0");
    print("If you want to load and run other cores, please run the MCU1_0 core after Sciserver is loaded. ");
    print("######################################################################################");
    dsMCU1_0.expression.evaluate('GEL_Load("'+ sciserver_elf_file +'")');
}

function clearCLECSecureClaim()
{
    dsC7X1_0 = debugServer.openSession( ".*C71X_0" );

    dsC7X1_0.target.connect();

    c7x_binary = pdkPath+"/packages/ti/drv/sciclient/tools/clearClecSecureClaim/sciclient_clear_clec_secure_claim_c7x_1_release.xe71";

    dsC7X1_0.memory.loadProgram(c7x_binary);
    dsC7X1_0.target.runAsynch();

    // Halt and re-run since the startup code image doesn't have a main function.
    dsC7X1_0.target.halt();
    dsC7X1_0.target.runAsynch();

    dsC7X1_0.target.disconnect();
}

function doEverything()
{
    printVars();
    connectTargets();
    disconnectTargets();
    sampleDDRCheck ();
    if (clearCLECSecureClaimFlag == 1)
    {
        print("Clearing CLEC Secure Claim...");
        clearCLECSecureClaim();
    }
    if (loadSciserverFlag == 1)
    {
        loadSciserver();
    }
    print("Happy Debugging!!");
}

var ds;
var debugServer;
var script;

// Check to see if running from within CCSv4 Scripting Console
var withinCCS = (ds !== undefined);

// Create scripting environment and get debug server if running standalone
if (!withinCCS)
{
    // Import the DSS packages into our namespace to save on typing
    importPackage(Packages.com.ti.debug.engine.scripting);
    importPackage(Packages.com.ti.ccstudio.scripting.environment);
    importPackage(Packages.java.lang);

    // Create our scripting environment object - which is the main entry point into any script and
    // the factory for creating other Scriptable ervers and Sessions
    script = ScriptingEnvironment.instance();

    // Get the Debug Server and start a Debug Session
    debugServer = script.getServer("DebugServer.1");
}
else // otherwise leverage existing scripting environment and debug server
{
    debugServer = ds;
    script = env;
}

doEverything();

Thanks.

Hi,

Burak Burak said:

Serial console does not log anything while trying to boot from SD card. I guess, even, U-boot does not run.

Your boot mode seems to be incorrect; keep your board in no boot mode

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j784s4/10_00_00_05/exports/docs/psdk_rtos/docs/user_guide/evm_setup_j784s4.html

Regards,

Karthik

Hi Karthik,

The boot mode is correct, I' ve checked it for either no boot and sd card cases.

Hi Burak,

Burak Burak said:

The boot mode is correct, I' ve checked it for either no boot and sd card cases

Did you try the same test in different boot modes? If not,Would you try different boot modes (OSPI or SD)?

Regards,
Karthik