[FAQ] AM62A7: OSPI Phy Tuning Algorithm

What is OSPI Phy Tuning?

The OSPI Phy Tuning algorithm is meant for tuning the data line in accordance with the flash part(could be NAND or NOR flash part).

Some times due to:

1. Improper clock distribution network
2. Line skewness
3. Varying temperature(high temperatures like 100 C or low temperatures like -10 C)

The data is not aligned according to the clock shared between the SoC OSPI Controller and the Flash Part.

To make this alignment perfect, we run the OSPI Phy Tuning Algorithm and figure out three crucial values namely:

1. rxDLL
2. txDLL
3. readDelay

You can find these three values in the file named as ospi_phy.c in the MCU PLUS SDK AM6xx. Here is a snapshot of the same:

This is just an overview of what this algorithm is meant for, let's read further.

When is the Phy Tuning Algorithm used?

The Phy Tuning Algorithm computes the OTP value which is known as Optimal Tuning Point. This OTP value comprising of rxDLL, txDLL and readDelay once computed is saved.

Now, whenever Phy is enabled later on, the OTP value is used.

Please note that Phy is used only for FASTER READS from the Flash Part.

Assume that the OSPI has following configuration:

1. Clock Frequency: 166 MHz
2. Clock Divider value: 8

Then in this case, the OSPI_CLK will turn out to be 166/8 which is roughly 20 MHz.

But when Phy mode is enabled, the OSPI clock frequency is 166 MHz as the Clock Divider value(in this case 8) is by passed.

Where is the Phy enabled and disabled throughout the MCU PLUS SDK code offering?

In the MCU PLUS SDK, when you start development, you would come across different APIs for different peripherals and protocols.

The usual flow is as follows:

To look at a sample easy to understand flow, please check this: https://github.com/TexasInstruments/mcupsdk-core/blob/next/examples/hello_world/hello_world.c

Now in SysConfig when:

1. OSPI is added
2. Flash is added
3. Under OSPI:
   1. Phy mode is enabled and checked.

Then at step 2: Board_driversOpen() if you step inside the code then you would eventually find that:

1. For NAND flash part: the flow goes to flash_nand_ospi.c and the API Flash_nandOspiOpen() is called. In this case, the API OSPI_phyTuneSDR() or OSPI_phyTuneDDR() is called based on the protocol SDR/DDR selected.
   
   
2. For NOR flash part: the flow goes to flash_nor_ospi.c and the API Flash_norOspiOpen() is called. In this case the API OSPI_phyTuneSDR() or OSPI_phyTuneDDR() is called based on the protocol SDR/DDR selected.

A: Inside OSPI_phyTuneDDR, OSPI_phyFindOTP1 computes the optimal tuning point(OTP)

B: Inside OSPI_phyTuneSDR, OSPI_phyFindOTP3 computes the optimal tuning point(OTP)

Note inside APIs A and B the flow is as follows:

The next time Phy is enabled is when the API Flash_read() is called.

If you step inside Flash_read() the flow comes to a point as follows:

So, when the Phy is enabled, the read happens at a clock frequency of 166 MHz as the clock divider value is bypassed and then the Phy is disabled.

Where can I find the current DDR and SDR Tuning Algorithm implementation?

The DDR algorithm is OSPI_phyTuneDDR() --> OSPI_phyFindOTP1()

The SDR algorithm is OSPI_phyTuneSDR() --> OSPI_phyFindOTP3()

Learn more about DDR algorithm: https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/10_00_00_20/exports/docs/api_guide_am64x/DRIVERS_OSPI_PAGE.html#autotoc_md1867

Learn more about SDR algorithm: https://software-dl.ti.com/mcu-plus-sdk/esd/AM62AX/latest/exports/docs/api_guide_am62ax/DRIVERS_OSPI_PAGE.html#autotoc_md557