Hello,
Now I use SDK0805, and when set the phy enable and open ddr mode, I found the tuning always fail.so I set the phy enable false, I could read data from the flash. what can I do with it? If I close the phy, How does this affect the functionality?
Hello, I use PDK finally on mcu1_0 Boot app. and I use PHY with DDR in DAC mode. Finally, I found that when I enable Cache and use PHY，I need open the pipeline, is it? Here, if I do not open the pipeline, is there any error?
Hello, yes, I use J721E now, and after enable the pipeline, the DAC mode work well. But if I do not open pipeline, I read error bytes with DAC mode.
now, I get another error during writing. When I use DAC mode to write flash, I just can write one page. when I write more, I find some error.
I think there are some data that do not be written in the flash. I want to know if use DAC mode to write, how to get another page after write one.
We compared the OSPI_dac_xfer_mode_write interface in MCAL and OSPI_dac_xfer_mode_write_v0 interface in PDK and find OSPI_dac_xfer_mode_write_v0 will also clean the cache at the end of the function.
Currently we use the MCAL function and we have to use the write through cache policy otherwise some lines may not write successfully. But the write speed is quite slow.
Do we need to add this cache operation to speed up write flash? Thanks!
