TDA4VM-Q1: ospi controller phy-tune fail

Hi,

What is the frequency you are operating at? Also, are you using the DAC mode or the INDAC mode?

Regards,
Parth

Hello,

 The Freq I use is 133M, and I use DAC Mode.

Hello, I found that when BM run, the initial clock in function "SBL_ospiInit" of ospi is 166M in SDK0805, but in 0703SDK, it is 133M. in the config file "SPI_soc.c", the ospi clk is 133M, how can I deal with it?

Hello, I want to know that if the 0805Mcal supports the ospi phy mode or not. when I use 0703Mcal, I found the ospi phy mode work well. Now I use the 0803Mcal, the ospi phy mode does not work.

Hi,

What is your final use case? Are you planning to use PDK or MCAL finally?
Also, did you check the OSPI driver example? It does use the PHY with DDR in DAC mode?

Regards,
Parth

Hello, I use PDK finally on mcu1_0 Boot app. and I use PHY with DDR in DAC mode. Finally, I found that when I enable Cache and use PHY，I need open the pipeline, is it? Here, if I do not open the pipeline, is there any error?

Hi,

phy pipeline mode is supported only with DAC reads. It enhances the read speeds, but it is not mandatory to enable it. You should be able to read fine even with pipeline disabled.

Did you try the default example given in the PDK? Is that working fine for you?
Also, can you please confirm the SOC you are using. This is on J721e right and you are using a NOR Flash right?

Regards,
Parth

Hello, yes, I use J721E now, and after enable the pipeline, the DAC mode work well. But if I do not open pipeline, I read error bytes with DAC mode.

now, I get another error during writing. When I use DAC mode to write flash, I just can write one page. when I write more, I find some error.

I think there are some data that do not be written in the flash. I want to know if use DAC mode to write, how to get another page after write one.

Hi,

If you are not using the same flash as the EVM, you'll need to make some changes to adapt to new flash. Please see the FAQ:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1104992/faq-tda4vm-how-to-add-support-for-new-flash-device-in-rtos-sdk

Regards,
Parth

Hi, now the Flash can be written by change the cache policy to Write-through(CSL_ARM_R5_CACHE_POLICY_WT_NO_WA) but the Flash write speed is very slow.

When download the application file  to Flash by Vector vFlash tool , need 2 seconds to write 16 KB data. 

I use following Flash configuration actually the BaudRateDiv is 32(CSL_OSPI_BAUD_RATE_DIVISOR_DEFAULT) decided by MCAL code. If I change flsBaudRateDiv to 2 the erase operation will fail. 

Hi,

Pengfei Yuan said:

Do you know how to increase the Flash write speed ?

Please refer to performance numbers in the datasheet for different modes in the datasheet https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/08_06_00_12/exports/docs/pdk_jacinto_08_06_00_31/docs/datasheet/jacinto/datasheet_j721e.html#ospi-read-write-performance-ddr-octal-mode

You can either try DAC with DMA or INDAC mode for better performance.

Pengfei Yuan said:

When I use cache policy Write-back the Flash will write fail (some address are still 0xFF after write operation). Do you know the reason?

Are you performing cache operations to write back the data?

Pengfei Yuan said:

Does PHY mode only for read operation ?

Yes, that is correct.

Regards,
Parth

We compared the OSPI_dac_xfer_mode_write interface in MCAL and OSPI_dac_xfer_mode_write_v0 interface in PDK and find OSPI_dac_xfer_mode_write_v0 will also clean the cache at the end of the function.

Currently we use the MCAL function and we have to use the write through cache policy otherwise some lines may not write successfully. But the write speed is quite slow.

Do we need to add this cache operation to speed up write flash? Thanks!

Hi,

Can you please put a break point in OSPI_dac_xfer_mode_write_v0 and check if the cache ops are actually getting executed.
Also, can you please try the default PDK test once at your end once with cacheEnable and see if that works fine? This will help us isolate the problem.

Regards,
Parth

Hello, when I use cache and open cache during MPU configuration. I found that flash writed failed (some addresses are still 0xFF after write operation) with setting "maxWriteNormalMode" as 768 . Then set "maxWriteNormalMode" as 256, it also writed failed(just small addresses error with compared failed, But the value was not 0xFF).

Hello, now I use the Mcal Code and the cache op code was Manually added.

Hi,

Apologies for long silence.

Is this issue still open? Can you please mention the current state of the issue?

Regards,
Parth