PROCESSOR-SDK-J721S2: TDA4VE-Q1,J721S2 CSITX Question

Hi,

but why do you want to modify these clocks? Can you please elaborate what's requirement to connect to video processor? 

Regards,

Brijesh

HI TI,

In this project ,only support 1280x960x30hz for application.

We just to modify these dphy_TxByteClkHS_cl_clk and vbus_clk_clk, Reduce the number by two times from the current setting,like vbus_clk_clk:250MHz/2.

-- 
Thanks.
Best Regards.

hi terry,

but there is a driver interface for reducing the number of lanes to 2.. and you can update the lane speed required as per your receiving device. 

Regards,

Brijesh

Hi Brijesh,

It's hard for me to describe how this processor works.

Whether we reduce the lane speed or the number of lanes, the video processor input Pixels clock parameter also needs to be adjusted to 250Mhz to lock the frame.

The video processor vendor think the dphy_TxByteClkHS_cl_clk and vbus_clk_clk are setting too high,The video processor vendor hope to try lowering the frequency.

Could you help and talk to me how to  modify ? please...

-- 
Thanks.
Best Regards.

For now, we have some problems.

If we  using CSI RX to CSI TX example, J721s2 CSI TX outputs stably 33ms by per frame and the video processor can lock each frame normally.

If we  using vxProcessGraph  to CSI TX, J721s2 CSI TX outputs non-stably 33ms by per frame(about 27ms~33ms,Measure from oscilloscope,The video active data  is a fixed time, and the blanking time is not a fixed value.)

Such as the below thread:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1429324/tda4vm-is-blanking-config-of-csitx-node-work

Hi Terry,

But there is nothing like pixel clock for CSITX output. CSITX outputs clock on the lane and this is controlled using lane speed. 

In case of CSIRX -> CSITX, there is a constant 30fps output, due to CSIRX. But when you connect to CSITX, you need to make sure that the frame is submitted at every 33.3ms. 

Regards,

Brijesh

Hi Brijesh,

thanks your reply.

If we changed laneSpeedMbps ,Are there any other parameters that need to be modified?

dphyCfg->laneSpeedMbps = 477

dphyCfg->psmClkFreqDiv = CSITX_DPHY_PSM_CLK_FREQ_DIV_DEF;
dphyCfg->pllByteClkDiv = CSITX_DPHY_PLL_BYTE_CLK_DIV_DEF;
dphyCfg->pwmCtrlDivLow = CSITX_DPHY_PWM_CTRL_DIV_LOW_DEF;
dphyCfg->pwmCtrlDivHigh = CSITX_DPHY_PWM_CTRL_DIV_HIGH_DEF;
dphyCfg->pllLockThreshold = CSITX_DPHY_PLL_LOCK_THRESHOLD_DEF;
dphyCfg->pllLockStart = CSITX_DPHY_PLL_LOCK_START_DEF;
dphyCfg->pllIpDiv = CSITX_DPHY_PLL_IPDIV_DEF;
dphyCfg->pllOpDiv = CSITX_DPHY_PLL_OPDIV_DEF;
dphyCfg->pllFbDiv = CSITX_DPHY_PLL_FBDIV_DEF;
dphyCfg->pllPd = CSITX_DPHY_PLL_PD_DEF;

dphyCfg->waitBurstTime = CSITX_DPHY_WAIT_BURSTTIME_DEF;
dphyCfg->txClkExitTime = CSITX_DPHY_TX_CLK_EXITTIME_DEF;
dphyCfg->dlWkupTime = CSITX_DPHY_DL_WKUPTIME_DEF;
dphyCfg->clWkupTime = CSITX_DPHY_CL_WKUPTIME_DEF;


dphyCfg->clSlewRateCtrl = CSITX_DPHY_SLEWRATECTRL_DEF;
dphyCfg->dlSlewRateCtrl = CSITX_DPHY_SLEWRATECTRL_DEF;

Hi Brijesh,

How to make sure that the frame is submitted at every 33.3ms?

Please provide your method at the  below thread:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1429324/tda4vm-is-blanking-config-of-csitx-node-work

-- 
Thanks.
Best Regards.

Hi Tarry,

I am not sure which SDK release are you using, but in the latest release, providing laneSpeedMbps is sufficient.. 

One possible way is to start a timer, which expires every 33ms and generates a callback and in this callback, you could submit the new frame to the driver. 

Regards,

Brijesh

Hi Brijesh,

We used  SDK 8.4 and replace the csi tx rtos driver with pdk_j721s2_10_00_00_27

-- 
Thanks.
Best Regards.

Hi Brijesh,

We saw the description of  Vertical Blanking time in the csitx driver as below:

Is the blank time calculated in pixels or lines???

pdk_j721s2_10_00_00_27\packages\ti\drv\csitx\include\csitx_cfg.h

/** \brief Vertical Blanking: Default VB (in terms of number of pixels)
* used for initialization */
#define CSITX_IN_FRAME_VB_DEFAULT (0U)

-- 
Thanks.
Best Regards.

Hi Terry,

Is your lane speed set to high value compare to total speed required? Like if you are setting it 1.5Gbps, the total speed would be 6Gpbs for 4 lanes output and if you are just sending 1920x1080 YUV422 output at 30fps, it require only around 1Gbps total speed (1920x1080x30x16). So you are using only around 16% of the total BW and in this case, the only way to send frame at every 33.3ms is to use timer. On every timer callback, please submit a frame to the CSITX driver. 

Btw, which component is feeding to the CSITX? Is it eventually connected to CSIRX?

Regards,

Brijesh

Hi Brijesh,

My csi tx parameter as below:

H active:1280 pixels 

V active:960 lines

H blank:310 pixels 

V blank:290 lines

 lane speed:477 Mbps

2 lane 

(1280+310) *(960+290)*2*30*8/2=477Mbps

which component is feeding to the CSITX? Is it eventually connected to CSIRX?<=====Are you referring to what our video chips use in hardware?

-- 
Thanks.
Best Regards.

Hi Brijesh,

We don't quite understand what timer you are referring to?

We tried using a sw layer timer , But the situation didn't improve.

The unit of tmp is ms.

[MPU1_0]    129.859005 s: | I | default | @@@ tmp=34726

[MPU1_0]    129.893634 s: | I | default | @@@ tmp=31274

[MPU1_0]    353.269156 s: | I | default | @@@ tmp=35024

[MPU1_0]    353.300170 s: | I | default | @@@ tmp=31031

[MPU1_0]    494.773198 s: | I | default | @@@ tmp=35056

[MPU1_0]    494.804180 s: | I | default | @@@ tmp=31003

[MPU1_0]   1217.406915 s: | I | default | @@@ tmp=34779

[MPU1_0]   1217.438140 s: | I | default | @@@ tmp=31258

[MPU1_0]   1691.187255 s: | I | default | @@@ tmp=34178

[MPU1_0]   1691.219143 s: | I | default | @@@ tmp=31876

[MPU1_0]   1949.808275 s: | I | default | @@@ tmp=34093

[MPU1_0]   1949.840198 s: | I | default | @@@ tmp=31991

[MPU1_0]   2417.815036 s: | I | default | @@@ tmp=34850

[MPU1_0]   2417.846141 s: | I | default | @@@ tmp=31209

[MPU1_0]   2887.569358 s: | I | default | @@@ tmp=34192

[MPU1_0]   2887.601220 s: | I | default | @@@ tmp=31881

[MPU1_0]   3203.709390 s: | I | default | @@@ tmp=34288

[MPU1_0]   3203.741379 s: | I | default | @@@ tmp=31797

[MPU1_0]   3497.808414 s: | I | default | @@@ tmp=37324

[MPU1_0]   3497.837207 s: | I | default | @@@ tmp=28776

[MPU1_0]   3903.804246 s: | I | default | @@@ tmp=34070

[MPU1_0]   3903.836178 s: | I | default | @@@ tmp=31976

[MPU1_0]   3916.312580 s: | I | default | @@@ tmp=35456

[MPU1_0]   3916.343139 s: | I | default | @@@ tmp=30600

[MPU1_0]   4457.941698 s: | I | default | @@@ tmp=35609

[MPU1_0]   4457.972148 s: | I | default | @@@ tmp=30431

[MPU1_0]   4553.805224 s: | I | default | @@@ tmp=34034

[MPU1_0]   5404.776179 s: | I | default | @@@ tmp=34098

[MPU1_0]   5749.956368 s: | I | default | @@@ tmp=34237

[MPU1_0]   5749.988137 s: | I | default | @@@ tmp=31782

[MPU1_0]   5923.701191 s: | I | default | @@@ tmp=34066

[MPU1_0]   5923.733133 s: | I | default | @@@ tmp=31981

[MPU1_0]   6411.804206 s: | I | default | @@@ tmp=34045

[MPU1_0]   6787.840590 s: | I | default | @@@ tmp=35393

[MPU1_0]   6787.871153 s: | I | default | @@@ tmp=30550

[MPU1_0]   6987.622371 s: | I | default | @@@ tmp=35218

[MPU1_0]   6987.653141 s: | I | default | @@@ tmp=30830

[MPU1_0]   7203.804215 s: | I | default | @@@ tmp=34075

[MPU1_0]   7203.836214 s: | I | default | @@@ tmp=31995

[MPU1_0]   7650.030952 s: | I | default | @@@ tmp=34822

[MPU1_0]   7650.062107 s: | I | default | @@@ tmp=31223

[MPU1_0]   7929.804268 s: | I | default | @@@ tmp=34141

[MPU1_0]   7929.836203 s: | I | default | @@@ tmp=31946

[MPU1_0]   8476.978784 s: | I | default | @@@ tmp=35626

[MPU1_0]   8477.009133 s: | I | default | @@@ tmp=30408

[MPU1_0]   8577.000528 s: | I | default | @@@ tmp=34397

[MPU1_0]   8577.032160 s: | I | default | @@@ tmp=31632

[MPU1_0]   8767.113507 s: | I | default | @@@ tmp=34413

[MPU1_0]   8767.145139 s: | I | default | @@@ tmp=31635

[MPU1_0]   8804.272453 s: | I | default | @@@ tmp=35352

[MPU1_0]   8804.303204 s: | I | default | @@@ tmp=30716

[MPU1_0]   8961.814989 s: | I | default | @@@ tmp=35870

[MPU1_0]   8961.845165 s: | I | default | @@@ tmp=30186

[MPU1_0]  10031.806912 s: | I | default | @@@ tmp=35816

[MPU1_0]  10031.837186 s: | I | default | @@@ tmp=30212

[MPU1_0]  10774.206200 s: | I | default | @@@ tmp=34137

[MPU1_0]  10774.238198 s: | I | default | @@@ tmp=31965

[MPU1_0]  10841.823563 s: | I | default | @@@ tmp=34328

[MPU1_0]  10841.855138 s: | I | default | @@@ tmp=31717

[MPU1_0]  11002.302492 s: | I | default | @@@ tmp=34352

[MPU1_0]  11002.334131 s: | I | default | @@@ tmp=31680

[MPU1_0]  11263.266147 s: | I | default | @@@ tmp=34016

[MPU1_0]  11708.733414 s: | I | default | @@@ tmp=34310

[MPU1_0]  11708.765142 s: | I | default | @@@ tmp=31732

[MPU1_0]  12143.805908 s: | I | default | @@@ tmp=34794

[MPU1_0]  12143.837194 s: | I | default | @@@ tmp=31295

[MPU1_0]  12564.060519 s: | I | default | @@@ tmp=34420

[MPU1_0]  12564.092092 s: | I | default | @@@ tmp=31625

[MPU1_0]  12681.804219 s: | I | default | @@@ tmp=34087

[MPU1_0]  12816.840736 s: | I | default | @@@ tmp=34670

[MPU1_0]  12816.872205 s: | I | default | @@@ tmp=31464

[MPU1_0]  13313.821565 s: | I | default | @@@ tmp=35423

[MPU1_0]  13313.852192 s: | I | default | @@@ tmp=30663

[MPU1_0]  13399.422215 s: | I | default | @@@ tmp=34151

[MPU1_0]  13399.454122 s: | I | default | @@@ tmp=31915

[MPU1_0]  13793.805167 s: | I | default | @@@ tmp=34005

[MPU1_0]  14265.804228 s: | I | default | @@@ tmp=34078

[MPU1_0]  14265.836167 s: | I | default | @@@ tmp=31997

[MPU1_0]  14321.806987 s: | I | default | @@@ tmp=35826

[MPU1_0]  14321.837189 s: | I | default | @@@ tmp=30249

[MPU1_0]  14955.803872 s: | I | default | @@@ tmp=36707

[MPU1_0]  14955.833166 s: | I | default | @@@ tmp=29331

[MPU1_0]  15297.054185 s: | I | default | @@@ tmp=34070

[MPU1_0]  15297.086129 s: | I | default | @@@ tmp=31969

[MPU1_0]  15769.812545 s: | I | default | @@@ tmp=34361

[MPU1_0]  15769.844185 s: | I | default | @@@ tmp=31724

[MPU1_0]  15779.845780 s: | I | default | @@@ tmp=35515

[MPU1_0]  15779.876143 s: | I | default | @@@ tmp=30423

[MPU1_0]  16565.838387 s: | I | default | @@@ tmp=34182

[MPU1_0]  16565.870151 s: | I | default | @@@ tmp=31773

[MPU1_0]  17415.820019 s: | I | default | @@@ tmp=34864

[MPU1_0]  17415.851188 s: | I | default | @@@ tmp=31219

[MPU1_0]  17777.961847 s: | I | default | @@@ tmp=34720

[MPU1_0]  17777.993096 s: | I | default | @@@ tmp=31297

[MPU1_0]  17822.973532 s: | I | default | @@@ tmp=34449

[MPU1_0]  17823.005135 s: | I | default | @@@ tmp=31618

[MPU1_0]  17887.554288 s: | I | default | @@@ tmp=34144

[MPU1_0]  17887.586130 s: | I | default | @@@ tmp=31904

[MPU1_0]  18688.233762 s: | I | default | @@@ tmp=34664

[MPU1_0]  18688.265146 s: | I | default | @@@ tmp=31385

[MPU1_0]  18998.632090 s: | I | default | @@@ tmp=34814

[MPU1_0]  18998.663152 s: | I | default | @@@ tmp=31230

[MPU1_0]  19337.806965 s: | I | default | @@@ tmp=35831

[MPU1_0]  19337.837202 s: | I | default | @@@ tmp=30275

[MPU1_0]  19413.144287 s: | I | default | @@@ tmp=34156

[MPU1_0]  19413.176168 s: | I | default | @@@ tmp=31910

[MPU1_0]  19423.178699 s: | I | default | @@@ tmp=36551

[MPU1_0]  19423.208127 s: | I | default | @@@ tmp=29480

[MPU1_0]  20271.804246 s: | I | default | @@@ tmp=34104

[MPU1_0]  20928.703567 s: | I | default | @@@ tmp=35429

[MPU1_0]  20928.734121 s: | I | default | @@@ tmp=30612

[MPU1_0]  21659.586179 s: | I | default | @@@ tmp=34076

[MPU1_0]  21659.618121 s: | I | default | @@@ tmp=31962

[MPU1_0]  22089.972678 s: | I | default | @@@ tmp=34558

[MPU1_0]  22090.004129 s: | I | default | @@@ tmp=31473

[MPU1_0]  22193.328319 s: | I | default | @@@ tmp=34179

[MPU1_0]  22193.360128 s: | I | default | @@@ tmp=31869

[MPU1_0]  22313.811218 s: | I | default | @@@ tmp=34060

[MPU1_0]  22835.673217 s: | I | default | @@@ tmp=34096

[MPU1_0]  22835.705171 s: | I | default | @@@ tmp=31993

[MPU1_0]  22911.804618 s: | I | default | @@@ tmp=34462

[MPU1_0]  22911.836136 s: | I | default | @@@ tmp=31583

[MPU1_0]  23196.990358 s: | I | default | @@@ tmp=34216

[MPU1_0]  23197.022101 s: | I | default | @@@ tmp=31819

[MPU1_0]  23367.633181 s: | I | default | @@@ tmp=34032

[MPU1_0]  23759.047129 s: | I | default | @@@ tmp=35004

[MPU1_0]  23759.078137 s: | I | default | @@@ tmp=31057

[MPU1_0]  24511.842794 s: | I | default | @@@ tmp=34532

[MPU1_0]  24511.874118 s: | I | default | @@@ tmp=31435

[MPU1_0]  25043.803419 s: | I | default | @@@ tmp=35201

[MPU1_0]  25043.834171 s: | I | default | @@@ tmp=30893

[MPU1_0]  25681.824190 s: | I | default | @@@ tmp=34018

[MPU1_0]  25716.838955 s: | I | default | @@@ tmp=35818

[MPU1_0]  25716.869177 s: | I | default | @@@ tmp=30282

[MPU1_0]  26127.753507 s: | I | default | @@@ tmp=34368

[MPU1_0]  26127.785201 s: | I | default | @@@ tmp=31687

[MPU1_0]  26388.717240 s: | I | default | @@@ tmp=34087

[MPU1_0]  26388.749141 s: | I | default | @@@ tmp=31956

[MPU1_0]  26670.768105 s: | I | default | @@@ tmp=34006

[MPU1_0]  27512.862916 s: | I | default | @@@ tmp=34837

[MPU1_0]  27512.894181 s: | I | default | @@@ tmp=31258

[MPU1_0]  27773.826818 s: | I | default | @@@ tmp=34697

-- 
Thanks.
Best Regards.

Hi Brijesh,

Thanks for your reply and waiting for your r5f timer patch file .

By the way, can we use GPIO interrupt(from ub960 generated 33ms fsync to TDA4) to trigger csitx callback ?

-- 
Thanks.
Best Regards.

Hi Terry,

There are ways to trigger to DMA on timer interrupt, so although it is possible, its not supported in the SDK by default and also i am not sure if the buffer is going to be ready when this interrupt comes. 

Regards,

Brijesh

Hi Terry,

Any further questions on this thread? 

Regards,

Brijesh

Hi Brijesh,

Thanks for your support,We have no other questions in this thread.

thanks.