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TDA4VM-Q1: lpddr4 timing budget

筱彦 李
Prodigy 20 points
Part Number: TDA4VM-Q1

Tool/software:

I am using Cadence systemSI simulation LPDDR4, the main control chip is TDA4VM88TGCALFRQ1,memorty particle is MT53E1G32D2FW-046 AUT:B; systemSI driving terminal has two timing parameters in DATA Write mode:min transmit setup \min transmit hold, please ask how to find these two parameters in the manual?

  • 0
    TI__Mastermind 34930 points

    Hi,

    For DDR, we recommend simulating to evaluate signal integrity and power integrity of the PCB design, not for timing analysis. 

    The DQ to DQS timing relationship will be "trained" to compensate for flight time (skew) differences.

    Regards,
    Kevin