HI Board designers,
Please refer below
Q.1
TPS65219: AM62P support
Customer already use the TPS65219 today for an AM62x design and would like to re-use the same PMIC with the new AM62P.
However, I see our recommendation is to use the new TPS65224-Q1 which is larger and more expensive.
Is there any reason why the TPS65219 can't support the AM62P? Has any analysis been done to show any shortcomings?
The input current requirements are higher for the AM62P than the AM62x, so the TPS65224-Q1 is required to meet these power requirements.
You can see the power architecture in Figure 2-25 in this document: https://www.ti.com/lit/ug/spruja2/spruja2.pdf
Q.2
About the GPIO pins of PMICs
Can the GPIO pins on the PMIC be used as part of the rising and falling sequence signals of the sequence?
The way to use it is to set the output high when the BUCKx starts. If the power supply drops, can the GPIO of the PMIC be set to Low output?
yes this can be implemented with the PFSM but not with simple I2C writes.
PFSM is short for pre-configurable finite state machine which is configured and written to the device by Texas Instruments to meet the customers needs.
Customer can't reprogram the PFSM due to the limitations of OTP (one time programmable memory).
Q.3
About the power rails of TPS65224
We had read that GPIO3(pin8) is used to select the BUCK1&2 output power rail.
The NVM default BUCK1&2 output is 0.75v, actually we want to use 0.85v.
0.75V is the default option. BUCK12 output can be configured to 0.85V by having a 10k pull-up resistor in GPIO3 when powering the TPS6522430-Q1.
Q,4 About ADC (GPIO4 and GPIO5)
From GPIO pin assigned as ADC_IN to ground. If GPIO4
is used as ADC_IN, VADC_IN ≤ VIO. If GPIO5 is used as
ADC_IN, VADC_IN ≤ 1.8V
Regards,
Sreenivasa
HI Board designers,
Depending on the use case TPS65224 can be used with AM62A7 / AM62A7-Q1 / AM62A3 / AM62A3-Q1 processor family.
Please refer below for queries related to operation of PMIC with 5V input
FAQs for reference
Regards,
Sreenivasa
HI Board designers,
Refer below inputs related to I2C1 and I2C2 connection
For automotive functional safety use cases, connect MCU_I2C0 of the processor to PMIC (TPS65224 / TPS65222) I2C1.
I2C channel 1 (I2C1) is the main channel with access to the registers, which control the configurable power
sequencer, the states and the outputs of power rails, the device operating states and the Error Signal Monitor.
I2C channel 2 (I2C2), which is available through the GPIO1 and GPIO2 pins, is dedicated for accessing the Q&A
Watchdog communication registers. If GPIO1 and GPIO2 are not configured as I2C2 pins, I2C1 can access all
of the registers, including the Q&A Watchdog registers. Alternatively, depending on the NVM-configuration of
the Orderable Part Number (OPN), SPI is the selected interface for the device and can be used to access all
from PMIC point of view there is no issue in not using the I2C2. As already stated in the original thread the I2C2 is used solely for the Q&A watchdog but that can also be carried by I2C1. Also trigger watchdog is available via GPIO2 but it is also an option to not use it at all. The WKUP domain is responsible for the low power modes in my understanding so this will not affect the low power modes in any way.
Reason for two I2C buses for the PMIC is that there is more bandwidth for the main I2C when constant watchdog communication isn't needed to be carried over the same bus. There is no limitations when running these on the same bus though if the bandwidth allows it. In order to use Q&A watchdog over I2C1 line the GPIO1 and 2 have to be assigned to anything else than the I2C2 function and nothing else is required. Please note that in this case the I2C2 address is still needed to address the watchdog registers through I2C1 line.
Registers.
Regards,
Sreenivasa
Hi Board designers
Input regarding selection of PMIC:
The recommend PMIC(s) on the product folder or used on the SK or EVM schematics has been designed considering the power sequencing, supply rail output slew, nRSTOUT (reset output) delay output from PMIC connected to MCU_PORz after all the supplies ramp for clock to be stable and the sizing of the supply rails based on the processor worst case current draw.
When choosing an alternate non-TI PMIC, the recommendation for custom board designers is to review the relevant collaterals including the data sheet and Maximum Current Ratings document and follow the requirements/recommendations. The recommendation is to review the slew rate requirements, Power-up and power-down sequence sections of the data sheet and confirm the non-TI PMIC based power architecture follows the recommendation.
An important point to note is the processor does not support dynamic scaling of the core voltage or the analog supplies.
Inputs regarding supply decay
Refer below FAQ
I have placed the note in both sections because it applies to both power-up and power-down. The power-up sequence should not begin until all power rails are below 300mV, and the power-down sequence is not complete until all power rails are below 300mV.
Regards,
Sreenivasa
HI Board designers,
Inputs on power supply sizing:
Using Maximum Current Ratings application note vs Power Estimation Tool PET
The max current app note is representing the current draw for a group of rails. Please note that it is not expected for this current to necessarily be replicated in the power estimation tool. The PET will tend to show more average use case power while the max current app note is intended to be used for power supply sizing as it will allow for the max transient on these groups with some margin. The PET should not be used for power supply sizing.
Regards,
Sreenivasa
HI Board designers,
Refer below debug steps for board-bringup
My customer has selected our TPS6522430RAHRQ1 to power AP62P-Q1 in a headlight domain control unit project.
After the customer got their board and powered it on, they found that the output voltage would be pulled down in a cycle of 1.1s, and each low output lasted for 100ms. After repeating for 12s, the output was completely turned off.
Before debugging, the customer made the following changes on the board:
Directly connect Pin 17 to an always 3.3V power rail.
Directly connect GPIO 6 to an always 3.3V power rail.
The customer currently suspects that the problem may be related to the watchdog in PMIC. Could you please help analyze the possible root cause of the problem?
If it is indeed related to the watchdog, is there any way to turn off the watchdog?
have they checked the user's guide for this configuration in secure folder? We just released a new version of this document which should be better than the original. They can request access here.
This doesn't seem to be watchdog issue since the default long window is 12 minutes long so if they don't start servicing it, it will not timeout this fast. I suspect they have orderlyOff2Safe sequence happening because it has this 100ms delay before starting up again. This is caused by almost every rail in the PMIC and also some internal features.
I see that they have 1uH inductors for the bucks which is not a recommended value. For 4.4 MHz in this configuration the only recommended inductor value is 220nH. This could cause the output to be outside of the voltage monitor range and cause UVOV interrupt which would cause orderlyOff2Safe sequence.
Also they only seem to have 4.7uF capacitors at buck inputs as the recommendation is 10uF with minimum allowed capacitance of 3uF so if these 4.7uF capacitors derate too much they could go below this and cause issues.
Is customer aware of the use-case selection this particular OTP has? This device has four different use cases which are selected by GPIO3/4 external resistors. Please see the user's guide for more information. I don't see an issue due to this though.
The watchdog can be disabled (WD_PWRHOLD=0x1) by pulling GPIO6 high before (or at the same time] supplying the VCCA for the PMIC. This is explained in the user's guide.
Customer should read the interrupts of the PMIC somehow as it will most often lead to the root cause. If they can't do it with on-board MCU then they can use external device similar to usb2any. If this still isn't possible then I would like to see the power up sequence measurement to see if some rail is not powering on correctly or doesn't reach the correct operating voltage.
Regards,
Sreenivasa
HI Board designers,
Note:
How were these pdn specs derived? Is it based on worst case analysis?
Yes it is based on worst case load transient estimates for a given SoC design.
The Target impedance for AM62x and AM62xSiP will be identical as the same worst case load transients exist on both designs since they share the same die.
Via sharing recommendations in the escape application note are only made to help guide a customer to escape the design with fewer vias in the VCA regions. The number of vias used for escaping signals will ultimately depend on the specific customer use-case, the number of interfaces that need to be implemented and the layer count. If the specific use case allows the customer to use more vias for VDD_CORE in the VCA regions, that is definitely a valid approach. Per-pin loop inductance guidelines are more applicable for single-pin supplies that are connected to a decap. In case of multi-pin supplies like VDD_CORE where there are a number of parallel connections to multiple pins/decap thru multiple vias, it is hard to tie it back in to a per-pin requirement. The most important target to meet is the impedance target specified in Table 7-6 of the PDN Applications note. This table is the same for AM62x and AM62x SiP.
We do not include Buck output inductance in PDN simulations.
For VDDS_DDR: we do not recommend using target impedance as the signoff for DDR.
Refer to the AM62x, AM62Lx DDR Board Design and Layout Guidelines which outlines all details of power aware SI/PI simulations
that need to be run. The eye mask checks from these power aware simulations are the signoff.
Power Distribution Networks: Implementation and Analysis
Sitara Processor Power Distribution Networks: Implementation and Analysis
https://www.ti.com/lit/pdf/sprac76
Note: The decoupling capacitor numbers and type on the SK/EVM are only intended to serve as a guideline for customers. The true pass/fail criteria is the target impedance published in the PDN app note.
High Speed Board design and Signal integrity simulation
https://www.ti.com/lit/pdf/spraar7
https://www.ti.com/lit/pdf/spracn9
https://www.ti.com/lit/pdf/sprabi1
Inputs on PDN
Please refer below inputs i received:
Please note these are only recommendations and they need to contact their EDA vendor on what works best for their specific simulation environment.
1、Do I need to separate VDD_CORE-1 to 17 for simulation, or use VDD_CORE as a Port?
TI>> You can lump all VDD_CORE BGAs together as a single terminal for the port
2、Do I need to include the PMIC FB loop in the simulation?
TI>> If you are simulating only for AC impedance (target impedance checks) this is not required. The board layout from the inductor onwards (inductor not included) can be modeled and PMIC FB loop can be studied separately.
3、 Is the simulation starting frequency from 1Hz or from a minimum of 100kHz for the capacitor S2P?
TI>> There should be some DC frequency points added. Please check with your EDA vendor on the exact setup and simulation points needed to generate causal models.
I added additional inputs related to PDN and decoupling capacitors for reference.
The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth
PCB design & Dcap scheme combine to form your board's Power Distribution Network (PDN) that should meet recommended SoC PI performance targets for robust processor operations. Each PCB design has a "unique finger-print" based upon component placements, power & Gnd routing, layer assignments, via qtys & locations, Dcap mounting & loop inductance, Dcap parameters, etc. As a result, an optimized Dcap scheme will vary from one PCB design to another but should provide a system PDN that meets PI performance targets when combined together. Similarly, the PI simulation tools can impact the estimated ZvsF response values, especially above 3.0MHz where non-3D extraction tools can return better Z values (10-15% less than more accurate 3D tools). This ican be due to a non-3D tool is only extracting a PCB's X & Y design elements & assuming a power & Gnd via inductances. Due to the 3D nature of current flow across & through a PCB from power & Gnd planes on different PCB layers, a 3D extraction gives a more accurate series inductance estimate needed to more accurately model power & Gnd vias which leads to a more accurate power rail impedance (ZvsF) response
it would be difficult to comment on reducing the amount of decoupling caps without going through the exercise ourselves. That said, you can likely prioritize the high-current and sensitive analog rails, then look to share bypass caps when you hit space constraints. Having decap as close to the BGA as possible will reduce inductance and improve their efficacy (two supply vias with a shared decap would be better than a decap located far away in most circumstances).
Please be aware that each PCB design is unique and may need different Dcap scheme to meet recommended PI parameter targets
Regarding decoupling capacitors, the recommendation is to start with the EVMs decoupling and then optimize (if needed) based on your power simulation results.
For the placement of the Caps and values, we would still recommend using the EVM as a reference along with the PDN document.
SK uses an EMI Filter at 1uF, can I replace it with a general ceramic capacitor?
The SK performance has been tested with 3-T terminal caps.
You may have to add multiple 2-T caps for each cap and perform simulations to finalize the values.
PDN application note
https://www.ti.com/lit/an/sprac76g/sprac76g.pdf
Regards,
Sreenivasa
HI Board designers,
Inputs related to delay between supply rails for processor power-up sequence
AM6442: Powering AM6442BSFFHAALV with TPS6522430RAHRQ1
The processor sequencing requirements can be found in the datasheet under "Power Supply Sequencing".
Power Supply Sequencing I can only find the order of the rails.
However, the delays between the different power supplies are not specified in the datasheet.
The only delay mentioned is the one between “all supplies valid” and the MCU_PORs (9.5ms).
Does this mean that the delays between the power supplies themselves don’t matter, and only the sequence is relevant?
We do not specify the delay between rails. Instead, we have slew rate requirements and sequence order. A supply group must fully ramp to the targeted output voltage with the required slew rate before the next one in sequence start ramping up.
I don't see any issue with this lower load condition. Is the 1.3A the typical/average current of this rail or the absolute maximum which occurs during load transients?
Regards,
Sreenivasa
