AM62P-Q1: AM62P Does DSS drivers support BT656?

Dear Expert.

upload more detail from customer.

there is 8bit data lines between DSS and ext SERDES.

4. assuming it is YUV422 output, 16bit/Pixel, please check if AM62P DSS can support 8bit BT656 as below customer HW design?

thanks a lot!

yong

Dear DIvyansh.

may I ask if you have update here?

thanks a lot!

yong

Hi,

I have checked internally and our current drivers do not have support for BT656 YUV signal.

Regards

Divyansh

what’s the max pixel clock frequency and the resolution limits of 8bit BT656 mode?

Hi,

We do not have BT656 supported on our EVMs yet, hence I will not able able to comment upon pixel clock and resolution.

As I mentioned, our current drivers do not support the BT656 mode.

Regards

Divyansh

Dear Divyansh

Thanks for the sharing that we don’t have DSS driver to support that.

Actually my local customer, Long-horn team, wants to confirm that if DSS HW can support their requirement from HW perspective. That is why they ask max pixel clock frequency and the resolution limits of 8bit BT656 mode.

Would you please help check this?

please let us know if you need customer schematic to confirm that.

thanks a lot!

yong

I am out for a couple of days, please expect a response by the end of this week.

Hi,

We do have hardware support for BT656 as mentioned in https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1335231/am62p-does-am62p-support-bt656.

To know about max pixel clock and resolution supported by DSS hardware, I will have to get back to you.

Dear expert.

one more request from local customer.

as they provided, there is one APN for TDA2(J6), https://www.ti.com/lit/an/spracg3/spracg3.pdf. it shows one concept that cheat hardware deal YUV422 as RGB565 with bypassing DSS CSC.

AM62P shows that some pipeline processing block can be bypassed independently. 

So customer request us to help check if the concept is possible on AM62P (J7).

please notice, on current customer HW design, they only connect 8bit data lines to outside (the serealizer). this is the limitation that why they are checking if 8bit YUV BT656 is supported in this HW design.

thanks a lot!

yong

Hi,

Yong Zhang said:

AM62P shows that some pipeline processing block can be bypassed independently. 

Bypass as shown in image can be done.

Yong Zhang said:

So customer request us to help check if the concept is possible on AM62P (J7).

I cannot comment if following the TDA2 appnote can enable YUV in AM62P, especially since the section you referred is for discrete syncs, and AM62P can only support embedded syncs and we cannot test this on our platforms.