AM625: Problem Enabling Additional UART Clocks in the R5 SPL

Part Number: AM625

Tool/software:

Hello,

I am attempting to switch the UART console port on my board. I have been following a process similar to the post here:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1345922/am625-console-output-uart0-to-uart2

However I am switching to UART1 instead of UART2. I am beginning first with the R5 modifications alone to the clock tree. See my below changes to add the additional nodes needed:

diff --git a/arch/arm/mach-k3/am62x/clk-data.c b/arch/arm/mach-k3/am62x/clk-data.c
index c0881778fe..7ba8f2f187 100644
--- a/arch/arm/mach-k3/am62x/clk-data.c
+++ b/arch/arm/mach-k3/am62x/clk-data.c
@@ -125,6 +125,11 @@ static const char * const main_usart0_fclk_sel_out0_parents[] = {
        "hsdiv4_16fft_main_1_hsdivout1_clk",
 };
 
+static const char * const main_usart1_fclk_sel_out0_parents[] = {
+       "usart_programmable_clock_divider_out1",
+       "hsdiv4_16fft_main_1_hsdivout1_clk",
+};
+
 static const struct clk_data clk_list[] = {
        CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
        CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
@@ -209,9 +214,11 @@ static const struct clk_data clk_list[] = {
        CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
        CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
        CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
+       CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out1", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108244, 0, 2, 0, 0, 48000000),
        CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
        CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
        CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
+       CLK_MUX("main_usart1_fclk_sel_out0", main_usart1_fclk_sel_out0_parents, 2, 0x108284, 0, 1, 0),  
        CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
        CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
        CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
@@ -311,6 +318,10 @@ static const struct dev_clk soc_dev_clk_data[] = {
        DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
        DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
        DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+       DEV_CLK(152, 0, "main_usart1_fclk_sel_out0"),
+       DEV_CLK(152, 1, "usart_programmable_clock_divider_out1"),
+       DEV_CLK(152, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
+       DEV_CLK(152, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(157, 20, "clkout0_ctrl_out0"),
        DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
        DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
diff --git a/arch/arm/mach-k3/am62x/dev-data.c b/arch/arm/mach-k3/am62x/dev-data.c
index 140dca4bd1..e8cb8c51b6 100644
--- a/arch/arm/mach-k3/am62x/dev-data.c
+++ b/arch/arm/mach-k3/am62x/dev-data.c
@@ -61,6 +61,7 @@ static struct ti_dev soc_dev_list[] = {
        PSC_DEV(36, &soc_lpsc_list[11]),
        PSC_DEV(102, &soc_lpsc_list[11]),
        PSC_DEV(146, &soc_lpsc_list[11]),
+       PSC_DEV(152, &soc_lpsc_list[11]),
        PSC_DEV(13, &soc_lpsc_list[12]),
        PSC_DEV(166, &soc_lpsc_list[13]),
        PSC_DEV(135, &soc_lpsc_list[14])

In booting tiboot3.bin, I am running into the same error message that person in the other post did (they never provided a resolution):

U-Boot SPL 2023.04-ti-g2c09eee5084d (Nov 15 2024 - 14:58:45 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.7--v09.02.07 (Kool Koala)')
k3_ddrss memorycontroller@f300000: clk get failed-2

I enabled DEBUG prints as suggested, and see the additional output:

U-Boot SPL 2023.04-ti-g2c09eee5084d (Nov 15 2024 - 14:58:45 +0000)                                                                                 
clk_set_defaults(sysctrler)                                                                                                                        
clk_set_default_parents: could not read assigned-clock-parents for 43c345a8                                                                        
clk_set_defaults(secproxy@44880000)                                                                                                                
clk_set_default_parents: could not read assigned-clock-parents for 43c34540                                                                        
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.7--v09.02.07 (Kool Koala)')                                                                               
clk_set_defaults(esm@420000)                                                                                                                       
clk_set_default_parents: could not read assigned-clock-parents for 43c34608                                                                        
clk_set_defaults(esm@4100000)                                                                                                                      
clk_set_default_parents: could not read assigned-clock-parents for 43c33a28                                                                        
clk_set_defaults(memorycontroller@f300000)                                                                                                         
clk_set_default_parents: could not read assigned-clock-parents for 43c34670                                                                        
of_xlate() failed: -2                                                                                                                              
k3_ddrss memorycontroller@f300000: clk get failed-2                                                                                                
clk_request(dev=43c33e7c, clk=43c3a048)                                                                                                            
clk_get_rate(clk=43c3a048)                                                                                                                         
clk_get_rate(clk=43c358c0)                                                                                                                         
clk_get_parent_rate(clk=43c358c0)                                                                                                                  
clk_get_parent(clk=43c358c0)                                                                                                                       
clk_set_rate(clk=43c3a028, rate=25000000)                                                                                                          
clk_get_rate(clk=43c358c0)                                                                                                                         
clk_get_parent_rate(clk=43c358c0)                                                                                                                  
clk_get_parent(clk=43c358c0)                                                                                                                       
clk_get_parent(clk=43c358c0)                                                                                                                       
clk_get_rate(clk=43c35740)                                                                                                                         
clk_get_rate(clk=43c35740)                                                                                                                         
clk_get_parent(clk=43c35740)                                                                                                                       
clk_get_rate(clk=ffffffed)

I am wondering if someone from TI can provide guidance here before I spend additional time trying to debug this:

  • Hello,

    MAIN_UART1 is reserved by TIFS for UART logging. Hence it is not possible to switch to UART1 from UART0
    https://software-dl.ti.com/tisci/esd/latest/4_trace/trace.html#trace-uart-allocation

    However, you can use any other MAIN_UART port. Let me know if that is possible for you?

    Regards,
    Aparna

  • Hi Aparna, thanks for your reply.

    Isn't TIFS logging disabled by default in the build? If it is disabled, can this port still be used?

    FYI, I tried this same procedure with a different port, like in the other post (UART0 to UART2) with the same results - error thrown regarding clk. So it seems the error at hand is unrelated to which port is used.

    Please advise, thanks.

  • Hi,

    Yes, looks like UART0 logs can be sent to UART2 port. I will need to do the experimentation myself to comment on this. Please allow me 3 working days to get back on this query.

    Regards,
    Aparna

  • Thank you Aparna, I look forward to your reply.

  • Hi Aparna,

    Just a friendly followup to see if you have made any progress or gained any insight on this. Thanks.

  • Hi Aparna,

    I see a reply from you but it only shows up in my email not here.

    Regarding where I got the clock changes, I used the linked forum post as a reference and I modified according to the instance I was using - the IDs, register offsets, etc. I found available both in the TI SDK docs as well as the reference manual.

  • Hi Apartha,

    Just following up on this. Were you able to find the issue? Is there anything additional I can provide you to assist?

  • Hello,

    It's been a few weeks since I have seen any reply on this. Is someone from TI able to provide an updated status?

    Thanks

  • Hi Aparna,

    I wanted to follow up on this thread again. I understand things can get busy, but I am still hoping to get your input on this UART R5 issue. Have you had any chance to look into it further? Please let me know if there is any other information I can provide to help.

  • Can someone from TI please advise on the status of this? There has been no reply in almost a month.

    Thanks

  • Hello, can someone from TI please advise on the status of this. There has been no response in 2 months.

  • Hi Ken,

    Sorry for the delay. I am taking over the support of this thread, and will provide you the details later today once I clean up my work queue.

  • Hi Ken,

    The following U-Boot changes the U-Boot console from UART0 to UART1. I tested it with SDK10.0. Please let me know if it works for you.

    diff --git a/arch/arm/dts/k3-am62x-sk-common.dtsi b/arch/arm/dts/k3-am62x-sk-common.dtsi
    index 59ee49616505..5e8276ced9ca 100644
    --- a/arch/arm/dts/k3-am62x-sk-common.dtsi
    +++ b/arch/arm/dts/k3-am62x-sk-common.dtsi
    @@ -12,7 +12,7 @@
     
     / {
            aliases {
    -               serial2 = &main_uart0;
    +               serial2 = &main_uart1;
                    mmc0 = &sdhci0;
                    mmc1 = &sdhci1;
                    mmc2 = &sdhci2;
    @@ -355,9 +355,10 @@
     &main_uart1 {
            /* Main UART1 is used by TIFS firmware */
            bootph-pre-ram;
    -       status = "reserved";
    +       status = "okay";
            pinctrl-names = "default";
            pinctrl-0 = <&main_uart1_pins_default>;
    +       clock-frequency = <48000000>;
     };
     
     &main_i2c0 {
    diff --git a/arch/arm/mach-k3/r5/am62x/dev-data.c b/arch/arm/mach-k3/r5/am62x/dev-data.c
    index 59c95df2a887..808a07eb5533 100644
    --- a/arch/arm/mach-k3/r5/am62x/dev-data.c
    +++ b/arch/arm/mach-k3/r5/am62x/dev-data.c
    @@ -60,7 +60,7 @@ static struct ti_dev soc_dev_list[] = {
            PSC_DEV(75, &soc_lpsc_list[10]),
            PSC_DEV(36, &soc_lpsc_list[11]),
            PSC_DEV(102, &soc_lpsc_list[11]),
    -       PSC_DEV(146, &soc_lpsc_list[11]),
    +       PSC_DEV(152, &soc_lpsc_list[11]),
            PSC_DEV(13, &soc_lpsc_list[12]),
            PSC_DEV(166, &soc_lpsc_list[13]),
            PSC_DEV(135, &soc_lpsc_list[14]),

  • Hi Bin,

    Thanks for the reply! I need to check this, give me a couple of days to verify and I will let you know if it solves the issue.