J722SXH01EVM: J722S

Zorah Ahmad

Part Number: J722SXH01EVM

Tool/software:

Hello,

I am attempting to use MCSPI on the J722S but my chip select(CS) interval in too small. I want it to be at least 2xclock=2x1us= 2us. Right now CS interval is 125 nano seconds. I also want there to be a delay of at least 2 clock cycles between chip select changing and the start of the clock. This is the configuration I am currently using.

In multi master mode I tried to change Chip select TCS in syscfg to 3 but I was not able to observe any resulting waveform on my logic analyzer after this change. Please guide on how to establish CS interval correctly

3 months ago

0 Tarun Mukesh Puvvada 3 months ago

TI__Mastermind 36355 points

Hello,

The chip-select timing control is available only in master mode with automatic CS generation (the [0] SINGLE bit set to 0) to add a programmable delay between CS assertion and first clock edge, or CS removal and last clock edge. This option is available only in 4-pin mode when [1] PIN34 set to 0.This mode is programmable per channel through the /1/2/3[26-25] TCS0 bit field.

If PIN34 is set to 1 the controller is in 3-pin mode and SPIEN[i] is not used. In this mode all options related to chip select management are useless (EPOL, FORCE and TCS0 bits of /1/2/3).

Regards

Tarun Mukesh

0 Zorah Ahmad 3 months ago in reply to Tarun Mukesh Puvvada

TI__Expert 3875 points

Hi Tarun,

What do you mean by if PIN34 is set to 1? You can see in syscfg I have set the device to 4 pin mode. What is Pin 34 and how is it being set to 1?

Can TCS not be used with multimaster? With TCS I can change the starting/ending time btw chipselect and clock

I have chosen multi master mode because when I keep everything the same but choose single master mode I do not the chip select toggle between consecutive 16 bits of data i.e between 0x5678 and 0x8765. You can see the behavior with single master below

0 Zorah Ahmad 3 months ago in reply to Zorah Ahmad

TI__Expert 3875 points

This is the desired behavior, what I want the SPI output to look like ie the part where the data on the MOSi is 0x5678 0x8765

I need the following conditions to be true

Right now I am struggling with points 1 and 3. In multimaster mode I am unable to achieve 1(setting TCS in syscfg results in no waveform) and 3(how to change the width of the CS toggle to at least 2 spi clocks). In master mode I am able to achieve 1(setting TCS in syscfg successfully allows delay at start and end of waveform) but CS toggle between words disappears(see below waveform)

0 Zorah Ahmad 3 months ago in reply to Zorah Ahmad

TI__Expert 3875 points

Can you help me achieve the desired waveform in either master or multi master mode?

0 Zorah Ahmad 3 months ago in reply to Zorah Ahmad

TI__Expert 3875 points

These are the parameters I set in my code

0 Zorah Ahmad 3 months ago in reply to Zorah Ahmad

TI__Expert 3875 points

Hello Can you please help with this?

0 Zorah Ahmad 3 months ago in reply to Tarun Mukesh Puvvada

TI__Expert 3875 points

For me MCSPI_CFG_MODULCTRL at 04B0 0128h is 0000 0001

0 Vaibhav Kumar 3 months ago in reply to Zorah Ahmad

TI__Mastermind 29594 points

Hi,

Considering the IP of MCSPI to be same across processors.

I have looked at your code and while reading values or writing values, I have seen that the dataSize defined by you is 16 bits, which is desired.

But your RX Buffer is of uint8 type, hence you can see that the values received is 0x56, 0x78. I guess in order to receive them as 0x5678 you need to make the rxBuffer uint16 instead of uint8.

This is just my top level understanding.

Thanks,

Vaibhav