J722SXH01EVM: Enabling GPIO interrupts in PROCESSOR-SDK-LINUX-J722S

Jin Lee

Part Number: J722SXH01EVM
Other Parts Discussed in Thread: SK-TDA4VM, TDA4VM

Tool/software:

Hi,

I am trying to enable interrupts for GPIO0_15, GPIO0_17, GPIO0_19, and GPIO0_21 on the TDA4AEN.

Referring to this thread, https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1058595/faq-tda4vm-how-to-test-gpio-interrupts, I first created a gpio_test node in k3-j722s-evm.dts:

    ...
	vsys_io_1v2: regulator-vsys-io-1v2 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_io_1v2";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <1200000>;
		regulator-always-on;
		regulator-boot-on;
	};

	gpio_test: gpio_test {
		compatible = "ti,gpio_test";
		interrupt-parent = <&main_gpio0>;
		interrupts = <69 IRQ_TYPE_EDGE_FALLING>;
	};

	hdmi0: connector-hdmi {
	...

&main_gpio:

&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&gpio0_pins_default>;
status = "okay";
};

gpio0_pins_default:

&main_pmx0 {

	///delete-property/ interrupts;
	
	gpio0_pins_default: gpio0-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x0118, PIN_INPUT, 7) /* (H26) MMC2_CLK.GPIO0_69  	| AWR3_RESETn */
		>;
	};

However, the interrupt does not show up on the kernel:

root@j722s-evm:~# cat /proc/interrupts 
           CPU0       CPU1       CPU2       CPU3       
 11:       2987       3399       3207       3010     GICv3  30 Level     arch_timer
 14:          0          0          0          0     GICv3 130 Level     pinctrl
 15:          4          0          0          0     GICv3 108 Level     mbox-r5-0
 16:          4          0          0          0     GICv3 109 Level     mbox-mcu-r5-0
 19:          0          0          0          0     GICv3  23 Level     arm-pmu
 20:       1368          0          0          0     GICv3  66 Level     4d000000.mailbox thr_012
 26:          0          0          0          0     GICv3 197 Level     2b200000.i2c
 27:         52          0          0          0     GICv3 193 Level     20000000.i2c
 28:         49          0          0          0     GICv3 194 Level     20010000.i2c
 29:          4          0          0          0     GICv3 195 Level     20020000.i2c
 30:       1962          0          0          0  MSI-INTA 1713152 Level     485c0100.dma-controller chan0
112:          9          2          0          0  MSI-INTA 1970707 Level     8000000.ethernet-tx0
120:          0          0          0          0  MSI-INTA 1970715 Level     8000000.ethernet-tx1
128:          0          0          0          0  MSI-INTA 1970723 Level     8000000.ethernet-tx2
136:          0          0          2          1  MSI-INTA 1970731 Level     8000000.ethernet-tx3
144:          4          0          0          0  MSI-INTA 1970739 Level     8000000.ethernet-tx4
152:          0          5          0          1  MSI-INTA 1970747 Level     8000000.ethernet-tx5
160:          0          0          2          0  MSI-INTA 1970755 Level     8000000.ethernet-tx6
168:          0          0          0          3  MSI-INTA 1970763 Level     8000000.ethernet-tx7
184:          0          0          0          0  MSI-INTA 1970779 Level     485c0000.dma-controller chan2
202:         11          7          0          0  MSI-INTA 1971731 Level     8000000.ethernet
226:          0          0          0          0  MSI-INTA 1971755 Level     485c0000.dma-controller chan0
227:          0          0          0          0  MSI-INTA 1971756 Level     485c0000.dma-controller chan1
274:        886          0          0          0     GICv3 210 Level     2800000.serial
275:          2          0          0          0     GICv3 171 Level     fc40000.spi
277:          0          0          0          0     GICv3 208 Level     4b00000.spi
278:          0          0          0          0     GICv3 209 Level     4b10000.spi
279:          0          0          0          0     GICv3 204 Level     20100000.spi
280:          0          0          0          0     GICv3 206 Level     20120000.spi
281:          0          0          0          0     GICv3 134 Level     8000000.ethernet
292:        694          0          0          0     GICv3 165 Level     mmc0
392:          0          0          0          0      GPIO  67 Edge    -davinci_gpio  2-0020
490:          0          0          0          0     GICv3 131 Edge      j721e-pcie-link-down-irq
491:          0          0          0          0   ITS-MSI   0 Edge      PCIe PME, aerdrv
492:      11216          0          0          0     GICv3 115 Level     mmc1
493:          0          0          0          0 2-0020  13 Edge      2-003b
497:          0          0          0          0     GICv3 132 Level     2b1f0000.rtc
498:          0          0          0          0     GICv3 257 Level     vpu_irq
501:        141          0          0          0     GICv3 258 Level     xhci-hcd:usb1
503:          0          0          0          0     GICv3 277 Level     31200000.usb
IPI0:       647       1458       1178       1080       Rescheduling interrupts
IPI1:      2109       3060       3132       3159       Function call interrupts
IPI2:         0          0          0          0       CPU stop interrupts
IPI3:         0          0          0          0       CPU stop (for crash dump) interrupts
IPI4:         0          0          0          0       Timer broadcast interrupts
IPI5:         0          0          0          0       IRQ work interrupts
IPI6:         0          0          0          0       CPU wake-up interrupts
Err:          0

I tried with GPIO0_69 after getting the same failure with GPIO0_15, thinking maybe the I2C expander is the issue, but get the same results.

Could you advise on what I'm doing wrong and how to enable GPIO interrupts?

Things I've tried:

I'm able to create regular GPIOs and have tested their functionality w/ gpioset and a logic analyzer (J28 expansion header)

root@j722s-evm:~# gpioinfo -c gpiochip2 
gpiochip2 - 87 lines:
        line   0:       unnamed                 input
        line   1:       unnamed                 input
        line   2:       unnamed                 input
        line   3:       unnamed                 input
        line   4:       unnamed                 input
        line   5:       unnamed                 input
        line   6:       unnamed                 input
        line   7:       unnamed                 input
        line   8:       unnamed                 input
        line   9:       unnamed                 input
        line  10:       unnamed                 input
        line  11:       unnamed                 input
        line  12:       unnamed                 input
        line  13:       unnamed                 input
        line  14:       unnamed                 input
        line  15:       "AWR1_SPI_INT"          input
        line  16:       "AWR2_RESETn"           input
        line  17:       "AWR2_SPI_INT"          input
        line  18:       unnamed                 input
        line  19:       "AWR3_SPI_INT"          input
        line  20:       "AWR4_RESETn"           input
        line  21:       "AWR4_SPI_INT"          input
        line  22:       unnamed                 input
        line  23:       unnamed                 input
        line  24:       unnamed                 input
        line  25:       unnamed                 input
        line  26:       unnamed                 input
        line  27:       unnamed                 input
        line  28:       unnamed                 input
        line  29:       unnamed                 input
        line  30:       unnamed                 input
        line  31:       "AWR1_RESETn"           input
        line  32:       unnamed                 input
        line  33:       unnamed                 input
        line  34:       unnamed                 input
        line  35:       unnamed                 input
        line  36:       "AWR_SOP0"              input
        line  37:       unnamed                 input
        line  38:       unnamed                 input
        line  39:       unnamed                 input
        line  40:       unnamed                 input
        line  41:       unnamed                 input
        line  42:       unnamed                 input
        line  43:       unnamed                 input
        line  44:       unnamed                 input
        line  45:       unnamed                 input
        line  46:       unnamed                 input
        line  47:       unnamed                 input
        line  48:       unnamed                 input
        line  49:       unnamed                 input
        line  50:       unnamed                 input
        line  51:       unnamed                 input
        line  52:       unnamed                 input
        line  53:       unnamed                 input
        line  54:       unnamed                 input
        line  55:       unnamed                 input
        line  56:       unnamed                 input
        line  57:       unnamed                 input
        line  58:       unnamed                 input
        line  59:       unnamed                 input
        line  60:       unnamed                 input
        line  61:       unnamed                 input
        line  62:       unnamed                 input
        line  63:       unnamed                 input
        line  64:       unnamed                 input
        line  65:       unnamed                 input
        line  66:       unnamed                 input
        line  67:       unnamed                 input
        line  68:       unnamed                 input
        line  69:       "AWR3_RESETn"           input
        line  70:       unnamed                 output consumer=tlv71033
        line  71:       unnamed                 input
        line  72:       unnamed                 input
        line  73:       unnamed                 input
        line  74:       unnamed                 input
        line  75:       unnamed                 input
        line  76:       unnamed                 input
        line  77:       unnamed                 input
        line  78:       unnamed                 input
        line  79:       unnamed                 input
        line  80:       unnamed                 input
        line  81:       unnamed                 input
        line  82:       unnamed                 input
        line  83:       unnamed                 input
        line  84:       unnamed                 input
        line  85:       unnamed                 input
        line  86:       unnamed                 input

k3-j722s-evm.dts:

&main_gpio0 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio0_pins_default>;
	gpio-line-names = 	"", "", "", "", "", "", "", "", "", "", "", "",
						"", "", "", "AWR1_SPI_INT", "AWR2_RESETn", "AWR2_SPI_INT", "", "AWR3_SPI_INT", "AWR4_RESETn", "AWR4_SPI_INT", "", "",
						"", "", "", "", "", "", "", "AWR1_RESETn", "", "", "", "",
						"AWR_SOP0", "", "", "", "", "", "", "", "", "", "", "",
						"", "", "", "", "", "", "", "", "", "", "", "",
						"", "", "", "", "", "", "", "", "", "AWR3_RESETn", "", "";
	status = "okay";
};

&main_gpio1 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio1_pins_default>;
	gpio-line-names = 	"", "", "", "", "", "", "", "", "", "AWR_SOP2", "AWR_SOP1", "",
						"AWR_ERROR_OUTn";
	status = "okay";
};

&main_pmx0 {

	///delete-property/ interrupts;
	
	gpio0_pins_default: gpio0-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x007c, PIN_INPUT, 7) /* (T23) GPMC0_CLK.GPIO0_31 	| AWR1_RESETn	*/
			J722S_IOPAD(0x003c, PIN_INPUT, 7) /* (R22) GPMC0_AD0.GPIO0_15 	| AWR1_SPI_INT */
			J722S_IOPAD(0x0040, PIN_INPUT, 7) /* (R23) GPMC0_AD1.GPIO0_16 	| AWR2_RESETn */
			J722S_IOPAD(0x0044, PIN_INPUT, 7) /* (R26) GPMC0_AD2.GPIO0_17 	| AWR2_SPI_INT */
			J722S_IOPAD(0x0118, PIN_INPUT, 7) /* (H26) MMC2_CLK.GPIO0_69  	| AWR3_RESETn */
			J722S_IOPAD(0x004c, PIN_INPUT, 7) /* (T25) GPMC0_AD4.GPIO0_19 	| AWR3_SPI_INT */
			J722S_IOPAD(0x0050, PIN_INPUT, 7) /* (T24) GPMC0_AD5.GPIO0_20 	| AWR4_RESETn */
			J722S_IOPAD(0x0054, PIN_INPUT, 7) /* (T21) GPMC0_AD6.GPIO0_21 	| AWR4_SPI_INT */
			
			J722S_IOPAD(0x0094, PIN_INPUT, 7) /* (P26) GPMC0_BE1n.GPIO0_36	| AWR_SOP0 */
		>;
	};
	gpio1_pins_default: gpio1-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x01a0, PIN_INPUT, 7) /* (F23) MCASP0_AXR0.GPIO1_10 | AWR_SOP1 */
			J722S_IOPAD(0x019c, PIN_INPUT, 7) /* (B25) MCASP0_AXR1.GPIO1_9 	| AWR_SOP2 */
			J722S_IOPAD(0x01a8, PIN_INPUT, 7) /* (C26) MCASP0_AFSX.GPIO1_12 | AWR_ERROR_OUTN */
		>;
	};
...

When I try adding interrupts in main_gpio0 in k3-am62p-main.dtsi, there is no change.

	main_gpio0: gpio@600000 {
		compatible = "ti,am64-gpio", "ti,keystone-gpio";
		reg = <0x00 0x00600000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = 	<190>, <191>, <192>,
			     		<193>, <194>, <195>,
						<15>, <17>, <19>, <21>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <92>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 77 0>;
		clock-names = "gpio";
		gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
				<&main_pmx0 70 72 22>;
	};

Thank you,

Jin

4 months ago

0 Keerthy J 4 months ago

TI__Guru**** 151940 points

Hi,

Jin Lee said:
I am trying to enable interrupts for GPIO0_15, GPIO0_17, GPIO0_19, and GPIO0_21 on the TDA4AEN.

Can you read out the corresponding pinmux registers and check that they read 0x50007.

The mode should be mode7 for GPIO and bit18 RX_ACTIVE should be set.

Let us first confirm that pinmux is setup properly.

- Keerthy

0 Jin Lee 4 months ago in reply to Keerthy J

TI__Intellectual 1471 points

Hi Keerthy,

Confirming that the pinmux registers are set accordingly:

root@j722s-evm:~# devmem2 0x000F403C
/dev/mem opened.
Memory mapped at address 0xffff99525000.
Read at address  0x000F403C (0xffff9952503c): 0x00050007
root@j722s-evm:~# devmem2 0x00F4044
/dev/mem opened.
Memory mapped at address 0xffff9cf28000.
Read at address  0x000F4044 (0xffff9cf28044): 0x00050007
root@j722s-evm:~# devmem2 0x00F404C
/dev/mem opened.
Memory mapped at address 0xffffbb897000.
Read at address  0x000F404C (0xffffbb89704c): 0x00050007
root@j722s-evm:~# devmem2 0x00F4054
/dev/mem opened.
Memory mapped at address 0xffff89c01000.
Read at address  0x000F4054 (0xffff89c01054): 0x00050007

0 Jin Lee 4 months ago in reply to Jin Lee

TI__Intellectual 1471 points

Hi Keerthy,

In addition, GPIO_BINTEN registers seem set to enable interrupts:

root@j722s-evm:~# devmem2 0x00600008
/dev/mem opened.
Memory mapped at address 0xffff9405e000.
Read at address  0x00600008 (0xffff9405e008): 0x0000003F

However, GPIO_SET_FAL_TRIG45 shows that GPIO0_69 trigger is not set. only the io-expander (GPIO0_67).

root@j722s-evm:~# devmem2 0x00600080
/dev/mem opened.
Memory mapped at address 0xffffb2cc4000.
Read at address  0x00600080 (0xffffb2cc4080): 0x00000008
root@j722s-evm:~#

0 Keerthy J 4 months ago in reply to Jin Lee

TI__Guru**** 151940 points

Hi,

Jin Lee said:
Confirming that the pinmux registers are set accordingly:

Thanks. They are looking correct.

We have indirectly verified the GPIO interrupts via:

        exp2: gpio@20 {
                compatible = "ti,tca6416";
                reg = <0x20>;
                gpio-controller;
                #gpio-cells = <2>;
                gpio-line-names = "DSI_Mux_SEL_2", "GPIO_eDP_ENABLE",
                                  "DP0_PWR_SW_EN", "GPIO_OLDI_RSTn",
                                  "GPIO_HDMI_RSTn", "HDMI_LS_OE",
                                  "", "",
                                  "DSI_GPIO0", "DSI_GPIO1",
                                  "DSI_EDID", "IO_eDP_IRQ",
                                  "OLDI_INT#", "HDMI_INTn",
                                  "", "";

                interrupt-parent = <&main_gpio0>;
                interrupts = <67 IRQ_TYPE_EDGE_FALLING>;
                interrupt-controller;
                #interrupt-cells = <2>;

Jin Lee said:
In addition, GPIO_BINTEN registers seem set to enable interrupts:

Okay. Are the pins correctly set as output in the GPIO register space?

Which exact pin are you looking for or you are trying to validate any GPIO for interrupts?

- Keerthy

0 Jin Lee 4 months ago in reply to Keerthy J

TI__Intellectual 1471 points

Hi Keerthy,

Which exact pin are you looking for or you are trying to validate any GPIO for interrupts?

We are specifically trying to enable interrupts GPIO0_15, GPIO0_17, GPIO0_19, and GPIO0_21.

Okay. Are the pins correctly set as output in the GPIO register space?

It seems all the GPIOs are set as inputs except for GPIO0_70, used by tlv71033

root@j722s-evm:~# devmem2 0x00600010
/dev/mem opened.
Memory mapped at address 0xffff91ef2000.
Read at address  0x00600010 (0xffff91ef2010): 0xFFFFFFFF
root@j722s-evm:~# devmem2 0x00600038
/dev/mem opened.
Memory mapped at address 0xffffbd3e6000.
Read at address  0x00600038 (0xffffbd3e6038): 0xFFFFFFFF
root@j722s-evm:~# devmem2 0x00600060
/dev/mem opened.
Memory mapped at address 0xffffac7b3000.
Read at address  0x00600060 (0xffffac7b3060): 0xFFFFFFBF

root@j722s-evm:~# gpioinfo -c gpiochip2 
gpiochip2 - 87 lines:
        line   0:       unnamed                 input
        line   1:       unnamed                 input
        line   2:       unnamed                 input
        line   3:       unnamed                 input
        line   4:       unnamed                 input
        line   5:       unnamed                 input
        line   6:       unnamed                 input
        line   7:       unnamed                 input
        line   8:       unnamed                 input
        line   9:       unnamed                 input
        line  10:       unnamed                 input
        line  11:       unnamed                 input
        line  12:       unnamed                 input
        line  13:       unnamed                 input
        line  14:       unnamed                 input
        line  15:       "AWR1_SPI_INT"          input
        line  16:       "AWR2_RESETn"           input
        line  17:       "AWR2_SPI_INT"          input
        line  18:       unnamed                 input
        line  19:       "AWR3_SPI_INT"          input
        line  20:       "AWR4_RESETn"           input
        line  21:       "AWR4_SPI_INT"          input
        line  22:       unnamed                 input
        line  23:       unnamed                 input
        line  24:       unnamed                 input
        line  25:       unnamed                 input
        line  26:       unnamed                 input
        line  27:       unnamed                 input
        line  28:       unnamed                 input
        line  29:       unnamed                 input
        line  30:       unnamed                 input
        line  31:       "AWR1_RESETn"           input
        line  32:       unnamed                 input
        line  33:       unnamed                 input
        line  34:       unnamed                 input
        line  35:       unnamed                 input
        line  36:       "AWR_SOP0"              input
        line  37:       unnamed                 input
        line  38:       unnamed                 input
        line  39:       unnamed                 input
        line  40:       unnamed                 input
        line  41:       unnamed                 input
        line  42:       unnamed                 input
        line  43:       unnamed                 input
        line  44:       unnamed                 input
        line  45:       unnamed                 input
        line  46:       unnamed                 input
        line  47:       unnamed                 input
        line  48:       unnamed                 input
        line  49:       unnamed                 input
        line  50:       unnamed                 input
        line  51:       unnamed                 input
        line  52:       unnamed                 input
        line  53:       unnamed                 input
        line  54:       unnamed                 input
        line  55:       unnamed                 input
        line  56:       unnamed                 input
        line  57:       unnamed                 input
        line  58:       unnamed                 input
        line  59:       unnamed                 input
        line  60:       unnamed                 input
        line  61:       unnamed                 input
        line  62:       unnamed                 input
        line  63:       unnamed                 input
        line  64:       unnamed                 input
        line  65:       unnamed                 input
        line  66:       unnamed                 input
        line  67:       unnamed                 input
        line  68:       unnamed                 input
        line  69:       "AWR3_RESETn"           input
        line  70:       unnamed                 output consumer=tlv71033
        line  71:       unnamed                 input
        line  72:       unnamed                 input
        line  73:       unnamed                 input
        line  74:       unnamed                 input
        line  75:       unnamed                 input
        line  76:       unnamed                 input
        line  77:       unnamed                 input
        line  78:       unnamed                 input
        line  79:       unnamed                 input
        line  80:       unnamed                 input
        line  81:       unnamed                 input
        line  82:       unnamed                 input
        line  83:       unnamed                 input
        line  84:       unnamed                 input
        line  85:       unnamed                 input
        line  86:       unnamed                 input

Things I've tried:

I don't quite understand it, but from reading online it seems like setting pins as outputs for padconfig != setting pins as outputs in the GPIO register space.

&main_pmx0 {

	///delete-property/ interrupts;
	
	gpio0_pins_default: gpio0-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x007c, PIN_INPUT, 7) /* (T23) GPMC0_CLK.GPIO0_31 	| AWR1_RESETn	*/
			J722S_IOPAD(0x003c, PIN_OUTPUT, 7) /* (R22) GPMC0_AD0.GPIO0_15 	| AWR1_SPI_INT */
			J722S_IOPAD(0x0040, PIN_INPUT, 7) /* (R23) GPMC0_AD1.GPIO0_16 	| AWR2_RESETn */
			J722S_IOPAD(0x0044, PIN_OUTPUT, 7) /* (R26) GPMC0_AD2.GPIO0_17 	| AWR2_SPI_INT */
			J722S_IOPAD(0x0118, PIN_INPUT, 7) /* (H26) MMC2_CLK.GPIO0_69  	| AWR3_RESETn */
			J722S_IOPAD(0x004c, PIN_OUTPUT, 7) /* (T25) GPMC0_AD4.GPIO0_19 	| AWR3_SPI_INT */
			J722S_IOPAD(0x0050, PIN_INPUT, 7) /* (T24) GPMC0_AD5.GPIO0_20 	| AWR4_RESETn */
			J722S_IOPAD(0x0054, PIN_OUTPUT, 7) /* (T21) GPMC0_AD6.GPIO0_21 	| AWR4_SPI_INT */
			
			J722S_IOPAD(0x0094, PIN_INPUT, 7) /* (P26) GPMC0_BE1n.GPIO0_36	| AWR_SOP0 */
		>;
	};

This had no effect.

I tried manually setting the GPIO_DIR registers to input.

root@j722s-evm:~# devmem2 0x00600038 w 0x002A7FFF
/dev/mem opened.
Memory mapped at address 0xffff992db000.
Read at address  0x00600038 (0xffff992db038): 0xFFFFFFFF
Write at address 0x00600038 (0xffff992db038): 0x002A7FFF, readback 0x002A7FFF
root@j722s-evm:~# devmem2 0x00600038                                                                                                                                                             root@j722s-evm:~# devmem2 0x00600038
/dev/mem opened.
Memory mapped at address 0xffffb6e4d000.
Read at address  0x00600038 (0xffffb6e4d038): 0x002A7FFF

gpioinfo still shows all of them are inputs.

root@j722s-evm:~# gpioinfo -c gpiochip2
gpiochip2 - 87 lines:
        line   0:       unnamed                 input
        line   1:       unnamed                 input
        line   2:       unnamed                 input
        line   3:       unnamed                 input
        line   4:       unnamed                 input
        line   5:       unnamed                 input
        line   6:       unnamed                 input
        line   7:       unnamed                 input
        line   8:       unnamed                 input
        line   9:       unnamed                 input
        line  10:       unnamed                 input
        line  11:       unnamed                 input
        line  12:       unnamed                 input
        line  13:       unnamed                 input
        line  14:       unnamed                 input
        line  15:       "AWR1_SPI_INT"          input
        line  16:       "AWR2_RESETn"           input
        line  17:       "AWR2_SPI_INT"          input
        line  18:       unnamed                 input
        line  19:       "AWR3_SPI_INT"          input
        line  20:       "AWR4_RESETn"           input
        line  21:       "AWR4_SPI_INT"          input
        line  22:       unnamed                 input
        line  23:       unnamed                 input
        line  24:       unnamed                 input
        line  25:       unnamed                 input
        line  26:       unnamed                 input
        line  27:       unnamed                 input
        line  28:       unnamed                 input
        line  29:       unnamed                 input
        line  30:       unnamed                 input
        line  31:       "AWR1_RESETn"           input
        line  32:       unnamed                 input
        line  33:       unnamed                 input
        line  34:       unnamed                 input
        line  35:       unnamed                 input
        line  36:       "AWR_SOP0"              input
        line  37:       unnamed                 input
        line  38:       unnamed                 input
        line  39:       unnamed                 input
        line  40:       unnamed                 input
        line  41:       unnamed                 input
        line  42:       unnamed                 input
        line  43:       unnamed                 input
        line  44:       unnamed                 input
        line  45:       unnamed                 input
        line  46:       unnamed                 input
        line  47:       unnamed                 input
        line  48:       unnamed                 input
        line  49:       unnamed                 input
        line  50:       unnamed                 input
        line  51:       unnamed                 input
        line  52:       unnamed                 input
        line  53:       unnamed                 input
        line  54:       unnamed                 input
        line  55:       unnamed                 input
        line  56:       unnamed                 input
        line  57:       unnamed                 input
        line  58:       unnamed                 input
        line  59:       unnamed                 input
        line  60:       unnamed                 input
        line  61:       unnamed                 input
        line  62:       unnamed                 input
        line  63:       unnamed                 input
        line  64:       unnamed                 input
        line  65:       unnamed                 input
        line  66:       unnamed                 input
        line  67:       unnamed                 input
        line  68:       unnamed                 input
        line  69:       "AWR3_RESETn"           input
        line  70:       unnamed                 output consumer=tlv71033
        line  71:       unnamed                 input
        line  72:       unnamed                 input
        line  73:       unnamed                 input
        line  74:       unnamed                 input
        line  75:       unnamed                 input
        line  76:       unnamed                 input
        line  77:       unnamed                 input
        line  78:       unnamed                 input
        line  79:       unnamed                 input
        line  80:       unnamed                 input
        line  81:       unnamed                 input
        line  82:       unnamed                 input
        line  83:       unnamed                 input
        line  84:       unnamed                 input
        line  85:       unnamed                 input
        line  86:       unnamed                 input

0 Keerthy J 4 months ago in reply to Jin Lee

TI__Guru**** 151940 points

Hi,

I will reproduce at my end today and come back to you by early next week.

Thanks,

Keerthy

0 Jin Lee 4 months ago in reply to Keerthy J

TI__Intellectual 1471 points

Hi Keerthy,

Thank you, looking forward to the results.

Also, I implemented the same gpio_test as described in the FAQ on the SK-TDA4VM and was able to successfully test the interrupt (GPIO0_52):

root@tda4vm-sk:/opt/edgeai-gst-apps# cat /proc/interrupts 
           CPU0       CPU1       
 11:       4486       4254     GICv3  30 Level     arch_timer
 14:          0          0     GICv3 804 Edge      arm-smmu-v3-evtq
 15:          0          0     GICv3 800 Edge      arm-smmu-v3-gerror
 16:          0          0     GICv3  23 Level     arm-pmu
 17:       2630          0     GICv3  69 Level     32c00000.mailbox thr_011
 31:       7334          0     GICv3 928 Level     42120000.i2c
 32:          2          0     GICv3 232 Level     2000000.i2c
 33:          0          0     GICv3 233 Level     2010000.i2c
 34:          2          0     GICv3 235 Level     2030000.i2c
 35:          0          0     GICv3 237 Level     2050000.i2c
 36:          0          0  MSI-INTA 15401056 Level     46000000.ethernet-tx0
 37:          0          0  MSI-INTA 15401057 Level     46000000.ethernet-tx1
 38:          0          0  MSI-INTA 15401058 Level     46000000.ethernet-tx2
 39:          0          0  MSI-INTA 15401059 Level     46000000.ethernet-tx3
 40:          0          0  MSI-INTA 15401060 Level     46000000.ethernet-tx4
 41:          0          0  MSI-INTA 15401061 Level     46000000.ethernet-tx5
 42:          0          0  MSI-INTA 15401062 Level     46000000.ethernet-tx6
 43:          0          0  MSI-INTA 15401063 Level     46000000.ethernet-tx7
 45:          0          0  MSI-INTA 15401065 Level     46000000.ethernet
 56:          0          0  MSI-INTA 13828536 Level     31150000.dma-controller chan0
 57:          0          0  MSI-INTA 13828537 Level     31150000.dma-controller chan1
 58:          0          0  MSI-INTA 13828538 Level     31150000.dma-controller chan2
206:          0          0     GICv3 878 Level     40a00000.serial
207:        839          0     GICv3 224 Level     2800000.serial
208:          0          0     GICv3 225 Level     2810000.serial
209:          0          0     GICv3 890 Level     46000000.ethernet
210:          0          0      INTR 391 Level     310d0000.cpts
211:          3          0      INTR 436 Level     mbox-mcu-r5fss0-core0
212:          6          0      INTR 432 Level     mbox-main-r5fss0-core0, mbox-main-r5fss0-core1
214:          7          0      INTR 424 Level     mbox-c66-0, mbox-c66-1
215:          4          0      INTR 420 Level     mbox-c71-0
229:          1          0      GPIO   7 Edge    -davinci_gpio  tps6594-0-0x48, tps6594-0-0x4c
274:          0          0      GPIO  52 Edge    -davinci_gpio  key-gpio
306:          0          0  tps6594-0-0x48   0 Edge      buck1_ov
307:          0          0  tps6594-0-0x48   1 Edge      buck1_uv
308:          0          0  tps6594-0-0x48   2 Edge      buck1_sc
309:          0          0  tps6594-0-0x48   3 Edge      buck1_ilim
310:          0          0  tps6594-0-0x48   4 Edge      buck2_ov
311:          0          0  tps6594-0-0x48   5 Edge      buck2_uv
312:          0          0  tps6594-0-0x48   6 Edge      buck2_sc
313:          0          0  tps6594-0-0x48   7 Edge      buck2_ilim
314:          0          0  tps6594-0-0x48   8 Edge      buck3_ov
315:          0          0  tps6594-0-0x48   9 Edge      buck3_uv
316:          0          0  tps6594-0-0x48  10 Edge      buck3_sc
317:          0          0  tps6594-0-0x48  11 Edge      buck3_ilim
318:          0          0  tps6594-0-0x48  12 Edge      buck4_ov
319:          0          0  tps6594-0-0x48  13 Edge      buck4_uv
320:          0          0  tps6594-0-0x48  14 Edge      buck4_sc
321:          0          0  tps6594-0-0x48  15 Edge      buck4_ilim
322:          0          0  tps6594-0-0x48  16 Edge      buck5_ov
323:          0          0  tps6594-0-0x48  17 Edge      buck5_uv
324:          0          0  tps6594-0-0x48  18 Edge      buck5_sc
325:          0          0  tps6594-0-0x48  19 Edge      buck5_ilim
326:          0          0  tps6594-0-0x48  20 Edge      ldo1_ov
327:          0          0  tps6594-0-0x48  21 Edge      ldo1_uv
328:          0          0  tps6594-0-0x48  22 Edge      ldo1_sc
329:          0          0  tps6594-0-0x48  23 Edge      ldo1_ilim
330:          0          0  tps6594-0-0x48  24 Edge      ldo2_ov
331:          0          0  tps6594-0-0x48  25 Edge      ldo2_uv
332:          0          0  tps6594-0-0x48  26 Edge      ldo2_sc
333:          0          0  tps6594-0-0x48  27 Edge      ldo2_ilim
334:          0          0  tps6594-0-0x48  28 Edge      ldo3_ov
335:          0          0  tps6594-0-0x48  29 Edge      ldo3_uv
336:          0          0  tps6594-0-0x48  30 Edge      ldo3_sc
337:          0          0  tps6594-0-0x48  31 Edge      ldo3_ilim
338:          0          0  tps6594-0-0x48  32 Edge      ldo4_ov
339:          0          0  tps6594-0-0x48  33 Edge      ldo4_uv
340:          0          0  tps6594-0-0x48  34 Edge      ldo4_sc
341:          0          0  tps6594-0-0x48  35 Edge      ldo4_ilim
342:          0          0  tps6594-0-0x48  36 Edge      vcca_ov
343:          0          0  tps6594-0-0x48  37 Edge      vcca_uv
361:          0          0  tps6594-0-0x48  55 Edge      npwron_start
362:          0          0  tps6594-0-0x48  56 Edge      enable
363:          0          0  tps6594-0-0x48  57 Edge      fsd
364:          0          0  tps6594-0-0x48  58 Edge      soft_reboot
365:          0          0  tps6594-0-0x48  59 Edge      bist_pass
366:          0          0  tps6594-0-0x48  60 Edge      ext_clk
367:          0          0  tps6594-0-0x48  61 Edge      twarn
368:          0          0  tps6594-0-0x48  62 Edge      tsd_ord
369:          0          0  tps6594-0-0x48  63 Edge      bist_fail
370:          0          0  tps6594-0-0x48  64 Edge      reg_crc_err
371:          0          0  tps6594-0-0x48  65 Edge      recov_cnt
372:          0          0  tps6594-0-0x48  66 Edge      spmi_err
373:          0          0  tps6594-0-0x48  67 Edge      npwron_long
374:          0          0  tps6594-0-0x48  68 Edge      nint_readback
375:          0          0  tps6594-0-0x48  69 Edge      nrstout_readback
376:          0          0  tps6594-0-0x48  70 Edge      tsd_imm
377:          0          0  tps6594-0-0x48  71 Edge      vcca_ovp
378:          0          0  tps6594-0-0x48  72 Edge      pfsm_err
379:          0          0  tps6594-0-0x48  73 Edge      imm_shutdown
380:          0          0  tps6594-0-0x48  74 Edge      ord_shutdown
381:          0          0  tps6594-0-0x48  75 Edge      mcu_pwr_err
382:          0          0  tps6594-0-0x48  76 Edge      soc_pwr_err
383:          0          0  tps6594-0-0x48  77 Edge      comm_frm_err
384:          0          0  tps6594-0-0x48  78 Edge      comm_crc_err
385:          0          0  tps6594-0-0x48  79 Edge      comm_adr_err
386:          0          0  tps6594-0-0x48  82 Edge      en_drv_readback
387:          0          0  tps6594-0-0x48  83 Edge      nrstout_soc_readback
388:          0          0  tps6594-0-0x48  84 Edge      esm_soc_pin
389:          0          0  tps6594-0-0x48  85 Edge      esm_soc_fail
390:          0          0  tps6594-0-0x48  86 Edge      esm_soc_rst
392:          0          0  tps6594-0-0x48  88 Edge      alarm
394:          0          0  tps6594-0-0x4c   0 Edge      buck1_ov
395:          0          0  tps6594-0-0x4c   1 Edge      buck1_uv
396:          0          0  tps6594-0-0x4c   2 Edge      buck1_sc
397:          0          0  tps6594-0-0x4c   3 Edge      buck1_ilim
398:          0          0  tps6594-0-0x4c   4 Edge      buck2_ov
399:          0          0  tps6594-0-0x4c   5 Edge      buck2_uv
400:          0          0  tps6594-0-0x4c   6 Edge      buck2_sc
401:          0          0  tps6594-0-0x4c   7 Edge      buck2_ilim
402:          0          0  tps6594-0-0x4c   8 Edge      buck3_ov
403:          0          0  tps6594-0-0x4c   9 Edge      buck3_uv
404:          0          0  tps6594-0-0x4c  10 Edge      buck3_sc
405:          0          0  tps6594-0-0x4c  11 Edge      buck3_ilim
406:          0          0  tps6594-0-0x4c  12 Edge      buck4_ov
407:          0          0  tps6594-0-0x4c  13 Edge      buck4_uv
408:          0          0  tps6594-0-0x4c  14 Edge      buck4_sc
409:          0          0  tps6594-0-0x4c  15 Edge      buck4_ilim
410:          0          0  tps6594-0-0x4c  16 Edge      buck5_ov
411:          0          0  tps6594-0-0x4c  17 Edge      buck5_uv
412:          0          0  tps6594-0-0x4c  18 Edge      buck5_sc
413:          0          0  tps6594-0-0x4c  19 Edge      buck5_ilim
414:          0          0  tps6594-0-0x4c  20 Edge      ldo1_ov
415:          0          1  tps6594-0-0x4c  21 Edge      ldo1_uv
416:          0          0  tps6594-0-0x4c  22 Edge      ldo1_sc
417:          0          0  tps6594-0-0x4c  23 Edge      ldo1_ilim
418:          0          0  tps6594-0-0x4c  24 Edge      ldo2_ov
419:          0          0  tps6594-0-0x4c  25 Edge      ldo2_uv
420:          0          0  tps6594-0-0x4c  26 Edge      ldo2_sc
421:          0          0  tps6594-0-0x4c  27 Edge      ldo2_ilim
422:          0          0  tps6594-0-0x4c  28 Edge      ldo3_ov
423:          0          0  tps6594-0-0x4c  29 Edge      ldo3_uv
424:          0          0  tps6594-0-0x4c  30 Edge      ldo3_sc
425:          0          0  tps6594-0-0x4c  31 Edge      ldo3_ilim
426:          0          0  tps6594-0-0x4c  32 Edge      ldo4_ov
427:          0          0  tps6594-0-0x4c  33 Edge      ldo4_uv
428:          0          0  tps6594-0-0x4c  34 Edge      ldo4_sc
429:          0          0  tps6594-0-0x4c  35 Edge      ldo4_ilim
430:          0          0  tps6594-0-0x4c  36 Edge      vcca_ov
431:          0          0  tps6594-0-0x4c  37 Edge      vcca_uv
449:          0          0  tps6594-0-0x4c  55 Edge      npwron_start
450:          0          0  tps6594-0-0x4c  56 Edge      enable
451:          0          0  tps6594-0-0x4c  57 Edge      fsd
452:          0          0  tps6594-0-0x4c  58 Edge      soft_reboot
453:          0          0  tps6594-0-0x4c  59 Edge      bist_pass
454:          0          0  tps6594-0-0x4c  60 Edge      ext_clk
455:          0          0  tps6594-0-0x4c  61 Edge      twarn
456:          0          0  tps6594-0-0x4c  62 Edge      tsd_ord
457:          0          0  tps6594-0-0x4c  63 Edge      bist_fail
458:          0          0  tps6594-0-0x4c  64 Edge      reg_crc_err
459:          0          0  tps6594-0-0x4c  65 Edge      recov_cnt
460:          0          0  tps6594-0-0x4c  66 Edge      spmi_err
461:          0          0  tps6594-0-0x4c  67 Edge      npwron_long
462:          0          0  tps6594-0-0x4c  68 Edge      nint_readback
463:          0          0  tps6594-0-0x4c  69 Edge      nrstout_readback
464:          0          0  tps6594-0-0x4c  70 Edge      tsd_imm
465:          0          0  tps6594-0-0x4c  71 Edge      vcca_ovp
466:          0          0  tps6594-0-0x4c  72 Edge      pfsm_err
467:          0          0  tps6594-0-0x4c  73 Edge      imm_shutdown
468:          0          0  tps6594-0-0x4c  74 Edge      ord_shutdown
469:          0          0  tps6594-0-0x4c  75 Edge      mcu_pwr_err
470:          0          0  tps6594-0-0x4c  76 Edge      soc_pwr_err
471:          0          0  tps6594-0-0x4c  77 Edge      comm_frm_err
472:          0          0  tps6594-0-0x4c  78 Edge      comm_crc_err
473:          0          0  tps6594-0-0x4c  79 Edge      comm_adr_err
474:          0          0  tps6594-0-0x4c  82 Edge      en_drv_readback
475:          0          0  tps6594-0-0x4c  83 Edge      nrstout_soc_readback
476:          0          0  tps6594-0-0x4c  84 Edge      esm_soc_pin
477:          0          0  tps6594-0-0x4c  85 Edge      esm_soc_fail
478:          0          0  tps6594-0-0x4c  86 Edge      esm_soc_rst
639:      14122          0     GICv3  36 Level     mmc1
643:          0          0     GICv3  43 Level     4e10000.rng
644:          0          0     GICv3 646 Level     mhdp8546
645:          0          0     GICv3 213 Level     vxe-enc
646:          0          0     GICv3 212 Level     vxd-dec
663:        144          0     GICv3 136 Level     xhci-hcd:usb1
665:          0          0     GICv3 153 Level     6400000.usb
IPI0:      1174       2652       Rescheduling interrupts
IPI1:      2569       7221       Function call interrupts
IPI2:         0          0       CPU stop interrupts
IPI3:         0          0       CPU stop (for crash dump) interrupts
IPI4:         0          0       Timer broadcast interrupts
IPI5:         0          0       IRQ work interrupts
IPI6:         0          0       CPU wake-up interrupts
Err:          0

root@tda4vm-sk:/opt/edgeai-gst-apps# devmem2 0x00600038
/dev/mem opened.
Memory mapped at address 0xffff984fb000.
Read at address  0x00600038 (0xffff984fb038): 0xFFFFFFFF
root@tda4vm-sk:/opt/edgeai-gst-apps# devmem2 0x00600038 w 0xFFEFFFFF                                                                                                                                        
/dev/mem opened.
Memory mapped at address 0xffff9e188000.
Read at address  0x00600038 (0xffff9e188038): 0xFFBFFFFF
Write at address 0x00600038 (0xffff9e188038): 0xFFEFFFFF, readback 0xFFEFFFFF
root@tda4vm-sk:/opt/edgeai-gst-apps# gpioset -c gpiochip0 52=1                                                                                                                                              
[  422.689799] test_irq: irq 274, val=0

The only difference in implementation on the J722S is the GPIOs being tested (wkup_gpio 52 vs main_gpio0 15).

Thank you,

Jin

0 Keerthy J 4 months ago in reply to Jin Lee

TI__Guru**** 151940 points

Hi Jin,

Thanks for testing. Any chance you can try any WKUP_GPIO instance on J722s?

- Keerthy

0 Jin Lee 4 months ago in reply to Keerthy J

TI__Intellectual 1471 points

Hi Keerthy,

The issue seems resolved; I had to define the nodes individually.

Thanks for your help!

0 Keerthy J 4 months ago in reply to Jin Lee

TI__Guru**** 151940 points

Hi,

Please share the working patch for our future reference.

Thanks,

Keerthy

0 Jin Lee 4 months ago in reply to Keerthy J

TI__Intellectual 1471 points

Hi Keerthy,

Actually, I'm running into a problem when trying to implement multiple interrupts on the J722S. I only have an SK-TDA4VM at the moment, but the question is the same for J722S.

Am I correctly defining both WKUP_GPIO0_52 and WKUP_GPIO0_54 as GPIO interrupts on the TDA4VM?

gpio_test: gpio_test {
	compatible = "ti, gpio_test";
	interrupt-parent = <&wkup_gpio0>;
	interrupts = <52 IRQ_TYPE_EDGE_FALLING>, <54 IRQ_TYPE_EDGE_FALLING>;
};

&wkup_pmx0 {
	test_key1_pins_default: test-key1-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x90, PIN_INPUT, 7) /* (E27) WKUP_GPIO0_52 */
		>;
	};

	test_key2_pins_default: test-key2-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */		
		>;
	};
...

&wkup_gpio0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&test_key1_pins_default &test_key2_pins_default>;
};

Only GPIO0_52 interrupt is visible on the kernel. How can implement multiple GPIO interrupts?

root@tda4vm-sk:/opt/edgeai-gst-apps# cat /proc/interrupts | grep gpio* 
229:          1          0      GPIO   7 Edge    -davinci_gpio  tps6594-0-0x48, tps6594-0-0x4c
274:          0          0      GPIO  52 Edge    -davinci_gpio  key-gpio

Thank you,

Jin

+1 Keerthy J 4 months ago in reply to Jin Lee

TI__Guru**** 151940 points

Jin,

No. The original patch was intended to just enable one pin. So you will have to do more changes.
Can do 1 at a time to check both interrupts are working.

That was only a reference example.

- Keerthy

0 Jin Lee 4 months ago in reply to Keerthy J

TI__Intellectual 1471 points

Uploading working patch for future reference.

For context, this patch is intended to test the following J722S SPI and GPIO connections to the MMWCAS-RF-EVM:

MCU_SPI0: AWR1_SPI
MCU_SPI1: AWR2_SPI
SPI0: AWR3_SPI
SPI2: AWR4_SPI

GPIO0_31, GPIO0_16, GPIO0_69, GPIO0_20: AWR#_RESETn
GPIO0_15, GPIO0_17, GPIO0_19, GPIO0_21: AWR#_SPI_INT

mmwavcas-rf-evm_ctrls.patch

How I tested:

(Confirmed that BINTEN registers are set.)

# set direction of AWR#_SPI_INT GPIOs to output (WR GPIO_DIR01)
root@j722s-evm:~# devmem2 0x00600010 w 0xFFD757FF
/dev/mem opened.
Memory mapped at address 0xffffaa850000.
Read at address  0x00600010 (0xffffaa850010): 0xFFFFFFFF
Write at address 0x00600010 (0xffffaa850010): 0xFFD757FF, readback 0xFFD757FF

# set SOP mode 4 for AWR2243 SPI control
root@j722s-evm:~# gpioset -c gpiochip2 36=1
^C
root@j722s-evm:~# gpioset -c gpiochip3 10=0 9=0
^C

# Toggle nRESET line for each AWR2243, which sends interrupt pulse in response
# AWR1
root@j722s-evm:~# gpioset -c gpiochip2 31=0
^C
root@j722s-evm:~# gpioset -c gpiochip2 31=1 
[ 1028.670246] test_irq: irq 340, val=0
[ 1028.674050] test_irq: irq 340, val=0
^C
# AWR2
root@j722s-evm:~# gpioset -c gpiochip2 16=0
^C
root@j722s-evm:~# gpioset -c gpiochip2 16=1
[ 1043.215204] test_irq: irq 342, val=0
[ 1043.219006] test_irq: irq 342, val=0
^C
# AWR3
root@j722s-evm:~# gpioset -c gpiochip2 69=0
^C
root@j722s-evm:~# gpioset -c gpiochip2 69=1
[ 1050.546768] test_irq: irq 344, val=0
[ 1050.550583] test_irq: irq 344, val=0
^C
# AWR4
root@j722s-evm:~# gpioset -c gpiochip2 20=0
^C
root@j722s-evm:~# gpioset -c gpiochip2 20=1
[ 1060.181796] test_irq: irq 346, val=0
[ 1060.185636] test_irq: irq 346, val=0

*Trigger type was set for both rising and falling edge for test, but will only be for rising edge for application.

Processors

Processors forum

J722SXH01EVM: Enabling GPIO interrupts in PROCESSOR-SDK-LINUX-J722S