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J722SXH01EVM: Enabling GPIO interrupts in PROCESSOR-SDK-LINUX-J722S

Jin Lee
Intellectual 1952 points
Part Number: J722SXH01EVM
Other Parts Discussed in Thread: SK-TDA4VM, TDA4VM

Tool/software:

Hi, 

I am trying to enable interrupts for GPIO0_15, GPIO0_17, GPIO0_19, and GPIO0_21 on the TDA4AEN. 

Referring to this thread, https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1058595/faq-tda4vm-how-to-test-gpio-interrupts, I first created a gpio_test node in k3-j722s-evm.dts:

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...
vsys_io_1v2: regulator-vsys-io-1v2 {
compatible = "regulator-fixed";
regulator-name = "vsys_io_1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
gpio_test: gpio_test {
compatible = "ti,gpio_test";
interrupt-parent = <&main_gpio0>;
interrupts = <69 IRQ_TYPE_EDGE_FALLING>;
};
hdmi0: connector-hdmi {
...
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

&main_gpio:

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&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&gpio0_pins_default>;
status = "okay";
};
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
gpio0_pins_default:
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&main_pmx0 {
///delete-property/ interrupts;
gpio0_pins_default: gpio0-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x0118, PIN_INPUT, 7) /* (H26) MMC2_CLK.GPIO0_69 | AWR3_RESETn */
>;
};
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
However, the interrupt does not show up on the kernel:
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root@j722s-evm:~# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
11: 2987 3399 3207 3010 GICv3 30 Level arch_timer
14: 0 0 0 0 GICv3 130 Level pinctrl
15: 4 0 0 0 GICv3 108 Level mbox-r5-0
16: 4 0 0 0 GICv3 109 Level mbox-mcu-r5-0
19: 0 0 0 0 GICv3 23 Level arm-pmu
20: 1368 0 0 0 GICv3 66 Level 4d000000.mailbox thr_012
26: 0 0 0 0 GICv3 197 Level 2b200000.i2c
27: 52 0 0 0 GICv3 193 Level 20000000.i2c
28: 49 0 0 0 GICv3 194 Level 20010000.i2c
29: 4 0 0 0 GICv3 195 Level 20020000.i2c
30: 1962 0 0 0 MSI-INTA 1713152 Level 485c0100.dma-controller chan0
112: 9 2 0 0 MSI-INTA 1970707 Level 8000000.ethernet-tx0
120: 0 0 0 0 MSI-INTA 1970715 Level 8000000.ethernet-tx1
128: 0 0 0 0 MSI-INTA 1970723 Level 8000000.ethernet-tx2
136: 0 0 2 1 MSI-INTA 1970731 Level 8000000.ethernet-tx3
144: 4 0 0 0 MSI-INTA 1970739 Level 8000000.ethernet-tx4
152: 0 5 0 1 MSI-INTA 1970747 Level 8000000.ethernet-tx5
160: 0 0 2 0 MSI-INTA 1970755 Level 8000000.ethernet-tx6
168: 0 0 0 3 MSI-INTA 1970763 Level 8000000.ethernet-tx7
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
I tried with GPIO0_69 after getting the same failure with GPIO0_15, thinking maybe the I2C expander is the issue, but get the same results.
Could you advise on what I'm doing wrong and how to enable GPIO interrupts?
Things I've tried:
I'm able to create regular GPIOs and have tested their functionality w/ gpioset and a logic analyzer (J28 expansion header)

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root@j722s-evm:~# gpioinfo -c gpiochip2
gpiochip2 - 87 lines:
line 0: unnamed input
line 1: unnamed input
line 2: unnamed input
line 3: unnamed input
line 4: unnamed input
line 5: unnamed input
line 6: unnamed input
line 7: unnamed input
line 8: unnamed input
line 9: unnamed input
line 10: unnamed input
line 11: unnamed input
line 12: unnamed input
line 13: unnamed input
line 14: unnamed input
line 15: "AWR1_SPI_INT" input
line 16: "AWR2_RESETn" input
line 17: "AWR2_SPI_INT" input
line 18: unnamed input
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

k3-j722s-evm.dts:

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&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&gpio0_pins_default>;
gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "",
"", "", "", "AWR1_SPI_INT", "AWR2_RESETn", "AWR2_SPI_INT", "", "AWR3_SPI_INT", "AWR4_RESETn", "AWR4_SPI_INT", "", "",
"", "", "", "", "", "", "", "AWR1_RESETn", "", "", "", "",
"AWR_SOP0", "", "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "AWR3_RESETn", "", "";
status = "okay";
};
&main_gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&gpio1_pins_default>;
gpio-line-names = "", "", "", "", "", "", "", "", "", "AWR_SOP2", "AWR_SOP1", "",
"AWR_ERROR_OUTn";
status = "okay";
};
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

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&main_pmx0 {
///delete-property/ interrupts;
gpio0_pins_default: gpio0-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x007c, PIN_INPUT, 7) /* (T23) GPMC0_CLK.GPIO0_31 | AWR1_RESETn */
J722S_IOPAD(0x003c, PIN_INPUT, 7) /* (R22) GPMC0_AD0.GPIO0_15 | AWR1_SPI_INT */
J722S_IOPAD(0x0040, PIN_INPUT, 7) /* (R23) GPMC0_AD1.GPIO0_16 | AWR2_RESETn */
J722S_IOPAD(0x0044, PIN_INPUT, 7) /* (R26) GPMC0_AD2.GPIO0_17 | AWR2_SPI_INT */
J722S_IOPAD(0x0118, PIN_INPUT, 7) /* (H26) MMC2_CLK.GPIO0_69 | AWR3_RESETn */
J722S_IOPAD(0x004c, PIN_INPUT, 7) /* (T25) GPMC0_AD4.GPIO0_19 | AWR3_SPI_INT */
J722S_IOPAD(0x0050, PIN_INPUT, 7) /* (T24) GPMC0_AD5.GPIO0_20 | AWR4_RESETn */
J722S_IOPAD(0x0054, PIN_INPUT, 7) /* (T21) GPMC0_AD6.GPIO0_21 | AWR4_SPI_INT */
J722S_IOPAD(0x0094, PIN_INPUT, 7) /* (P26) GPMC0_BE1n.GPIO0_36 | AWR_SOP0 */
>;
};
gpio1_pins_default: gpio1-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x01a0, PIN_INPUT, 7) /* (F23) MCASP0_AXR0.GPIO1_10 | AWR_SOP1 */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

When I try adding interrupts in main_gpio0 in k3-am62p-main.dtsi, there is no change.
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main_gpio0: gpio@600000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x00 0x00600000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <190>, <191>, <192>,
<193>, <194>, <195>,
<15>, <17>, <19>, <21>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <92>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 77 0>;
clock-names = "gpio";
gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
<&main_pmx0 70 72 22>;
};
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Thank you,
Jin
  • 0
    TI__Guru**** 155270 points

    Hi,

    Jin Lee said:
    I am trying to enable interrupts for GPIO0_15, GPIO0_17, GPIO0_19, and GPIO0_21 on the TDA4AEN. 

    Can you read out the corresponding pinmux registers and check that they read 0x50007.

    The mode should be mode7 for GPIO and bit18 RX_ACTIVE should be set.

    Let us first confirm that pinmux is setup properly.

    - Keerthy

  • 0 in reply to Keerthy J
    TI__Intellectual 1952 points

    Hi Keerthy, 

    Confirming that the pinmux registers are set accordingly:

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    root@j722s-evm:~# devmem2 0x000F403C
    /dev/mem opened.
    Memory mapped at address 0xffff99525000.
    Read at address 0x000F403C (0xffff9952503c): 0x00050007
    root@j722s-evm:~# devmem2 0x00F4044
    /dev/mem opened.
    Memory mapped at address 0xffff9cf28000.
    Read at address 0x000F4044 (0xffff9cf28044): 0x00050007
    root@j722s-evm:~# devmem2 0x00F404C
    /dev/mem opened.
    Memory mapped at address 0xffffbb897000.
    Read at address 0x000F404C (0xffffbb89704c): 0x00050007
    root@j722s-evm:~# devmem2 0x00F4054
    /dev/mem opened.
    Memory mapped at address 0xffff89c01000.
    Read at address 0x000F4054 (0xffff89c01054): 0x00050007
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to Jin Lee
    TI__Intellectual 1952 points

    Hi Keerthy, 

    In addition, GPIO_BINTEN registers seem set to enable interrupts:

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    root@j722s-evm:~# devmem2 0x00600008
    /dev/mem opened.
    Memory mapped at address 0xffff9405e000.
    Read at address 0x00600008 (0xffff9405e008): 0x0000003F
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    However, GPIO_SET_FAL_TRIG45 shows that GPIO0_69 trigger is not set. only the io-expander (GPIO0_67).

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    root@j722s-evm:~# devmem2 0x00600080
    /dev/mem opened.
    Memory mapped at address 0xffffb2cc4000.
    Read at address 0x00600080 (0xffffb2cc4080): 0x00000008
    root@j722s-evm:~#
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to Jin Lee
    TI__Guru**** 155270 points

    Hi,

    Jin Lee said:
    Confirming that the pinmux registers are set accordingly:

    Thanks. They are looking correct.

    We have indirectly verified the GPIO interrupts via:

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    exp2: gpio@20 {
    compatible = "ti,tca6416";
    reg = <0x20>;
    gpio-controller;
    #gpio-cells = <2>;
    gpio-line-names = "DSI_Mux_SEL_2", "GPIO_eDP_ENABLE",
    "DP0_PWR_SW_EN", "GPIO_OLDI_RSTn",
    "GPIO_HDMI_RSTn", "HDMI_LS_OE",
    "", "",
    "DSI_GPIO0", "DSI_GPIO1",
    "DSI_EDID", "IO_eDP_IRQ",
    "OLDI_INT#", "HDMI_INTn",
    "", "";
    interrupt-parent = <&main_gpio0>;
    interrupts = <67 IRQ_TYPE_EDGE_FALLING>;
    interrupt-controller;
    #interrupt-cells = <2>;
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Jin Lee said:

    In addition, GPIO_BINTEN registers seem set to enable interrupts:

    Okay. Are the pins correctly set as output in the GPIO register space?

    Which exact pin are you looking for or you are trying to validate any GPIO for interrupts?

    - Keerthy

  • 0 in reply to Keerthy J
    TI__Intellectual 1952 points

    Hi Keerthy, 

    Which exact pin are you looking for or you are trying to validate any GPIO for interrupts?

    We are specifically trying to enable interrupts GPIO0_15, GPIO0_17, GPIO0_19, and GPIO0_21.

    Okay. Are the pins correctly set as output in the GPIO register space?

    It seems all the GPIOs are set as inputs except for GPIO0_70, used by tlv71033

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    root@j722s-evm:~# devmem2 0x00600010
    /dev/mem opened.
    Memory mapped at address 0xffff91ef2000.
    Read at address 0x00600010 (0xffff91ef2010): 0xFFFFFFFF
    root@j722s-evm:~# devmem2 0x00600038
    /dev/mem opened.
    Memory mapped at address 0xffffbd3e6000.
    Read at address 0x00600038 (0xffffbd3e6038): 0xFFFFFFFF
    root@j722s-evm:~# devmem2 0x00600060
    /dev/mem opened.
    Memory mapped at address 0xffffac7b3000.
    Read at address 0x00600060 (0xffffac7b3060): 0xFFFFFFBF
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

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    root@j722s-evm:~# gpioinfo -c gpiochip2
    gpiochip2 - 87 lines:
    line 0: unnamed input
    line 1: unnamed input
    line 2: unnamed input
    line 3: unnamed input
    line 4: unnamed input
    line 5: unnamed input
    line 6: unnamed input
    line 7: unnamed input
    line 8: unnamed input
    line 9: unnamed input
    line 10: unnamed input
    line 11: unnamed input
    line 12: unnamed input
    line 13: unnamed input
    line 14: unnamed input
    line 15: "AWR1_SPI_INT" input
    line 16: "AWR2_RESETn" input
    line 17: "AWR2_SPI_INT" input
    line 18: unnamed input
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Things I've tried:

    I don't quite understand it, but from reading online it seems like setting pins as outputs for padconfig != setting pins as outputs in the GPIO register space.

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    &main_pmx0 {
    ///delete-property/ interrupts;
    gpio0_pins_default: gpio0-default-pins {
    pinctrl-single,pins = <
    J722S_IOPAD(0x007c, PIN_INPUT, 7) /* (T23) GPMC0_CLK.GPIO0_31 | AWR1_RESETn */
    J722S_IOPAD(0x003c, PIN_OUTPUT, 7) /* (R22) GPMC0_AD0.GPIO0_15 | AWR1_SPI_INT */
    J722S_IOPAD(0x0040, PIN_INPUT, 7) /* (R23) GPMC0_AD1.GPIO0_16 | AWR2_RESETn */
    J722S_IOPAD(0x0044, PIN_OUTPUT, 7) /* (R26) GPMC0_AD2.GPIO0_17 | AWR2_SPI_INT */
    J722S_IOPAD(0x0118, PIN_INPUT, 7) /* (H26) MMC2_CLK.GPIO0_69 | AWR3_RESETn */
    J722S_IOPAD(0x004c, PIN_OUTPUT, 7) /* (T25) GPMC0_AD4.GPIO0_19 | AWR3_SPI_INT */
    J722S_IOPAD(0x0050, PIN_INPUT, 7) /* (T24) GPMC0_AD5.GPIO0_20 | AWR4_RESETn */
    J722S_IOPAD(0x0054, PIN_OUTPUT, 7) /* (T21) GPMC0_AD6.GPIO0_21 | AWR4_SPI_INT */
    J722S_IOPAD(0x0094, PIN_INPUT, 7) /* (P26) GPMC0_BE1n.GPIO0_36 | AWR_SOP0 */
    >;
    };
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     This had no effect.

    I tried manually setting the GPIO_DIR registers to input. 

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    root@j722s-evm:~# devmem2 0x00600038 w 0x002A7FFF
    /dev/mem opened.
    Memory mapped at address 0xffff992db000.
    Read at address 0x00600038 (0xffff992db038): 0xFFFFFFFF
    Write at address 0x00600038 (0xffff992db038): 0x002A7FFF, readback 0x002A7FFF
    root@j722s-evm:~# devmem2 0x00600038 root@j722s-evm:~# devmem2 0x00600038
    /dev/mem opened.
    Memory mapped at address 0xffffb6e4d000.
    Read at address 0x00600038 (0xffffb6e4d038): 0x002A7FFF
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    gpioinfo still shows all of them are inputs.

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    root@j722s-evm:~# gpioinfo -c gpiochip2
    gpiochip2 - 87 lines:
    line 0: unnamed input
    line 1: unnamed input
    line 2: unnamed input
    line 3: unnamed input
    line 4: unnamed input
    line 5: unnamed input
    line 6: unnamed input
    line 7: unnamed input
    line 8: unnamed input
    line 9: unnamed input
    line 10: unnamed input
    line 11: unnamed input
    line 12: unnamed input
    line 13: unnamed input
    line 14: unnamed input
    line 15: "AWR1_SPI_INT" input
    line 16: "AWR2_RESETn" input
    line 17: "AWR2_SPI_INT" input
    line 18: unnamed input
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to Jin Lee
    TI__Guru**** 155270 points

    Hi,

    I will reproduce at my end today and come back to you by early next week. 

    Thanks, 

    Keerthy 

  • 0 in reply to Keerthy J
    TI__Intellectual 1952 points

    Hi Keerthy,

    Thank you, looking forward to the results.

    Also, I implemented the same gpio_test as described in the FAQ on the SK-TDA4VM and was able to successfully test the interrupt (GPIO0_52):

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    root@tda4vm-sk:/opt/edgeai-gst-apps# cat /proc/interrupts
    CPU0 CPU1
    11: 4486 4254 GICv3 30 Level arch_timer
    14: 0 0 GICv3 804 Edge arm-smmu-v3-evtq
    15: 0 0 GICv3 800 Edge arm-smmu-v3-gerror
    16: 0 0 GICv3 23 Level arm-pmu
    17: 2630 0 GICv3 69 Level 32c00000.mailbox thr_011
    31: 7334 0 GICv3 928 Level 42120000.i2c
    32: 2 0 GICv3 232 Level 2000000.i2c
    33: 0 0 GICv3 233 Level 2010000.i2c
    34: 2 0 GICv3 235 Level 2030000.i2c
    35: 0 0 GICv3 237 Level 2050000.i2c
    36: 0 0 MSI-INTA 15401056 Level 46000000.ethernet-tx0
    37: 0 0 MSI-INTA 15401057 Level 46000000.ethernet-tx1
    38: 0 0 MSI-INTA 15401058 Level 46000000.ethernet-tx2
    39: 0 0 MSI-INTA 15401059 Level 46000000.ethernet-tx3
    40: 0 0 MSI-INTA 15401060 Level 46000000.ethernet-tx4
    41: 0 0 MSI-INTA 15401061 Level 46000000.ethernet-tx5
    42: 0 0 MSI-INTA 15401062 Level 46000000.ethernet-tx6
    43: 0 0 MSI-INTA 15401063 Level 46000000.ethernet-tx7
    45: 0 0 MSI-INTA 15401065 Level 46000000.ethernet
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

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    root@tda4vm-sk:/opt/edgeai-gst-apps# devmem2 0x00600038
    /dev/mem opened.
    Memory mapped at address 0xffff984fb000.
    Read at address 0x00600038 (0xffff984fb038): 0xFFFFFFFF
    root@tda4vm-sk:/opt/edgeai-gst-apps# devmem2 0x00600038 w 0xFFEFFFFF
    /dev/mem opened.
    Memory mapped at address 0xffff9e188000.
    Read at address 0x00600038 (0xffff9e188038): 0xFFBFFFFF
    Write at address 0x00600038 (0xffff9e188038): 0xFFEFFFFF, readback 0xFFEFFFFF
    root@tda4vm-sk:/opt/edgeai-gst-apps# gpioset -c gpiochip0 52=1
    [ 422.689799] test_irq: irq 274, val=0
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    The only difference in implementation on the J722S is the GPIOs being tested (wkup_gpio 52 vs main_gpio0 15).

    Thank you,

    Jin

  • 0 in reply to Jin Lee
    TI__Guru**** 155270 points

    Hi Jin,

    Thanks for testing. Any chance you can try any WKUP_GPIO instance on J722s?

    - Keerthy

  • 0 in reply to Keerthy J
    TI__Intellectual 1952 points

    Hi Keerthy, 

    The issue seems resolved; I had to define the nodes individually. 

    Thanks for your help!

  • 0 in reply to Jin Lee
    TI__Guru**** 155270 points

    Hi,

    Please share the working patch for our future reference.

    Thanks, 

    Keerthy 

  • 0 in reply to Keerthy J
    TI__Intellectual 1952 points

    Hi Keerthy,

    Actually, I'm running into a problem when trying to implement multiple interrupts on the J722S. I only have an SK-TDA4VM at the moment, but the question is the same for J722S.

    Am I correctly defining both WKUP_GPIO0_52 and WKUP_GPIO0_54 as GPIO interrupts on the TDA4VM?

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    gpio_test: gpio_test {
    compatible = "ti, gpio_test";
    interrupt-parent = <&wkup_gpio0>;
    interrupts = <52 IRQ_TYPE_EDGE_FALLING>, <54 IRQ_TYPE_EDGE_FALLING>;
    };
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

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    &wkup_pmx0 {
    test_key1_pins_default: test-key1-pins-default {
    pinctrl-single,pins = <
    J721E_WKUP_IOPAD(0x90, PIN_INPUT, 7) /* (E27) WKUP_GPIO0_52 */
    >;
    };
    test_key2_pins_default: test-key2-pins-default {
    pinctrl-single,pins = <
    J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
    >;
    };
    ...
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

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    &wkup_gpio0 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&test_key1_pins_default &test_key2_pins_default>;
    };
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Only GPIO0_52 interrupt is visible on the kernel. How can implement multiple GPIO interrupts?

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    root@tda4vm-sk:/opt/edgeai-gst-apps# cat /proc/interrupts | grep gpio*
    229: 1 0 GPIO 7 Edge -davinci_gpio tps6594-0-0x48, tps6594-0-0x4c
    274: 0 0 GPIO 52 Edge -davinci_gpio key-gpio
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    Thank you,

    Jin

  • +1 in reply to Jin Lee
    TI__Guru**** 155270 points

    Jin,

    No. The original patch was intended to just enable one pin. So you will have to do more changes.
    Can do 1 at a time to check both interrupts are working.

    That was only a reference example.

    - Keerthy

  • 0 in reply to Keerthy J
    TI__Intellectual 1952 points

    Uploading working patch for future reference.

    For context, this patch is intended to test the following J722S SPI and GPIO connections to the MMWCAS-RF-EVM:

    • MCU_SPI0: AWR1_SPI
    • MCU_SPI1: AWR2_SPI
    • SPI0: AWR3_SPI
    • SPI2: AWR4_SPI

    • GPIO0_31, GPIO0_16, GPIO0_69, GPIO0_20: AWR#_RESETn
    • GPIO0_15, GPIO0_17, GPIO0_19, GPIO0_21: AWR#_SPI_INT

    mmwavcas-rf-evm_ctrls.patch

    How I tested:

    (Confirmed that BINTEN registers are set.) 

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    # set direction of AWR#_SPI_INT GPIOs to output (WR GPIO_DIR01)
    root@j722s-evm:~# devmem2 0x00600010 w 0xFFD757FF
    /dev/mem opened.
    Memory mapped at address 0xffffaa850000.
    Read at address 0x00600010 (0xffffaa850010): 0xFFFFFFFF
    Write at address 0x00600010 (0xffffaa850010): 0xFFD757FF, readback 0xFFD757FF
    # set SOP mode 4 for AWR2243 SPI control
    root@j722s-evm:~# gpioset -c gpiochip2 36=1
    ^C
    root@j722s-evm:~# gpioset -c gpiochip3 10=0 9=0
    ^C
    # Toggle nRESET line for each AWR2243, which sends interrupt pulse in response
    # AWR1
    root@j722s-evm:~# gpioset -c gpiochip2 31=0
    ^C
    root@j722s-evm:~# gpioset -c gpiochip2 31=1
    [ 1028.670246] test_irq: irq 340, val=0
    [ 1028.674050] test_irq: irq 340, val=0
    ^C
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    *Trigger type was set for both rising and falling edge for test, but will only be for rising edge for application.