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Tool/software:
Hi,
I'm working on enabling SPI on the J722SXH01EVM, using the below app note and E2E threads for the TDA4VM as reference:
1. I added the device tree node and the corresponding pinmux node as shown below:
Pinmux node (k3-j722s-evm.dts, line 272):
// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the J722S EVM * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ * * Schematics: https://www.ti.com/lit/zip/sprr495 */ /dts-v1/; #include <dt-bindings/net/ti-dp83867.h> #include <dt-bindings/phy/phy.h> #include "k3-j722s.dtsi" #include "k3-serdes.h" / { compatible = "ti,j722s-evm", "ti,j722s"; model = "Texas Instruments J722S EVM"; aliases { serial0 = &wkup_uart0; serial2 = &main_uart0; serial3 = &main_uart5; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { stdout-path = &main_uart0; }; memory@80000000 { /* 8G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>, <0x00000008 0x80000000 0x00000001 0x80000000>; device_type = "memory"; bootph-all; }; reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; /* global cma region */ linux,cma { compatible = "shared-dma-pool"; reusable; size = <0x00 0x38000000>; linux,cma-default; }; secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; no-map; }; secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; no-map; }; wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; c7x_0_memory_region: c7x-memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4000000 0x00 0x100000>; no-map; }; c7x_1_memory_region: c7x-memory@a4100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; rtos_ipc_memory_region: ipc-memories@a5000000 { reg = <0x00 0xa5000000 0x00 0x1c00000>; alignment = <0x1000>; no-map; }; }; vmain_pd: regulator-0 { /* TPS65988 PD CONTROLLER OUTPUT */ compatible = "regulator-fixed"; regulator-name = "vmain_pd"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; regulator-boot-on; bootph-all; }; vsys_5v0: regulator-vsys5v0 { /* Output of LM5140 */ compatible = "regulator-fixed"; regulator-name = "vsys_5v0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; vin-supply = <&vmain_pd>; regulator-always-on; regulator-boot-on; }; vdd_mmc1: regulator-mmc1 { /* TPS22918DBVR */ compatible = "regulator-fixed"; regulator-name = "vdd_mmc1"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; enable-active-high; gpio = <&exp1 15 GPIO_ACTIVE_HIGH>; bootph-all; }; vdd_sd_dv: regulator-TLV71033 { compatible = "regulator-gpio"; regulator-name = "tlv71033"; pinctrl-names = "default"; pinctrl-0 = <&vdd_sd_dv_pins_default>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; vin-supply = <&vsys_5v0>; gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>; states = <1800000 0x0>, <3300000 0x1>; }; vcc_3v3_aud: regulator-vcc3v3 { /* Output of LM5140 */ compatible = "regulator-fixed"; regulator-name = "vcc_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; vsys_io_1v8: regulator-vsys-io-1v8 { compatible = "regulator-fixed"; regulator-name = "vsys_io_1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; vsys_io_1v2: regulator-vsys-io-1v2 { compatible = "regulator-fixed"; regulator-name = "vsys_io_1v2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; regulator-boot-on; }; hdmi0: connector-hdmi { compatible = "hdmi-connector"; label = "hdmi"; type = "a"; port { hdmi_connector_in: endpoint { remote-endpoint = <&sii9022_out>; }; }; }; transceiver0: can-phy0 { compatible = "ti,tcan1042"; #phy-cells = <0>; max-bitrate = <5000000>; pinctrl-names = "default"; pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; standby-gpios = <&mcu_gpio0 12 GPIO_ACTIVE_HIGH>; }; transceiver1: can-phy1 { compatible = "ti,tcan1042"; #phy-cells = <0>; max-bitrate = <5000000>; }; transceiver2: can-phy2 { compatible = "ti,tcan1042"; #phy-cells = <0>; max-bitrate = <5000000>; standby-gpios = <&exp1 17 GPIO_ACTIVE_HIGH>; }; codec_audio: sound { compatible = "simple-audio-card"; simple-audio-card,name = "J722S-EVM"; simple-audio-card,widgets = "Headphone", "Headphone Jack", "Line", "Line In", "Microphone", "Microphone Jack"; simple-audio-card,routing = "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT", "LINE1L", "Line In", "LINE1R", "Line In", "MIC3R", "Microphone Jack", "Microphone Jack", "Mic Bias"; simple-audio-card,format = "dsp_b"; simple-audio-card,bitclock-master = <&sound_master>; simple-audio-card,frame-master = <&sound_master>; simple-audio-card,bitclock-inversion; simple-audio-card,cpu { sound-dai = <&mcasp1>; }; sound_master: simple-audio-card,codec { sound-dai = <&tlv320aic3106>; clocks = <&audio_refclk1>; }; }; }; &main_pmx0 { /delete-property/ interrupts; main_spi0_pins_default: main-spi0-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x01bc, PIN_INPUT, 0) /* (D20) SPI0_CLK */ J722S_IOPAD(0x01b4, PIN_INPUT, 0) /* (B20) SPI0_CS0 */ J722S_IOPAD(0x01b8, PIN_INPUT, 0) /* (C20) SPI0_CS1 */ J722S_IOPAD(0x01d0, PIN_INPUT, 1) /* (E22) SPI0_CS2 */ J722S_IOPAD(0x01d4, PIN_INPUT, 1) /* (B21) SPI0_CS3 */ J722S_IOPAD(0x01c0, PIN_INPUT, 0) /* (E19) SPI0_D0 */ J722S_IOPAD(0x01c4, PIN_INPUT, 0) /* (E20) SPI0_D1 */ >; bootph-all; }; main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */ J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */ >; bootph-all; }; main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ J722S_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A22) I2C1_SDA */ >; bootph-all; }; main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ J722S_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ >; }; main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ J722S_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ >; bootph-all; }; main_uart5_pins_default: main-uart5-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x0108, PIN_INPUT, 3) /* (J27) UART5_RXD */ J722S_IOPAD(0x010c, PIN_OUTPUT, 3) /* (H27) UART5_TXD */ >; }; vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */ >; bootph-all; }; main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */ J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */ J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ >; bootph-all; }; mdio_pins_default: mdio-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ >; }; ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */ J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */ J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */ J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */ J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */ J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */ J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (L21) OSPI0_D4 */ J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (M26) OSPI0_D5 */ J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (N27) OSPI0_D6 */ J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (M27) OSPI0_D7 */ J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (L22) OSPI0_DQS */ >; bootph-all; }; rgmii1_pins_default: rgmii1-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ >; }; main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */ >; }; main_gpio0_ioexp_intr_pins_default: main-gpio0-ioexp-intr-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x0110, PIN_INPUT, 7) /* (G27) MMC2_DAT1.GPIO0_67 */ >; }; main_dpi_pins_default: main-dpi-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AB23) VOUT0_VSYNC */ J722S_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ J722S_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC26) VOUT0_PCLK */ J722S_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (AC27) VOUT0_DE */ J722S_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (W27) VOUT0_DATA0 */ J722S_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA1 */ J722S_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA2 */ J722S_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W23) VOUT0_DATA3 */ J722S_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA4 */ J722S_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA5 */ J722S_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y26) VOUT0_DATA6 */ J722S_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (Y27) VOUT0_DATA7 */ J722S_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA8 */ J722S_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (AA27) VOUT0_DATA9 */ J722S_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA10 */ J722S_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA11 */ J722S_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA12 */ J722S_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA22) VOUT0_DATA13 */ J722S_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AB26) VOUT0_DATA14 */ J722S_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AB27) VOUT0_DATA15 */ J722S_IOPAD(0x005c, PIN_OUTPUT, 1) /* (U27) GPMC0_AD8.VOUT0_DATA16 */ J722S_IOPAD(0x0060, PIN_OUTPUT, 1) /* (U26) GPMC0_AD9.VOUT0_DATA17 */ J722S_IOPAD(0x0064, PIN_OUTPUT, 1) /* (V27) GPMC0_AD10.VOUT0_DATA18 */ J722S_IOPAD(0x0068, PIN_OUTPUT, 1) /* (V25) GPMC0_AD11.VOUT0_DATA19 */ J722S_IOPAD(0x006c, PIN_OUTPUT, 1) /* (V26) GPMC0_AD12.VOUT0_DATA20 */ J722S_IOPAD(0x0070, PIN_OUTPUT, 1) /* (V24) GPMC0_AD13.VOUT0_DATA21 */ J722S_IOPAD(0x0074, PIN_OUTPUT, 1) /* (V22) GPMC0_AD14.VOUT0_DATA22 */ J722S_IOPAD(0x0078, PIN_OUTPUT, 1) /* (V23) GPMC0_AD15.VOUT0_DATA23 */ J722S_IOPAD(0x009c, PIN_OUTPUT, 1) /* (W26) GPMC0_WAIT1.VOUT0_EXTPCLKIN */ >; }; main_mcan0_pins_default: main-mcan0-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x1dc, PIN_INPUT, 0) /* (C22) MCAN0_RX */ J722S_IOPAD(0x1d8, PIN_OUTPUT, 0) /*(D22) MCAN0_TX */ >; }; main_mcasp1_pins_default: main-mcasp1-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ J722S_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */ J722S_IOPAD(0x008c, PIN_OUTPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */ J722S_IOPAD(0x0084, PIN_INPUT, 2) /* (R25) GPMC0_ADVn_ALE.MCASP1_AXR2 */ >; }; audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ >; }; }; &cpsw3g { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&rgmii1_pins_default>; }; &cpsw3g_mdio { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mdio_pins_default>; cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,min-output-impedance; }; }; &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy0>; }; &cpsw_port2 { status = "disabled"; }; &main_gpio1 { status = "okay"; }; &main_uart0 { pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; status = "okay"; bootph-all; }; &main_uart5 { pinctrl-names = "default"; pinctrl-0 = <&main_uart5_pins_default>; status = "reserved"; }; &mcu_pmx0 { wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ >; bootph-all; }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (C7) WKUP_I2C0_SCL */ J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_I2C1_SDA */ >; bootph-all; }; mcu_mcan0_pins_default: mcu-mcan0-default-pins { pinctrl-single,pins = < J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */ J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (B2) MCU_MCAN0_TX */ >; }; mcu_mcan1_pins_default: mcu-mcan1-default-pins { pinctrl-single,pins = < J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */ J722S_MCU_IOPAD(0x03C, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */ >; }; mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { pinctrl-single,pins = < J722S_MCU_IOPAD(0x0030, PIN_OUTPUT, 7) /* (C3) MCU_GPIO0_12 */ >; }; }; &wkup_uart0 { /* WKUP UART0 is used by Device Manager firmware */ pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; status = "reserved"; bootph-all; }; &wkup_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; status = "okay"; bootph-all; }; &k3_clks { /* Configure AUDIO_EXT_REFCLK1 pin as output */ pinctrl-names = "default"; pinctrl-0 = <&audio_ext_refclk1_pins_default>; }; &main_spi0 { pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; status = "okay"; spidev@0 { spi-max-frequency=<24000000>; reg = <0>; compatible = "linux,spidev"; }; }; &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; status = "okay"; bootph-all; exp1: gpio@23 { compatible = "ti,tca6424"; reg = <0x23>; gpio-controller; #gpio-cells = <2>; gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL", "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#", "CSI_VIO_SEL", "USB2.0_MUX_SEL", "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2", "LMK1_OE1", "LMK1_OE0", "LMK2_OE0", "LMK2_OE1", "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN", "USER_LED2", "MCAN0_STB", "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; p01_hog: p01-hog { /* P01 - TRC_MUX_SEL */ gpio-hog; gpios = <0 GPIO_ACTIVE_HIGH>; output-low; line-name = "TRC_MUX_SEL"; }; p02_hog: p02-hog { /* P02 - MCASP1_FET_SEL */ gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; output-high; line-name = "MCASP1_FET_SEL"; }; p05-hog { /* P05 - USB2.0_MUX_SEL */ gpio-hog; gpios = <5 GPIO_ACTIVE_LOW>; output-high; }; p13_hog: p13-hog { /* P13 - GPIO_AUD_RSTn */ gpio-hog; gpios = <13 GPIO_ACTIVE_HIGH>; output-high; line-name = "GPIO_AUD_RSTn"; }; }; tlv320aic3106: audio-codec@1b { #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x1b>; ai3x-micbias-vg = <1>; /* 2.0V */ AVDD-supply = <&vcc_3v3_aud>; IOVDD-supply = <&vcc_3v3_aud>; DRVDD-supply = <&vcc_3v3_aud>; DVDD-supply = <&vsys_io_1v8>; }; }; &main_i2c1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <100000>; exp2: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; gpio-line-names = "DSI_Mux_SEL_2", "GPIO_eDP_ENABLE", "DP0_PWR_SW_EN", "GPIO_OLDI_RSTn", "GPIO_HDMI_RSTn", "HDMI_LS_OE", "", "", "DSI_GPIO0", "DSI_GPIO1", "DSI_EDID", "IO_eDP_IRQ", "OLDI_INT#", "HDMI_INTn", "", ""; interrupt-parent = <&main_gpio0>; interrupts = <67 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&main_gpio0_ioexp_intr_pins_default>; bootph-all; p04-hog { /* P04 - GPIO_HDMI_RSTn */ gpio-hog; gpios = <4 GPIO_ACTIVE_LOW>; output-low; line-name = "GPIO_HDMI_RSTn"; }; p03-hog { /* P03 - GPIO_OLDI_RSTn */ gpio-hog; gpios = <3 GPIO_ACTIVE_LOW>; output-low; line-name = "GPIO_OLDI_RSTn"; }; p05-hog { /* P05 - HDMI_LS_OE */ gpio-hog; gpios = <5 GPIO_ACTIVE_HIGH>; output-high; line-name = "HDMI_LS_OE"; }; }; sii9022: bridge-hdmi@3b { compatible = "sil,sii9022"; reg = <0x3b>; interrupt-parent = <&exp2>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; #sound-dai-cells = <0>; sil,i2s-data-lanes = < 0 >; hdmi_tx_ports: ports { #address-cells = <1>; #size-cells = <0>; /* * HDMI can be serviced with 3 potential VPs - * (DSS0 VP1 / DSS1 VP0 / DSS1 VP1). * For now, we will service it with DSS1 VP0. */ port@0 { reg = <0>; sii9022_in: endpoint { remote-endpoint = <&dss1_dpi0_out>; }; }; port@1 { reg = <1>; sii9022_out: endpoint { remote-endpoint = <&hdmi_connector_in>; }; }; }; }; }; &main_i2c2 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c2_pins_default>; clock-frequency = <400000>; pca9543_0: i2c-mux@70 { compatible = "nxp,pca9543"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; }; pca9543_1: i2c-mux@71 { compatible = "nxp,pca9543"; #address-cells = <1>; #size-cells = <0>; reg = <0x71>; }; }; &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; status = "okay"; ospi0_nor: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <25000000>; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; bootph-all; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi.tiboot3"; reg = <0x00 0x80000>; }; partition@80000 { label = "ospi.tispl"; reg = <0x80000 0x200000>; }; partition@280000 { label = "ospi.u-boot"; reg = <0x280000 0x400000>; }; partition@680000 { label = "ospi.env"; reg = <0x680000 0x40000>; }; partition@6c0000 { label = "ospi.env.backup"; reg = <0x6c0000 0x40000>; }; partition@800000 { label = "ospi.rootfs"; reg = <0x800000 0x37c0000>; }; partition@3fc0000 { label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; }; }; }; ospi0_nand: nand@0 { compatible = "spi-nand"; reg = <0x0>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <25000000>; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <2>; #address-cells = <1>; #size-cells = <1>; status = "disabled"; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi_nand.tiboot3"; reg = <0x0 0x80000>; }; partition@80000 { label = "ospi_nand.tispl"; reg = <0x80000 0x200000>; }; partition@280000 { label = "ospi_nand.u-boot"; reg = <0x280000 0x400000>; }; partition@680000 { label = "ospi_nand.env"; reg = <0x680000 0x40000>; }; partition@6c0000 { label = "ospi_nand.env.backup"; reg = <0x6c0000 0x40000>; }; partition@2000000 { label = "ospi_nand.rootfs"; reg = <0x2000000 0x5fc0000>; }; partition@7fc0000 { label = "ospi_nand.phypattern"; reg = <0x7fc0000 0x40000>; }; }; }; }; &sdhci0 { disable-wp; bootph-all; ti,driver-strength-ohm = <50>; status = "okay"; }; &sdhci1 { /* SD/MMC */ vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; disable-wp; status = "okay"; bootph-all; }; &mailbox0_cluster0 { status = "okay"; mbox_r5_0: mbox-r5-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; }; }; &mailbox0_cluster1 { status = "okay"; mbox_mcu_r5_0: mbox-mcu-r5-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; }; }; &mailbox0_cluster2 { status = "okay"; mbox_c7x_0: mbox-c7x-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; }; }; &mailbox0_cluster3 { status = "okay"; mbox_main_r5_0: mbox-main-r5-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; }; mbox_c7x_1: mbox-c7x-1 { ti,mbox-rx = <2 0 0>; ti,mbox-tx = <3 0 0>; }; }; &main_timer0 { status = "reserved"; }; &main_timer1 { status = "reserved"; }; &main_timer2 { status = "reserved"; }; &wkup_r5fss0 { status = "okay"; }; &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; }; &mcu_r5fss0 { status = "okay"; }; &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &main_r5fss0 { status = "okay"; }; &main_r5fss0_core0 { mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &c7x_0 { status = "okay"; mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; memory-region = <&c7x_0_dma_memory_region>, <&c7x_0_memory_region>; }; &c7x_1 { status = "okay"; mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; memory-region = <&c7x_1_dma_memory_region>, <&c7x_1_memory_region>; }; &serdes_ln_ctrl { idle-states = <J722S_SERDES0_LANE0_USB>, <J722S_SERDES1_LANE0_PCIE0_LANE0>; }; &serdes0 { status = "okay"; serdes0_usb_link: phy@0 { reg = <0>; cdns,num-lanes = <1>; #phy-cells = <0>; cdns,phy-type = <PHY_TYPE_USB3>; resets = <&serdes_wiz0 1>; }; }; &serdes1 { serdes1_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <1>; #phy-cells = <0>; cdns,phy-type = <PHY_TYPE_PCIE>; resets = <&serdes_wiz1 1>; }; }; &usbss0 { ti,vbus-divider; status = "okay"; }; &usb0 { dr_mode = "otg"; usb-role-switch; }; &usbss1 { pinctrl-names = "default"; pinctrl-0 = <&main_usb1_pins_default>; ti,vbus-divider; status = "okay"; }; &usb1 { dr_mode = "host"; maximum-speed = "super-speed"; phys = <&serdes0_usb_link>; phy-names = "cdns3,usb3-phy"; }; &pcie0_rc { status = "okay"; reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>; phys = <&serdes1_pcie_link>; phy-names = "pcie-phy"; }; &dss1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_dpi_pins_default>; clocks = <&k3_clks 232 8>, <&k3_clks 232 0>, <&k3_clks 232 4>; assigned-clocks = <&k3_clks 241 0>, /* DSS1-VP0 */ <&k3_clks 240 0>, /* DSS1-VP1 */ <&k3_clks 245 0>; /* DPI Output */ assigned-clock-parents = <&k3_clks 241 2>, /* PLL 17 HDMI */ <&k3_clks 240 1>, /* PLL 18 DSI */ <&k3_clks 245 2>; /* DSS1-DPI0 */ }; &dss1_ports { /* DSS1-VP0: DPI/HDMI Output */ port@0 { reg = <0>; dss1_dpi0_out: endpoint { remote-endpoint = <&sii9022_in>; }; }; }; &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_mcan0_pins_default>; phys = <&transceiver0>; }; &mcu_mcan1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_mcan1_pins_default>; phys = <&transceiver1>; }; &main_mcan0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan0_pins_default>; phys = <&transceiver2>; }; &mcu_gpio0 { status = "okay"; }; &mcasp1 { status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&main_mcasp1_pins_default>; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 >; }; &main_conf { audio_refclk1: clock@82e4 { compatible = "ti,am62-audio-refclk"; reg = <0x82e4 0x4>; clocks = <&k3_clks 157 18>; assigned-clocks = <&k3_clks 157 18>; assigned-clock-parents = <&k3_clks 157 33>; #clock-cells = <0>; }; };
Pins correspond to SPI0 on the J722S. I have checked that these pins are not in conflict with any others in the .dts.
Device tree node (k3-j722s-main.dtsi, line 26):
// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the J722S main domain peripherals * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/phy/phy-cadence.h> #include <dt-bindings/phy/phy-ti.h> /* * USB1 controller on AM62P and J722S are of different IP. * Delete AM62P's USBSS1 node definition and redefine it for J722S. */ /delete-node/ &usbss1; / { serdes_refclk: clk-0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; }; &cbass_main { main_spi0: spi@20100000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x20100000 0x00 0x400>; interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 141 1>; power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; }; serdes_wiz0: phy@f000000 { compatible = "ti,am64-wiz-10g"; ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; num-lanes = <1>; #reset-cells = <1>; #clock-cells = <1>; assigned-clocks = <&k3_clks 279 1>; assigned-clock-parents = <&k3_clks 279 5>; serdes0: serdes@f000000 { compatible = "ti,j721e-serdes-10g"; reg = <0x0f000000 0x00010000>; reg-names = "torrent_phy"; resets = <&serdes_wiz0 0>; reset-names = "torrent_reset"; clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; clock-names = "refclk", "phy_en_refclk"; assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; assigned-clock-parents = <&k3_clks 279 1>, <&k3_clks 279 1>, <&k3_clks 279 1>; #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; status = "disabled"; /* Needs lane config */ }; }; serdes_wiz1: phy@f010000 { compatible = "ti,am64-wiz-10g"; ranges = <0x0f010000 0x0 0x0f010000 0x00010000>; #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; num-lanes = <1>; #reset-cells = <1>; #clock-cells = <1>; assigned-clocks = <&k3_clks 280 1>; assigned-clock-parents = <&k3_clks 280 5>; serdes1: serdes@f010000 { compatible = "ti,j721e-serdes-10g"; reg = <0x0f010000 0x00010000>; reg-names = "torrent_phy"; resets = <&serdes_wiz1 0>; reset-names = "torrent_reset"; clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; clock-names = "refclk", "phy_en_refclk"; assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; assigned-clock-parents = <&k3_clks 280 1>, <&k3_clks 280 1>, <&k3_clks 280 1>; #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; }; }; pcie0_rc: pcie@f102000 { compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host"; reg = <0x00 0x0f102000 0x00 0x1000>, <0x00 0x0f100000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, <0x00 0x68000000 0x00 0x00001000>; reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; interrupt-names = "link_state"; interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>; device_type = "pci"; max-link-speed = <3>; num-lanes = <1>; power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; clock-names = "fck", "pcie_refclk"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0xff>; vendor-id = <0x104c>; device-id = <0xb010>; cdns,no-bar-match-nbits = <64>; ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; msi-map = <0x0 &gic_its 0x0 0x10000>; status = "disabled"; }; usbss1: usb@f920000 { compatible = "ti,j721e-usb"; reg = <0x00 0x0f920000 0x00 0x100>; power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 278 3>, <&k3_clks 278 1>; clock-names = "ref", "lpm"; assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */ assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */ #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; usb1: usb@31200000{ compatible = "cdns,usb3"; reg = <0x00 0x31200000 0x00 0x10000>, <0x00 0x31210000 0x00 0x10000>, <0x00 0x31220000 0x00 0x10000>; reg-names = "otg", "xhci", "dev"; interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ interrupt-names = "host", "peripheral", "otg"; maximum-speed = "super-speed"; dr_mode = "otg"; }; }; ti_csi2rx1: ticsi2rx@30122000 { compatible = "ti,j721e-csi2rx-shim"; dmas = <&main_bcdma_csi 0 0x5100 0>, <&main_bcdma_csi 0 0x5101 0>, <&main_bcdma_csi 0 0x5102 0>, <&main_bcdma_csi 0 0x5103 0>; dma-names = "rx0", "rx1", "rx2", "rx3"; reg = <0x00 0x30122000 0x00 0x1000>; power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; cdns_csi2rx1: csi-bridge@30121000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30121000 0x00 0x1000>; clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>, <&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; phys = <&dphy1>; phy-names = "dphy"; ports { #address-cells = <1>; #size-cells = <0>; csi1_port0: port@0 { reg = <0>; status = "disabled"; }; csi1_port1: port@1 { reg = <1>; status = "disabled"; }; csi1_port2: port@2 { reg = <2>; status = "disabled"; }; csi1_port3: port@3 { reg = <3>; status = "disabled"; }; csi1_port4: port@4 { reg = <4>; status = "disabled"; }; }; }; }; ti_csi2rx2: ticsi2rx@30142000 { compatible = "ti,j721e-csi2rx-shim"; dmas = <&main_bcdma_csi 0 0x5200 0>, <&main_bcdma_csi 0 0x5201 0>, <&main_bcdma_csi 0 0x5202 0>, <&main_bcdma_csi 0 0x5203 0>; dma-names = "rx0", "rx1", "rx2", "rx3"; reg = <0x00 0x30142000 0x00 0x1000>; power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; cdns_csi2rx2: csi-bridge@30141000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30141000 0x00 0x1000>; clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>, <&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; phys = <&dphy2>; phy-names = "dphy"; ports { #address-cells = <1>; #size-cells = <0>; csi2_port0: port@0 { reg = <0>; status = "disabled"; }; csi2_port1: port@1 { reg = <1>; status = "disabled"; }; csi2_port2: port@2 { reg = <2>; status = "disabled"; }; csi2_port3: port@3 { reg = <3>; status = "disabled"; }; csi2_port4: port@4 { reg = <4>; status = "disabled"; }; }; }; }; ti_csi2rx3: ticsi2rx@30162000 { compatible = "ti,j721e-csi2rx-shim"; dmas = <&main_bcdma_csi 0 0x5300 0>, <&main_bcdma_csi 0 0x5301 0>, <&main_bcdma_csi 0 0x5302 0>, <&main_bcdma_csi 0 0x5303 0>; dma-names = "rx0", "rx1"; reg = <0x00 0x30162000 0x00 0x1000>; power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; cdns_csi2rx3: csi-bridge@30161000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30161000 0x00 0x1000>; clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>, <&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; phys = <&dphy3>; phy-names = "dphy"; ports { #address-cells = <1>; #size-cells = <0>; csi3_port0: port@0 { reg = <0>; status = "disabled"; }; csi3_port1: port@1 { reg = <1>; status = "disabled"; }; csi3_port2: port@2 { reg = <2>; status = "disabled"; }; csi3_port3: port@3 { reg = <3>; status = "disabled"; }; csi3_port4: port@4 { reg = <4>; status = "disabled"; }; }; }; }; dphy1: phy@30130000 { compatible = "cdns,dphy-rx"; reg = <0x00 0x30130000 0x00 0x1100>; #phy-cells = <0>; power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; dphy2: phy@30150000 { compatible = "cdns,dphy-rx"; reg = <0x00 0x30150000 0x00 0x1100>; #phy-cells = <0>; power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; dphy3: phy@30170000 { compatible = "cdns,dphy-rx"; reg = <0x00 0x30170000 0x00 0x1100>; #phy-cells = <0>; power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; main_r5fss0: r5fss@78400000 { compatible = "ti,am62-r5fss"; #address-cells = <1>; #size-cells = <1>; ranges = <0x78400000 0x00 0x78400000 0x8000>, <0x78500000 0x00 0x78500000 0x8000>; power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; main_r5fss0_core0: r5f@78400000 { compatible = "ti,am62-r5f"; reg = <0x78400000 0x00008000>, <0x78500000 0x00008000>; reg-names = "atcm", "btcm"; ti,sci = <&dmsc>; ti,sci-dev-id = <262>; ti,sci-proc-ids = <0x04 0xff>; resets = <&k3_reset 262 1>; firmware-name = "j722s-main-r5f0_0-fw"; ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; }; }; c7x_0: dsp@7e000000 { compatible = "ti,j722s-c7xv-dsp"; reg = <0x00 0x7e000000 0x00 0x00200000>; reg-names = "l2sram"; ti,sci = <&dmsc>; ti,sci-dev-id = <208>; ti,sci-proc-ids = <0x30 0xff>; resets = <&k3_reset 208 1>; firmware-name = "j722s-c71_0-fw"; status = "disabled"; }; c7x_1: dsp@7e200000 { compatible = "ti,j722s-c7xv-dsp"; reg = <0x00 0x7e200000 0x00 0x00200000>; reg-names = "l2sram"; ti,sci = <&dmsc>; ti,sci-dev-id = <268>; ti,sci-proc-ids = <0x31 0xff>; resets = <&k3_reset 268 1>; firmware-name = "j722s-c71_1-fw"; status = "disabled"; }; }; /* MCU domain overrides */ &mcu_r5fss0_core0 { firmware-name = "j722s-mcu-r5f0_0-fw"; }; /* Wakeup domain overrides */ &wkup_r5fss0_core0 { firmware-name = "j722s-wkup-r5f0_0-fw"; }; &main_conf { serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x4080 0x14>; #mux-control-cells = <1>; mux-reg-masks = <0x0 0x3>, /* SERDES0 lane0 select */ <0x10 0x3>; /* SERDES1 lane0 select */ }; }; &wkup_conf { pcie0_ctrl: pcie0-ctrl@4070 { compatible = "ti,j784s4-pcie-ctrl", "syscon"; reg = <0x4070 0x4>; }; };
The parameters have been updated according to the J722S TRM and TISCI.
2. I added a spidev node inside the SPI- node as shown below (k3-j722s-evm.dts, line 561):
&main_spi0 { pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; status = "okay"; spidev@0 { spi-max-frequency=<24000000>; reg = <0>; compatible = "linux,spidev"; }; };
3. I enabled CONFIG_SPI_SPIDEV=y in arch/arm64/configs/defconfig. CONFIG_SPI_OMAP24XX=y by default.
Problem
When I make the SDK with these changes and boot Linux, spidev does not show, just spi_master (spi1). I'm not sure what the spi0 is doing there, but I see it on the default image as well.
I commented out all the other .dtbo for J722S besides k3-j722s-evm.dtb and make, but no difference in output.
# Boards with J722s SoC dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb #dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-ov5640.dtbo #dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo #dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo #dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-dsi-rpi-7inch-panel.dtbo #dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-fpdlink-fusion.dtbo #dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-microtips-mf101hie-panel.dtbo #dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-v3link-fusion.dtbo #dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-pwm.dtbo #dtb-$(CONFIG_ARCH_K3) += k3-j722s-vision-apps.dtbo #dtb-$(CONFIG_ARCH_K3) += k3-j722s-edgeai-apps.dtbo
Could you advise?
Thank you,
Jin
Hi Jin,
+&main_spi5 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&main_spi5_pins_default>; + pinctrl-names = "default"; + spidev@0 { + spi-max-frequency = <24000000>; + reg = <0>; + compatible = "rohm,dh2228fv"; + }; +};
compatible = "rohm,dh2228fv";
Can you try the above?
- Keerthy