TDA4VH-Q1: vpac1 very slow after Ethernet firmware disabling

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Tool/software:

Hi

We are experiencing a slowdown in vpac1 (but not vpac2) by an order of magnitude when running our application on Tda4VH.
This happens after applying a fix to enable HDMI monitor usage.

Our sdk is 09.02.05 with some modifications provided by you:
c7x-mma-tidl_j784s4_10_00_05_00, mmalib_obj_C7120_10_00_00_09.

The fix we've applied is located at the following file:

sdk_builder/vision_apps_build_flags.mak line: 116

ifeq ($(RTOS),SAFERTOS)
ifeq ($(SOC),j784s4)
BUILD_ENABLE_ETHFW=no
endif
endif

We have removed the first ifeq (setting BUILD_ENABLE_ETHFW to no).

We would like to understand what is the correlation between VPAC1 to the module, and would like to have you assistance in solving our issue.

Thanks in advance,
Oren


  • Hi Oren,

    Do you mean you are seeing issue of slowness in VPAC1 when enabling EthFw? The only reason i can think of is because they both are running from the same core.. but are you using any EthFw functionality? 

    Regards,

    Brijesh

  • when the EthFw is off, we are seeing slowness of VPAC1.
    we are not using a EthFw functionality.

    Thanks,
    Oren

  • Hi Oren,

    That's strange, when what happens when EthFw is on? Does it run fine? 

    Regards,

    Brijesh

  • EthFw off -> vpac1 slower then vpac2.
    EthFw on -> vpac1 as fast as vpac2.

    Thanks

  • Hi oran,

    This does not explain. If EthFw is off, there is nothing which can affect vpac1 performance. When you vpac1 is slower than vpac2, how much is it slower? Is the resolution and other parameters are same for vpac1 and vpac2? Are you using Ethernet from mcu2_0? 

    Regards,

    Brijesh

  • Hi Brijesh,

    I am a colleague of Oren. I observed the same slowness of vpac1 when ETHFW disabled in R5 firmware in my TDA4Vh setup too (I don't have the expansion Ethernet board at all in my setup).

    I dumped clock tree to compare the difference between enabled and disabled ETHFW in A72 side.

    I noticed that the clock source configured for main_cpsw0@c000000 are different, 500 MHz and 250 MHz, when enabled and disabled ETHFW, respectively (see below screenshot).

    Is there clocking any relation between the main_cpsw0 and vpac1? Why does the ETHFW impact the vpac1 performance?


    Does the system controller behave differently when configure vpac1 and vpac2?

    Thanks,

    Minh

  • Hi Minh,

    It should not be, but can we please readback the clock configured for VPAC1 and confirm it to be running at 720MHz? You can use SciClient interface to get the clock for VPAC1.

    Regards,

    Brijesh

  • Hi Brijesh,

    Can you share the sciclient command to read back the clock configured to vpac1 and vpac2?

    Also, why does ETHFW has an impact to change the parent clock of main_cpsw0@c000000  in A72 side?

    Thanks,

    Minh

  • Hi Minh,

    No, EthFw should not have impact on VPAC performance and that reducing it when EthFw is not running.. This is very strange. 

    Can you please use 

    Sciclient_pmGetModuleClkFreq(TISCI_DEV_VPAC0, TISCI_DEV_VPAC0_MAIN_CLK, &freq);

    to get VPAC0 frequency in freq variable? 

    Similar mechanism can be used to get even VPAC1 frequency. 

    Regards,

    Brijesh